Download Parallel Wafer Level Reliability (WLR) Basics

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Parallel Wafer Level Reliability (WLR) Basics
Paul Meyer
Senior Staff Technologist,
Semiconductor Measurements Group
Keithley Instruments, Inc.
Email: [email protected]
[email protected]
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G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
www.keithley.com
Seminar Outline
•
•
•
•
•
•
•
Motivation
Traditional WLR Practices
Traditional WLR Structures
Parallel WLR Capabilities
Benefits of Parallel over Sequential
Advanced Practices
Summary
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G R E A T E R
M E A S U R E
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C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
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Motivation
• More wafer level reliability (WLR) testers are being pressed
to their limits in throughput
– Increasingly restrictive automotive and mobile standards
– High levels of integration for System On a Chip (SOC)
– Ultra-thin oxides for deeply scaled silicon
• The use of gang (or parallel) stress and sequential
characterization techniques offers opportunities for some
improvement in throughput
– Larger number of samples (DUT) in a single touchdown
• Substantial throughput improvements will require greater
parallel testing capabilities
– More stress conditions per touchdown = acceleration factor in a
single touchdown
– Parallel measurement = faster test and tighter stress control
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G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
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WLR Includes Both Fast WLR and Standard WLR
•
Fast WLR (fWLR) is used to
monitor a process after
qualification
fWLR
•
Stress
– fWLR uses the highest possible
stress for the shortest possible
test time
WLR is used for process
integration, technology
development, and materials
research
WLR
– WLR uses lower stress to
selectively activate specific
degradation mechanisms
•
PLR
PLR (Package Level
Reliability) used for long term
testing
Time
– Parts are diced and packaged
(long cycle time)
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G R E A T E R
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C O N F I D E N C E
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Benefits of fWLR in Production
•
No chip packaging required,
unlike package level reliability
(PLR)
– Reduced risk of DUT damage
– No long test chip packaging cycles
•
Test results in real time
– Immediate feedback for process
control
•
•
Easy to correlate results to
process tools, chambers, etc.
Product chips can still be shipped
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G R E A T E R
M E A S U R E
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C O N F I D E N C E
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Benefits of WLR in Process Integration,
Technology Development, etc.
•
•
•
•
Test wafers can have
hundreds of WLR DUTs for
large statistical samples
DUT layout and stress bias
conditions can work together
to select one specific
degradation mechanism
WLR results in minutes or
hours – not weeks for PLR
Reduces time to market by
allowing a wide range of
materials and process
variations to be tested quickly
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G R E A T E R
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C O N F I D E N C E
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Traditional Practices
• Stress Requirements
• System Configuration
• Limitations
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C O N F I D E N C E
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Stress Conditions
Depends on mechanism to be tested
– Temperature: Most every WLR test is performed at
an elevated temperature between 30C and 600C
• Hot Chuck – heats entire wafer up to 300C
• Poly Heaters – integrated into DUT for up to 600C
– Stress Bias Voltages
• Used for insulator integrity and device reliability
• Between 1V and several hundred volts depending on
materials and thickness
• Source precision helps determine voltage acceleration
factors more accurately
• Single source can be used for gang stress
– Stress Bias Current
• Used for electromigration of metal lines and vias as well
as some BJT tests
• Between 1mA and 1A depending on structure and
device
• Cannot be used for gang stress
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G R E A T E R
M E A S U R E
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C O N F I D E N C E
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Traditional WLR Test System Configuration
Test Instruments
– 4 to 6 Source Measure Units
(SMUs)
Mainframe
•
• 2 Low Power SMUs
• 2  High Power SMUs
SMU 1
SMU 2
SMU 3
SMU 4
SMU 5
SMU 6
SMU 7
SMU 8
8
8xM Switch
Matrix
M
Prober with Hot Chuck
– Switch matrix
• Multiplex between DUTs for test
• Fan-out Bias Stress Voltage to
multiple DUTs
•
4200-SCS
Parametric
Analyzer
Hot Chuck
– Up to 300C
•
Probe Card
707A
Switch
Matrix
– Up to 300C
– Many tests below 150C
– Single site
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G R E A T E R
M E A S U R E
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C O N F I D E N C E
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Traditional WLR Test System Configuration
Test Instruments
– 4 to 6 Source Measure Units
(SMUs)
Mainframe
•
• 2X Low Power SMUs
• 2X High Power SMUs
SMU 1
SMU 2
SMU 3
SMU 4
SMU 5
SMU 6
SMU 7
SMU 8
8
8xM Switch
Matrix
M
Prober with Hot Chuck
– Switch matrix
• Multiplex between DUTs for test
• Fan-out Bias Stress Voltage to
multiple DUTs
•
•
Hot Chuck
– Up to 300C
Probe Card
– Up to 300C
– Many tests below 150C
– Single site
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G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
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Traditional WLR Test System Configuration
Test Instruments
– 4 to 6 Source Measure Units
(SMUs)
Mainframe
•
• 2X Low Power SMUs
• 2X High Power SMUs
SMU 1
SMU 2
SMU 3
SMU 4
SMU 5
SMU 6
SMU 7
SMU 8
8
8xM Switch
Matrix
M
Prober with Hot Chuck
– Switch matrix
• Multiplex between DUTs for test
• Fan-out Bias Stress Voltage to
multiple DUTs
•
Hot Chuck
– Up to 300C
•
Single-Site Probe
– Up to 300C
– Many tests below 150C
– Single site
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C O N F I D E N C E
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Traditional WLR Test System Limitations
•
Only one DUT can be
characterized at a time
•
The number of stress
conditions is limited by the
number of SMUs
•
Stress cycles shorter than the
sum of the sequential test
times are pointless
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G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
www.keithley.com
Traditional WLR Test System Limitations
•
Only one DUT can be
characterized at a time
•
The number of stress
conditions is limited by the
number of SMUs
•
Stress cycles shorter than the
sum of the sequential test
times are pointless
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
www.keithley.com
Traditional WLR Test System Limitations
Measure
Switch
Switch
VST1
TST1
Stress 1 (no readings)
V = 0V
DUT #2
VST2 = VST1
Measure
Switch
Stress 2 (no readings)
TST2
DUT #N
VSTN = VST1
Measure
Measure
Switch
V = 0V
Switch
The number of stress
conditions is limited by the
number of SMUs
V = 0V
DUT #1
Switch
•
Only one DUT can be
characterized at a time
Voltage applied to DUT pin
•
Stress N
TST3
Stress (no readings)
Time
•
Stress cycles shorter than the
sum of the sequential test
times are pointless
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G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
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Traditional WLR Structures
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G R E A T E R
M E A S U R E
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C O N F I D E N C E
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Test Element Groups in the Kerf
•
WLR test structures are
grouped into Test Element
Groups or TEGs and placed
in kerf (dicing lanes) to
reduce cost
– No additional cost to producing
wafer
– Does not interfere with product
chips
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G R E A T E R
M E A S U R E
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C O N F I D E N C E
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Only 20 to 32 Pads Typical
• WLR TEGs typically have 20 to 32 pads, which can support
up to:
–
–
–
–
5 to 8 FET structures for HCI, BTI, etc.
20 to 32 Capacitors for TDDB, JRAMP, VRAMP, etc.
2 to 4 Mobile Ion structures
5 to 8 Electromigration structures
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C O N F I D E N C E
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Standardized Across Many Products
• The TEG pad layout is standardized within a fab to:
– Reduce the number of probe card types
– Simplify wafer layout
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G R E A T E R
M E A S U R E
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C O N F I D E N C E
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Parallel WLR Capabilities
 Simple throughput improvements
 Using existing test structures
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G R E A T E R
M E A S U R E
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C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
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Low Hanging Fruit
•
Simply testing two structures in parallel
can greatly improve throughput. Here is
an example from the Technology
Development (TD) lab:
–
–
–
–
–
–
•
•
HCI test takes 100 seconds per device
There are six structures per TEG
Nine TEGs across a wafer will be tested
Five wafers per lot will be tested
Serial test requires 7.5 hours
Parallel (two structures at a time) test
requires 3.75 hours
Just testing two devices at once saves
more than 3 hours of system test time
Testing six devices at once saves more
than 6 hours of time!
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G R E A T E R
M E A S U R E
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C O N F I D E N C E
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Using Existing Structures to Reduce Cost and Risk
•
•
•
Many existing WLR structures are
suitable for parallel WLR testing
A single site typically has several
elements that can be tested in parallel
Benefits of using existing structures
and testing all the elements in a
group:
- Use of existing probe cards can
provide significant speed
improvement
- Single site – no new multi-site
probe card technology required
- No GDSII or reticle changes
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G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
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What Is Required to Go Parallel?
There are two basic strategies
Mainframe
– Gang stress – sequential measure (using a switch matrix)
SMU 1
SMU 2
SMU 3
SMU 4
SMU 5
SMU 6
SMU 7
SMU 8
8xM Switch
Matrix
8
M
Prober with Hot Chuck
– SMU-per-pin without a switch matrix (all SMUs are high power!)
SMU 1
SMU 2
SMU 3
SMU 4
SMU 5
36
Prober with Hot Chuck
Mainframe
•
SMU 35
SMU 36
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C O N F I D E N C E
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Benefits of Parallel over Sequential WLR
• Limitations of gang stress – sequential
measure
• Benefits of SMU-per-pin
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G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
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Major Limitations of Gang Stress – Sequential Measure
•
There are five major problems with gang stress –
sequential measure
1. The number of “voltage splits” is limited by the number of SMUs
available for stress. May make extracting acceleration factor
difficult in a single touchdown
2. Difficult to control stress timing – especially with so-called
“Quasi-per-pin” methodologies
3. Structures cannot be monitored when they are under stress –
meaning that transient events cannot be captured and that one
catastrophic structure failure can ruin the entire touchdown’s
results
4. Relaxation between stress and measure can be detrimental to
certain tests that involve ultra-thin gate oxide, such as BTI and HCI
5. Some tests require a current source per structure and are not
conducive to gang stress, such as electromigration
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
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Major Limitation of Gang Stress – Sequential Measure
4
Device Relaxation
3
Missed Event (no readings during stress)
Switch
Measure
i
ry
ng
Stress 2 (no readings)
s
re
St
TST2
Measure
Switch
Switch
DUT #2
VST2 = VST1
Stress 1 (no readings)
V = 0V
Va
s
Measure
Measure
Switch
es
DUT #N
VSTN = VST1 1
V = 0V
2
Switch
m
Ti
Voltage applied to DUT pin
VST1
TST1
Switch
V = 0V
DUT #1
Stress N
TST3
Stress (no readings)
Time
The number of “voltage splits” is limited by the
number of SMUs available for stress. May make
extracting acceleration factor difficult in a single
touchdown
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
www.keithley.com
Major Limitation of Gang Stress – Sequential Measure
4
Device Relaxation
3
Missed Event (no readings during stress)
Switch
Measure
i
ry
ng
Stress 2 (no readings)
s
re
St
TST2
Measure
Switch
Switch
DUT #2
VST2 = VST1
Stress 1 (no readings)
V = 0V
Va
s
Measure
Measure
Switch
es
DUT #N
VSTN = VST1 1
V = 0V
2
Switch
m
Ti
Voltage applied to DUT pin
VST1
TST1
Switch
V = 0V
DUT #1
Stress N
TST3
Stress (no readings)
Time
Difficult to control stress timing – especially with socalled “Quasi-per-pin” methodologies
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
www.keithley.com
Major Limitation of Gang Stress – Sequential Measure
4
Device Relaxation
3
Missed Event (no readings during stress)
Switch
Measure
i
ry
ng
Stress 2 (no readings)
s
re
St
TST2
Measure
Switch
Switch
DUT #2
VST2 = VST1
Stress 1 (no readings)
V = 0V
Va
s
Measure
Measure
Switch
es
DUT #N
VSTN = VST1 1
V = 0V
2
Switch
m
Ti
Voltage applied to DUT pin
VST1
TST1
Switch
V = 0V
DUT #1
Stress N
TST3
Stress (no readings)
Time
Structures cannot be monitored when they are under stress –
meaning that transient events cannot be captured and that one
catastrophic structure failure can ruin the entire touchdown’s results
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
www.keithley.com
Major Limitation of Gang Stress – Sequential Measure
4
Device Relaxation
3
Missed Event (no readings during stress)
Switch
Measure
i
ry
ng
Stress 2 (no readings)
s
re
St
TST2
Measure
Switch
Switch
DUT #2
VST2 = VST1
Stress 1 (no readings)
V = 0V
Va
s
Measure
Measure
Switch
es
DUT #N
VSTN = VST1 1
V = 0V
2
Switch
m
Ti
Voltage applied to DUT pin
VST1
TST1
Switch
V = 0V
DUT #1
Stress N
TST3
Stress (no readings)
Time
Relaxation between stress and measure can be
detrimental to certain tests that involve ultra-thin
gate oxide, such as BTI and HCI
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
www.keithley.com
Major Limitations of Gang Stress – Sequential Measure
•
There are five major problems with gang stress –
sequential measure
1. The number of “voltage splits” is limited by the number of SMUs
available for stress. May make extracting acceleration factor
difficult in a single touchdown
2. Difficult to control stress timing – especially with so-called
“Quasi-per-pin” methodologies
3. Structures cannot be monitored when they are under stress –
meaning that transient events cannot be captured and that one
catastrophic structure failure can ruin the entire touchdown’s
results
4. Relaxation between stress and measure can be detrimental to
certain tests that involve ultra-thin gate oxide, such as BTI and HCI
5. Some tests require a current source per structure and are not
conducive to gang stress, such as electromigration
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
www.keithley.com
Benefits of SMU-per-Pin
A
G R E A T E R
SMU 1
SMU 2
SMU 3
SMU 4
SMU 5
36
Prober with Hot Chuck
Mainframe
1. Current source per pin
2. Current limit per structure –
minimizes collateral damage that
may accompany breakdown
3. Test all structures – even
complex structures like mobile
ion structures with poly heaters
and metal temperature lines
4. As many splits as there are
structures
5. Tight control of stress timing
6. No missed transient events
7. No relaxation between stress
and test
M E A S U R E
SMU 35
SMU 36
OF
C O N F I D E N C E
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www.keithley.com
Voltage applied to DUT pin
Benefits of SMU-per-Pin
VST1
Measure
Stress
(with readings)
TST1b
TST1a
VST2
Measure
Stress
(with readings)
Measure
Stress
(with readings)
TST2a
TST2b
VSTN
Stress
(with readings)
Measure
Measure
Measure
Stress
(with readings)
Stress
(with readings)
TSTNb
Stress (with readings)
TSTNa
Measure
Time
As many splits as there are structures
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
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Voltage applied to DUT pin
Benefits of SMU-per-Pin
VST1
Measure
Stress
(with readings)
TST1b
TST1a
VST2
Measure
Stress
(with readings)
Measure
Stress
(with readings)
TST2a
TST2b
VSTN
Stress
(with readings)
Measure
Measure
Measure
Stress
(with readings)
Stress
(with readings)
TSTNb
Stress (with readings)
TSTNa
Measure
Time
Tight control of stress timing
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
www.keithley.com
Voltage applied to DUT pin
Benefits of SMU-per-Pin
VST1
Measure
Stress
(with readings)
TST1b
TST1a
VST2
Measure
Stress
(with readings)
Measure
Stress
(with readings)
TST2a
TST2b
VSTN
Stress
(with readings)
Measure
Measure
Measure
Stress
(with readings)
Stress
(with readings)
TSTNb
Stress (with readings)
TSTNa
Measure
Time
No missed transient events
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
www.keithley.com
Voltage applied to DUT pin
Benefits of SMU-per-Pin
VST1
Measure
Stress
(with readings)
TST1b
TST1a
VST2
Measure
Stress
(with readings)
Measure
Stress
(with readings)
TST2a
TST2b
VSTN
Stress
(with readings)
Measure
Measure
Measure
Stress
(with readings)
Stress
(with readings)
TSTNb
Stress (with readings)
TSTNa
Measure
Time
No relaxation between stress and test
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
© Copyright 2008 Keithley Instruments, Inc.
www.keithley.com
Advanced Practices using Parallel WLR
• Distributed processing optimizes timing
• High speed for TDDB and BTI
• Advanced structures
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
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Traditional SMU Control Libraries
Central Controller
traditional SMU control libraries
Auxiliary Routines
Determine smu count,
type etc.
Choose Test to perform
WLR Test Routines
(EM_Isothermal,
TDDB, etc.)
Traditional SMU
Data Management &
Display
Decision Making
Based on results
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
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Traditional SMU Control Libraries
Central Controller
traditional SMU control libraries
Auxiliary Routines
Determine smu count,
type etc.
Choose Test to perform
Bus Latency
• SMU takes and returns data
• Waits for next instruction
• Performs next action and
repeats EACH step over GPIB
WLR Test Routines
(EM_Isothermal,
TDDB, etc.)
Traditional SMU
Data Management &
Display
Decision Making
Based on results
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
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Traditional SMU Control Libraries
Central Controller
traditional SMU control libraries
Auxiliary Routines
Determine smu count,
type etc.
Bus Latency
Issues
SMU control libraries
Choose Test to perform
No bus communication!
SMU makes the decision
Auxiliary Routines
Determine smu count,
type etc.
WLR Test Routines
(EM_Isothermal,
TDDB, etc.)
Central Controller
Traditional SMU
Data Management &
Display
Choose Test to perform
(Decide which function
to call)
Data Management &
Display
Smart SMU
WLR Test Routines
(EM_Isothermal,
TDDB, etc.)
Decision Making
(on the fly)
Decision Making
Based on results
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
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Old-Style Centralized Processing
•
Old-style computing – everything
centralized except I/O
Main Frame
Processing power
Terminals
Terminals
Terminals
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
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Modern-Style Distributed Computing
•
Old-style computing – everything
centralized except I/O
•
Modern-style – distributed
processing and I/O,
centralized data
Mainframe
Processing power
terminals
terminals
Processing power
terminals
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
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Traditional System with Central Controller
Traditional:
Testing with “traditional SMUs”
• Check SMU availability
• Choose test to perform
• Control test routines
(EM_Isothermal, TDDB, etc.)
• Data management & display
• Decision-making based on results
“Traditional SMUs”
A
G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
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“Smart SMUs” Allow “Distributed Test Architecture”
with Localized Decision-Making Inside SMU
Traditional:
Testing with “traditional SMUs”
• Check SMU availability
• Choose test to perform
• Control test routines (EM_Isothermal,
TDDB etc.)
• Data management and display
• Decision-making based on results
Distributed testing with “smart SMUs”
• Check SMU availability
• Choose test to perform and
make appropriate function call
• Data management and
display
• Control all test routines
(EM_Isothermal, TDDB, etc.)
• “On-the-fly” decision-making
• Communicate test status and
data
“Smart SMUs”
“Traditional SMUs”
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G R E A T E R
M E A S U R E
OF
C O N F I D E N C E
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NBTI Test with Fastest SMU on the Market
•
By using Series 26xx SMUs with
the TSP™ engine, one can
achieve:
1. Single-point fast switching NBTI
test complete in less than
300µs(Gate), minimize recovery
effect
2. Minimum 100µs sampling time
3. No GPIB command
communication during test period
Gate
Drain
>300µS
Single-point NBTI
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Same Speed on Every SMU – Due to Embedded Processing
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Same Speed on Every SMU – Due to Embedded Processing
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Same Speed on Every SMU – Due to Embedded Processing
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© Copyright 2008 Keithley Instruments, Inc.
www.keithley.com
Same Speed on Every SMU – Due to Embedded Processing
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© Copyright 2008 Keithley Instruments, Inc.
www.keithley.com
Custom Algorithms
• Often, the TD and
materials labs have
special testing needs
• A good parallel WLR
solution provides an
interface that allows
quick prototyping of
custom test methods
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Advanced Parallel WLR Test Structures
• Shared pins provide special challenges for parallel WLR
• SMU-per-pin systems can address a very wide range of
structures that gang-stress systems cannot
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Keithley ACS-WLR Integrated Test System
• Easy parallel WLR setup
• Cassette- and wafer-level
automation
• Database
• Data analysis
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Parallel WLR Summary
• Using existing test structures and probe cards with SMUper-pin test systems offer significantly superior value
• Throughput improvements range from 2 to 30 depending
on structure and system configuration
• Fidelity of the test can be increased with superior timing
and dedicated measurement
• Maximum benefit of parallel WLR requires SMU-per-pin
using advanced SMUs with embedded script processing
capabilities
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Contact Keithley with Your Questions
Speaker: Paul Meyer, Senior Staff Technologist,
Semiconductor Measurements Group, Keithley Instruments
Email: [email protected]
Worldwide Headquarters
Within the USA: 1-888-KEITHLEY
Outside the USA: +1-440-248-0400
Europe:
Germany: (+49) 89 849 307 40
Great Britain: (+44) 118 929 7500
Email: [email protected]
Far East:
China: (+86) 10-822 55 011
Japan: (+81) 3-5733-7555
Korea: (+82) 2-574-7778
Taiwan: (+886) 3-572-9077
Additional offices: www.keithley.com
Keithley also offers a variety of seminars and training classes.
For additional seminars and events, visit www.keithley.com/events
For our current training class schedule, visit www.keithley.com/events/training
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