Download Lecture 12: Combinational Circuit Design

Digital VLSI design
Lecture 12:
Combinational Circuit Design
Quiz # 4 (Discussion)
 Size the transistor in the
circuit so that it has same
drive strength, in the worst
case, as an inverter that has
PW=5 and NW=3.
 Use the smallest widths
possible to achieve this ratio.
 If there are multiple paths
through a transistor, use the
size for the ‘worst-case’ input
combination.
2
Method of Logical Effort
1)
2)
3)
4)
5)
Compute path effort
Estimate best number of stages
Sketch path with N stages
Estimate least delay
Determine best stage effort
F  GBH
N  log4 F
1
N
D  NF  P
ˆf  F N1
gi Couti
Cini 
fˆ
6) Find gate sizes
3
Example
 An 8-input AND gate is to be designed to drive a
load capacitance of 200 units and the input
capacitance is 20 units. Identify the suitable
solution with fastest speed.
 Follow board work!
4
Input Order
 The logical effort and parasitic
delay of different gate inputs
is often different
5
Input Order
 Our parasitic delay model was too simple
 Calculate parasitic delay for Y falling
 If A arrives latest? 2t
 If B arrives latest? 2.33t
2
2
A
2
B
2x
Y
6C
2C
6
Inner & Outer Inputs
 Inner input is closest to output (A)
 Outer input is closest to rail (B)
 If input arrival time is known
 Connect latest input to inner terminal
7
2
2
A
2
B
2
Y
Asymmetric Gates
 Asymmetric gates favor one input over another
 Ex: suppose input A of a NAND gate is most critical
 Use smaller transistor on A (less capacitance)
 Boost size of noncritical input
A
 So total resistance is same
reset
Y
 gA = 10/9
2
2
Y
 gB = 2
A
4/3
 gtotal = gA + gB = 28/9
4
reset
 Asymmetric gate approaches g = 1 on critical input
 But total logical effort goes up
8
Symmetric Gates
 Inputs can be made perfectly symmetric
2
2
A
1
1
B
1
1
9
Y
Skewed Gates
 Skewed gates favor one edge over another
 Ex: suppose rising output of inverter is most
critical
 Downsize noncritical nMOS transistor
HI-skew
inverter
unskewed inverter
(equal rise resistance)
2
A
unskewed inverter
(equal fall resistance)
2
Y
A
1/2
1
Y
A
1
Y
1/2
 Calculate logical effort by comparing to unskewed
inverter with same effective resistance on that
edge.
 gu = 2.5 / 3 = 5/6
 gd = 2.5 / 1.5 = 5/3
10
HI- and LO-Skew
 Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of
that gate to the input capacitance of an unskewed
inverter delivering the same output current for the
same transition.
 Skewed gates reduce size of noncritical transistors
 HI-skew gates favor rising output (small nMOS)
 LO-skew gates favor falling output (small pMOS)
 Logical effort is smaller for favored direction
 But larger for the other direction
11
Catalog of Skewed Gates
Inverter
NAND2
2
unskewed
1
Y
guu = 1
gdd = 1
gavg
=1
avg
A
2
B
2
2
HI-skew
2
A
Y
1/2 gu
u
gdd
gavg
avg
= 5/6
= 5/3
= 5/4
B
1
A
1
1
Y
guu = 4/3
gdd = 2/3
gavg
=1
avg
1
A
2
B
2
12
4
A
4
1
guu = 4/3
gdd = 4/3
gavg
= 4/3
avg
Y
1
B
Y
2
A
1
LO-skew
2
Y
2
A
NOR2
1
B
4
A
4
guu = 5/3
gdd = 5/3
gavg
= 5/3
avg
Y
guu
gdd
gavg
avg
1/2
=1
=2
= 3/2
guu
gdd
gavg
avg
= 3/2
=3
= 9/4
2
B
A
Y
1/2
2
Y
guu = 2
gdd = 1
gavg
= 3/2
avg
1
1
guu = 2
gdd = 1
gavg
= 3/2
avg