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Triangle de signalisation 1 ANALYSE DU SYSTEME MIXTE ...................................................................................................................................2 1.1 1.2 EXPRESSION DU BESOIN ..................................................................................................................................................2 DIAGRAMME SAGITTAL ...................................................................................................................................................2 2 PRESENTATION DE L'OBJET TECHNIQUE 1............................................................................................................2 3 ANALYSE FONCTIONNELLE DU TRIANGLE DE SIGNALISATION LUMINEUX .............................................3 3.1 ETUDE FONCTIONNELLE ..................................................................................................................................................3 3.1.1 Fonction d'usage ....................................................................................................................................................3 3.1.2 Schéma fonctionnel de niveau 2 .............................................................................................................................3 3.1.3 Etude des milieux associés à l'objet technique1 .....................................................................................................3 a) b) c) d) Milieu humain:...............................................................................................................................................................................3 Milieu physique: ............................................................................................................................................................................3 Milieu économique: .......................................................................................................................................................................3 Milieu technique: ...........................................................................................................................................................................3 3.2 ETUDE FONCTIONNELLE DE 1ER DEGRE...........................................................................................................................4 3.2.1 SCHEMA FONCTIONNEL DE 1er DEGRE .........................................................................................................4 3.3 ETUDE FONCTIONNELLE DE 2ND DEGRE ..........................................................................................................................5 3.3.1 Schéma fonctionnel de degré 2...............................................................................................................................5 3.3.2 Définition des entrées/sorties .................................................................................................................................6 4 ETUDE STRUCTURELLE ................................................................................................................................................7 4.1 4.2 4.3 5 SCHEMA STRUCTUREL.....................................................................................................................................................7 NOMENCLATURE .............................................................................................................................................................8 DOCUMENTS DE FABRICATION ........................................................................................................................................9 DOCUMENTATION TECHNIQUE................................................................................................................................10 RT 28/01/06 triangle.doc -1- 1 Analyse du système mixte 1.1 Expression du besoin Lors de travaux sur la chaussée, les usagers de la route doivent être avertis du chantier qu'ils vont rencontrer, afin qu'ils limitent leur vitesse et qu'ils ne soient pas surpris par l'encombrement de la route. Une signalisation lumineuse avertira l'automobiliste de plus loin et attirera plus fortement son attention. 1.2 Diagramme sagittal information M/A et choix du motif usagers de la route triangle de signalisation lumineux information lumineuse signalant un chantier visualisation ouvrier de chantier O.T.1 info. J/N info. 12V/24V environnement batterie de véhicule O.T.2 2 Présentation de l'objet technique 1 RT 28/01/06 triangle.doc -2- 3 Analyse fonctionnelle du triangle de signalisation lumineux 3.1 Etude fonctionnelle 3.1.1 Fonction d'usage Le triangle de signalisation lumineux réalise les fonctions suivantes: • Élaborer une commande d'allumage des lampes en fonction du motif choisit, de la luminosité de l'environnement et du type de batterie. • Signaler de façon lumineuse un éventuel chantier aux usagers de la route. 3.1.2 Schéma fonctionnel de niveau 2 info.M/A élaboration d'une cmde choix du motif d'allumage des lampes ouvrier 3.1.3 usagers de la route O.T.1 Simplicité d'utilisation. Détermination du motif effectué en usine, en accord avec le client. Diminution de l'intensité lumineuse la nuit pour éviter les éblouissements. Milieu physique: • • L'électronique étant logée dans la carcasse du triangle, il en résulte des contraintes dues à l'environnement thermique (température ambiante avoisinant 60°C en été). Électronique enrobée de résine et protégée contre les courts-circuits. Résistant aux chocs. Milieu économique: • • • Reconnaissance et adaptation automatique au type de batterie 12V ou 24V. Motif lumineux facilement modifiable à la commande. Faible coût de revient. Milieu technique: • • RT 28/01/06 lumineuse Milieu humain: • d) info. Etude des milieux associés à l'objet technique1 • • • c) lumineuse information 12V/24V batterie b) des lampes signalisation info. J/N environnement a) cmde d'allumage ouvrier de chantier Source d'énergie = batterie 12V ou 24V. Lampe à iode 12V/55W uniquement. triangle.doc -3- 3.2 Etude fonctionnelle de 1er degré 3.2.1 SCHEMA FONCTIONNEL DE 1er DEGRE info. 12V/24V identification du information 12V / 24V type de batterie F.P.3 captage info. J/N information J/N jour / nuit F.P.4 3 choix d'un motif parmi 8 élaboration de la commande d'allumage des lampes F.P.1 commande d'allumage signalisation lumineuse des lampes information lumineuse F.P.2 O.T.1 RT 28/01/06 triangle.doc -4- 3.3 Etude fonctionnelle de 2nd degré 3.3.1 Schéma fonctionnel de degré 2 Choix d'un motif parmi 8 info J/N A12-A13-A14 captage J/N 3 mémorisation A10 J/N S0 de commande énergie électrique 12V/24V S0' des informations F.S.4.1 identification de la tension BAT A11 12V ou 24V protection contre les inversions VA de polarité et détection du niveau de charge de la batterie F.S.3.1 production d'un signal rectangulaire h amplification de puissance S1 S1' des lampes F.S.2.1 F.S.3.2 Production d’adresses F.S.1.1 A0-A9 10 F.S.1.2 F.S.1.3 R.A.Z VA Vo F.a RT 28/01/06 triangle.doc -5- conversion énergie électrique/ énergie lumineuse F.S.2.2 information lumineuse 3.3.2 Définition des entrées/sorties info.J/N : Information : intensité lumineuse ambiante. J/N (A10) : Information logique relative à l'éclairement ambiant. E.E (12V/24V) : tension de batterie alimentant le triangle pouvant atteindre 14,5V pour une batterie de 12V et 28V pour une batterie de 24V. VA: tension d'alimentation provenant de la batterie. BAT (A11): information logique pour la détection d'une batterie de 12V ou 24V. Vo : tension régulée à 5V permettant d'alimenter les circuits logiques. A12, A13, A14: Information numérique: mot binaire de 3 bits qui permet la sélection d'un motif parmi 8. A14 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1 A12 0 1 0 1 0 1 0 1 motifs Modèle A Modèle B ou C Non utilisé Non utilisé Non utilisé Non utilisé Non utilisé Non utilisable Identification mémoire h : ddp rectangulaire d'amplitude (0;5V). A0 à A9 : Information numérique: mot binaire de 10 bits. Chaque mot correspond à une case mémoire qui renferme un nombre binaire de 8 bits. Le balayage des combinaisons $000 à $3FF détermine la période d'allumage et de découpage des lampes. S0 : Information logique qui commande l'allumage des lampes L1, L2, L3. S0 est une valeur mémorisée et correspond au bit de poids faible de l'octet. Lors du balayage des combinaisons des adresses A0 à A9, le niveau logique en S0 détermine l'allumage et l'intensité lumineuse des lampes L1, L2, L3. RAZ : Information logique permet la remise à zéro du nombre (A9…A0)2 . RT 28/01/06 triangle.doc -6- 4 Etude structurelle 4.1 Schéma structurel 11 RST 10 RT 28/01/06 triangle.doc f Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1 -7- 4.2 Nomenclature RT 28/01/06 RefDes Type Value -------------------- -------------------- --------------- RefDes Type Value -------------------- -------------------- --------------- C1 C2 C3 C4 C5 C6 C7 C8 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 L1 L2 L3 P1 P2 R1 R2 R3 R4 R5 R6 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 S1 S2 S3 T1 T2 T3 T4 U1 U2 U3 U4 U5 U6 C2 C2 C1 C2_POL C2_POL C2_POL C2 C2 1N4148 1N4148 ZENER12V 1N4148 ZENER9.1V ZENER9.1V 1N4001 ZENER4.7V ZENER9.1V ZENER4.7V BORNE1 BORNE1 DOUILLE4 DOUILLE4 PTEST PTEST PTEST PTEST PTEST PTEST PTEST BORNE1 BORNE1 LAMPE LAMPE LAMPE POT3T POT3T R1 R1 R1 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R1 R2 INVERSEUR INVERSEUR INVERSEUR 10n 22u 22n 100u 1u 1u 100n 100n 12v BC548A SFH309 BC548A BC558B CD4093BCN HCC4040BF IRF540 ZVP2106A HN58C256 78L05 9.1V 9.1V 4.7V 9.1V 4.7V 2.2Meg 470k 100K 0 100k 4.7k 1K 100k 100k 100k 100k 3.3k 1Meg 100K 22K 4.7K 4.7k 10k 3.3k triangle.doc -8- 4.3 Documents de fabrication RT 25/01/06 triangle.doc -9- Triangles rabattables pour véhicules Triangles pour véhicules symbole AK5 r : 500 LEDs Ø 60 Code Référence T1 T2 T1 T2 T1 T2 TML124/500T1 TML124/500T2 808562035 TML500ELECT1 808562036 TML500ELECT2 808564035 TUML124/500T1 808564036 TUML124/500T2 Moins value XENON Ø 60 Relevage(1) Double T1 face manuel T2 Relevage Double T1 face électrique T2 Fixation T1 simple face rail arrière T2 Référence TNX124/500T1 808500045 TNX124/500T2 808503 TNX500ELECT1 808503045 TNX500ELECT2 808506 TUX124/500T1 808506035 TUX124/500T2 Moins value Relevage(1) Double face manuel Relevage Double face électrique Fixation simple face rail arrière Simple face TML500/700 Simple face TNX500/700 IODE Ø 60 Relevage(1) Double face manuel Relevage Double face électrique Fixation rail arrière simple face 808560035 808560036 Code 808500 Code T1 T2 T1 T2 T1 T2 808542 808542045 808548 808548045 808509 808509045 Simple face TMO500/700 Référence TMO124/500T1 TMO124/500T2 TMO500ELECT1 TMO500ELECT2 TUMO124/500T1 TUMO124/500T2 Moins value r : 700 Prix 389 431 678 719 281 302 -89 €� €� €� €� €� €� €� Prix 427 469 791 832 317 338 -74 €� €� €� €� €� €� €� Code €� €� €� €� €� €� €� Prix 474 562 793 882 366 410 -89 TML124/700T1 TML124/700T2 808563035 TML700ELECT1 808563036 TML700ELECT2 808565035 TUML124/700T1 808565036 TUML124/700T2 Moins value 808561035 808561036 €� €� €� €� €� €� €� Jour Nuit 12 V : 0,3 A 12 V : 0,15 A 24 V : 0,15 A 24 V : 0,07 A 12 V : 0,15 A 12 V : 0,07 A 24 V : 0,07 A 24 V : 0,04 A Prix Référence TNX124/700T1 531 €� 808501045 TNX124/700T2 620 €� 808504 TNX700ELECT1 926 €� 808504045 TNX700ELECT2 1015 €� 808507 TUX124/700T1 412 €� 808507035 TUX124/700T2 456 €� Moins value -74 €� Code 808501 Prix 294 335 657 698 291 312 -6 Consommation Référence Code 808543045 808549 808549045 808510 808510045 384 473 779 867 381 425 -6 Moins value (1) Le kit de rabattement est à commander séparément 12 V : 0,8 A 24 V : 0,7 A 24 V : 0,4 A 12 V : 0,7 A 12 V : 0,4 A 24 V : 0,04 A 24 V : 0,2 A 12 V : 6,8 A 12 V : 3,4A 24 V : 3,4 A 24 V : 1,7A 12 V : 6,8 A 12 V : 3,4 A 24 V : 3,4 A 24 V : 1,7 A Prix Référence TMO124/700T1 TMO124/700T2 TMO700ELECT1 TMO700ELECT2 TUMO124/700T1 TUMO124/700T2 808543 12 V : 1,4 A €� €� €� €� €� €� €� Accessoires Code inter avec voyant 12 V (10 A max) 812199 inter avec voyant 24 V (10 A max) 812197 prise allume-cigares 811400 kit de rabattement 809356 plaque de fixation r 500 809355 plaque de fixation r 700 809357 embase magnétique r 500 809613 embase magnétique r 700 809614 Référence INT/VOY12 INT/VOY24 P/AC K/RAB FIX/TP500 FIX/TP700 MAG/TP500 MAG/TP700 Prix 12 12 8 23 21 28 63 73 €� €� €� €� €� €� €� €� SYMBOLES AK2 AK3 AK4 AK5 AK14 AK17 AK22 AK30 AK31 • Film Diamond Grade fluo • Symbole autre que AK5 • Triangles de dimensions 1000 mm • Relevage électrique seul • Triangles pendulaires pour camions bennes Nous sommes à votre disposition pour étudier toute fabrication particulière ! 275, rue de Clermont - ZA la Vatine - F 60000 BEAUVAIS Tél. : 03 44 10 33 90 - Fax : 03 44 10 33 99 - Email : [email protected] - www.franclair.com Tarifs en Euros hors taxes - départ usine Extrait du Catalogue 2005 MM54HC4020/MM74HC4020 14-Stage Binary Counter MM54HC4040/MM74HC4040 12-Stage Binary Counter General Description The MM54HC4020/MM74HC4020, MM54HC4040/ MM74HC4040, are high speed binary ripple carry counters. These counters are implemented utilizing advanced silicongate CMOS technology to achieve speed performance similar to LS-TTL logic while retaining the low power and high noise immunity of CMOS. The ’HC4020 is a 14 stage counter and the ’HC4040 is a 12stage counter. Both devices are incremented on the falling edge (negative transition) of the input clock, and all their outputs are reset to a low level by applying a logical high on their reset input. These devices are pin equivalent to the CD4020 and CD4040 respectively. All inputs are protected from damage due to static discharge by protection diodes to VCC and ground. Features Y Y Y Y Y Typical propagation delay: 16 ns Wide operating voltage range: 2 – 6V Low input current: 1 mA maximum Low quiescent current: 80 mA maximum (74HC Series) Output drive capability: 10 LS-TTL loads Connection Diagrams Dual-In-Line Packages ’HC4020 TL/F/5216 – 1 ’HC4040 TL/F/5216 – 3 Order Number MM54HC4020/4040 or MM74HC4020/4040 C1995 National Semiconductor Corporation TL/F/5216 RRD-B30M105/Printed in U. S. A. MM54HC4020/MM74HC4020 14-Stage Binary Counter MM54HC4040/MM74HC4040 12-Stage Binary Counter December 1988 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (ICD) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) DC Input or Output Voltage (VIN, VOUT) b 0.5 to a 7.0V b 1.5 to VCC a 1.5V Operating Temp. Range (TA) MM74HC MM54HC b 0.5 to VCC a 0.5V g 20 mA Min 2 Max 6 0 VCC Units V V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns Input Rise or Fall Times VCC e 2.0V (tr, tf) VCC e 4.5V VCC e 6.0V g 25 mA g 50 mA b 65§ C to a 150§ C 600 mW 500 mW 260§ C DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC TA e 25§ C Typ 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 V V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA 4.5V 6.0V 0.2 0.2 .26 .26 0.33 0.33 0.4 0.4 V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA IIN Maximum Input Current VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 6.0V 8.0 80 160 mA Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns Symbol Parameter Conditions Typ Guaranteed Limit Units 50 30 MHz 17 35 ns fMAX Maximum Operating Frequency tPHL, tPLH Maximum Propagation Delay Clock to Q tPHL Maximum Propagation Delay Reset to any Q 16 40 ns tREM Minimum Reset Removal Time 10 20 ns tW Minimum Pulse Width 10 16 ns (Note 5) AC Electrical Characteristics VCC e 2.0V to 6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions TA e 25§ C VCC Typ 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits fMAX Maximum Operating Frequency 2.0V 4.5V 6.0V 10 40 50 6 30 35 5 24 28 4 20 24 MHz MHz MHz tPHL, tPLH Maximum Propagation Delay Clock to Q1 2.0V 4.5V 6.0V 80 21 18 210 42 36 265 53 45 313 63 53 ns ns ns TPHL, tPLH Maximum Propagation Delay Between Stages from Qn to Qn a 1 2.0V 4.5V 6.0V 80 18 15 125 25 21 156 31 26 188 38 31 ns ns ns tPHL Maximum Propagation Delay Reset to any Q (’4020 and ’4040) 2.0V 4.5V 6.0V 72 24 20 240 48 41 302 60 51 358 72 61 ns ns ns tREM Minimum Reset Removal Time 2.0V 4.5V 6.0V 100 20 16 126 25 21 149 50 25 ns ns ns tW Minimum Pulse Width 2.0V 4.5V 6.0V 90 16 14 100 20 18 120 24 20 ns ns ns tTLH, tTHL Maximum Output Rise and Fall Time 2.0V 4.5V 6.0V 75 15 13 95 19 16 110 22 19 ns ns ns tr, tf Maximum Input Rise and Fall Time 1000 500 400 1000 500 400 1000 500 400 ns ns ns CPD Power Dissipation Capacitance (Note 6) CIN Maximum Input Capacitance 30 10 9 (per package) 55 5 pF 10 10 10 pF Note 5: Typical Propagation delay time to any output can be calculated using: tP e 17 a 12(N–1) ns; where N is the number of the output, QW, at VCC e 5V. Note 6: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 3 Logic Diagrams MM54HC4020/MM74HC4020 TL/F/5216 – 5 MM54HC4040/MM74HC4040 TL/F/5216 – 7 4 TL/F/5216 – 11 Timing Diagram 5 Physical Dimensions inches (millimeters) Order Number MM54HC4020J, MM54HC4024J, MM54HC4040J, MM74HC4020J, MM74HC4024J, or MM74HC4040J NS Package J14A 6 Physical Dimensions inches (millimeters) (Continued) Order Number MM54HC4020J, MM54HC4024J, MM54HC4040J, MM74HC4020J, MM74HC4024J, or MM74HC4040J NS Package J16A Order Number MM74HC4020N, MM74HC4024N or MM74HC4040N NS Package N14A 7 MM54HC4020/MM74HC4020 14-Stage Binary Counter MM54HC4040/MM74HC4040 12-Stage Binary Counter Physical Dimensions inches (millimeters) (Continued) Order Number MM74HC4020N, MM74HC4024N or MM74HC4040N NS Package N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Order this document by MCT7800/D These voltage regulators are monolithic integrated circuits designed as fixed-voltage regulators for a wide variety of applications including local, on-card regulation. These regulators employ internal current limiting, thermal shutdown, and safe-area compensation. With adequate heatsinking they can deliver output currents in excess of 1.0 A. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltages and currents. • Output Current in Excess of 1.0 A • • • • • • THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORS No External Components Required Internal Thermal Overload Protection T SUFFIX PLASTIC PACKAGE CASE 221A Internal Short Circuit Current Limiting Output Transistor Safe-Area Compensation Output Voltage Offered with a 4% Tolerance Available in Surface Mount D2PAK and Standard 3-Lead Transistor Heatsink surface connected to Pin 2. 1 Packages 2 3 Pin 1. Input 2. Ground 3. Output D2T SUFFIX PLASTIC PACKAGE CASE 936 (D2PAK) 1 2 3 Heatsink surface (shown as terminal 4 in case outline drawing) is connected to Pin 2. This MCT-prefixed device is intended to be a possible replacement for the similar device with the MC-prefix. Because the MCT device originates from different source material, there may be subtle differences in typical parameter values or characteristic curves. Due to the diversity of potential applications, Motorola can not assure identical performance in all circuits. Motorola recommends that the customer qualify the MCT-prefixed device in each potential application. STANDARD APPLICATION Input Cin* 0.33 µF DEVICE TYPE/NOMINAL OUTPUT VOLTAGE MCT7805 MCT7806 MCT7808 MCT7809 5.0 V 6.0 V 8.0 V 9.0 V MCT7812 MCT7815 MCT7818 MCT7824 12 V 15 V 18 V 24 V MCT78XX Output CO** A common ground is required between the input and the output voltages. The input voltage must remain typically 2.0 V above the output voltage even during the low point on the input ripple voltage. ORDERING INFORMATION Device Output Voltage Tolerance Tested Operating Temperature Range Package Surface Mount MCT78XXBD2T TJ = – 40° to +125°C MCT78XXBT Insertion Mount 4% Surface Mount MCT78XXCD2T MCT78XXCT TJ = 0° to +125°C Insertion Mount XX, these two digits of the type number indicate nominal voltage. ** Cin is required if regulator is located an appreciable distance from power supply filter. ** Some CO is recommended for stability; it does improve transient response. Values less than 0.1 µF could cause instability. XX indicates nominal voltage. Motorola, Inc. 1994 MOTOROLA Rev 3 MCT7800 1 MCT7800 MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.) Rating Symbol Value Unit VI 35 Vdc PD θJA θJC Internally Limited 65 5.0 W °C/W °C/W PD θJA θJC Internally Limited 70 5.0 W °C/W °C/W Tstg – 65 to +150 °C TJ +150 °C Input Voltage Power Dissipation Case 221A TA = +25°C Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Case 936 (D2PAK) TA = +25°C Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Storage Junction Temperature Range Operating Junction Temperature Representative Schematic Diagram Input 100 100 100 10 k 500 240 200 0.3 Output 3.3 k 2.0 k 6.0 k 0.25 k 2.7 k 1.4 k 28 k 30 pF 5.0 k 500 6.0 k 1.0 k 5.0 k Gnd This device contains 19 active transistors. MCT7800 2 MOTOROLA MCT7800 ELECTRICAL CHARACTERISTICS (Vin = 10 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.) MCT7805B Characteristics MCT7805C Symbol Min Typ Max Min Typ Max Unit Output Voltage (TJ = +25°C) VO 4.8 5.0 5.2 4.8 5.0 5.2 Vdc Output Voltage (5.0 mA ≤ IO ≤ 1.0 A, PO ≤15 W) 7.0 Vdc ≤ Vin ≤ 20 Vdc 8.0 Vdc ≤ Vin ≤ 20 Vdc VO — 4.75 — 5.0 — 5.25 4.75 — 5.0 — 5.25 — — — 7.0 2.0 100 50 — — 7.0 2.0 100 50 — — 2.0 1.5 100 50 — — 2.0 1.5 100 50 — 5.5 8.0 — 5.5 8.0 — — — — — — — 1.3 0.5 — — — — — — 1.3 — 0.5 — 65 — — 65 — — 2.0 — — 2.0 — — 10 — — 10 — — 1.3 — — 1.3 — — 0.2 — — 0.2 — Imax — 2.2 — — 2.2 — A TCVO — 0.5 — — 0.5 — mV/°C Line Regulation, TJ = +25°C (Note 2) 7.0 Vdc ≤ Vin ≤ 25 Vdc 8.0 Vdc ≤ Vin ≤ 12 Vdc Regline Load Regulation, TJ = +25°C (Note 2) 5.0 mA ≤ Vin ≤ 1.5 A 250 mA ≤ Vin ≤ 750 mA Regload Quiescent Current (TJ = +25°C) IB Quiescent Current Change 7.0 Vdc ≤ Vin ≤ 25 Vdc 8.0 Vdc ≤ Vin ≤ 25 Vdc 5.0 mA ≤ IO ≤ 1.0 A ∆IB Ripple Rejection 8.0 Vdc ≤ Vin ≤ 18 Vdc, f = 120 Hz RR Dropout Voltage (IO = 1.0 A, TJ = +25°C) VI – VO Output Noise Voltage (TA = +25°C) 10 Hz ≤ f ≤ 100 kHz Vn Output Resistance f = 1.0 kHz rO Short Circuit Current Limit (TA = +25°C) Vin = 35 Vdc ISC Peak Output Current (TJ = +25°C) Average Temperature Coefficient of Output Voltage Vdc mV mV mA mA dB Vdc µV/VO mΩ A ELECTRICAL CHARACTERISTICS (Vin = 11 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.) MCT7806B Characteristics MCT7806C Symbol Min Typ Max Min Typ Max Unit Output Voltage (TJ = +25°C) VO 5.75 6.0 6.25 5.75 6.0 6.25 Vdc Output Voltage (5.0 mA ≤ IO ≤ 1.0 A, PO ≤15 W) 8.0 Vdc ≤ Vin ≤ 21 Vdc 9.0 Vdc ≤ Vin ≤ 21 Vdc VO — 5.7 — 6.0 — 6.3 5.7 — 6.0 — 6.3 — — — 7.0 2.0 120 60 — — 7.0 2.0 120 60 — — 2.0 1.5 120 60 — — 2.0 1.5 120 60 — 5.5 8.0 — 5.5 8.0 — — — — — — — 1.3 0.5 — — — — — — 1.3 — 0.5 — 65 — — 65 — Line Regulation, TJ = +25°C (Note 2) 8.0 Vdc ≤ Vin ≤ 25 Vdc 9.0 Vdc ≤ Vin ≤ 13 Vdc Regline Load Regulation, TJ = +25°C (Note 2) 5.0 mA ≤ Vin ≤ 1.5 A 250 mA ≤ Vin ≤ 750 mA Regload Quiescent Current (TJ = +25°C) IB Quiescent Current Change 8.0 Vdc ≤ Vin ≤ 25 Vdc 9.0 Vdc ≤ Vin ≤ 25 Vdc 5.0 mA ≤ IO ≤ 1.0 A ∆IB Ripple Rejection 9.0 Vdc ≤ Vin ≤ 19 Vdc, f = 120 Hz RR NOTES: Vdc mV mV mA mA dB 1. Tlow = 0°C for MCT78XXC = – 40°C for MCT78XXB Thigh = +125°C for MCT78XXB, C. When the junction temperature exceeds +125°C, internal current limiting will reduce the output current to less than 1.0 A at a VI–VO of 15 V or greater. The MC7800 die will supply more current under the same conditions. 2. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. MOTOROLA MCT7800 3 MCT7800 ELECTRICAL CHARACTERISTICS (continued) (Vin = 11 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.) MCT7806B Characteristics Dropout Voltage (IO = 1.0 A, TJ = +25°C) Output Noise Voltage (TA = +25°C) 10 Hz ≤ f ≤ 100 kHz MCT7806C Symbol Min Typ Max Min Typ Max Unit VI – VO — 2.0 — — 2.0 — Vdc — 10 — — 10 — — 1.3 — — 1.3 — — 0.2 — — 0.2 — µV/VO Vn Output Resistance f = 1.0 kHz rO Short Circuit Current Limit (TA = +25°C) Vin = 35 Vdc ISC Peak Output Current (TJ = +25°C) Imax — 2.2 — — 2.2 — A TCVO — – 0.8 — — – 0.8 — mV/°C Average Temperature Coefficient of Output Voltage mΩ A ELECTRICAL CHARACTERISTICS (Vin = 14 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.) MCT7808B Characteristics MCT7808C Symbol Min Typ Max Min Typ Max Unit Output Voltage (TJ = +25°C) VO 7.7 8.0 8.3 7.7 8.0 8.3 Vdc Output Voltage (5.0 mA ≤ IO ≤ 1.0 A, PO ≤15 W) 10.5 Vdc ≤ Vin ≤ 23 Vdc 11.5 Vdc ≤ Vin ≤ 23 Vdc VO — 7.6 — 8.0 — 8.4 7.6 — 8.0 — 8.4 — — — 7.0 2.0 160 80 — — 7.0 2.0 160 80 — — 2.0 1.5 160 80 — — 2.0 1.5 160 80 — 5.5 8.0 — 5.5 8.0 — — — — — — — 1.0 0.5 — — — — — — 1.0 — 0.5 — 63 — — 63 — — 2.0 — — 2.0 — — 10 — — 10 — — 18 — — 18 — — 0.2 — — 0.2 — Line Regulation, TJ = +25°C (Note 2) 10.5 Vdc ≤ Vin ≤ 25 Vdc 11 Vdc ≤ Vin ≤ 17 Vdc Regline Load Regulation, TJ = +25°C (Note 2) 5.0 mA ≤ IO ≤ 1.5 A 250 mA ≤ IO ≤ 750 mA Regload Quiescent Current (TJ = +25°C) IB Quiescent Current Change 10.5 Vdc ≤ Vin ≤ 25 Vdc 11.5 Vdc ≤ Vin ≤ 25 Vdc 5.0 mA ≤ IO ≤ 1.0 A ∆IB Ripple Rejection 11.5 Vdc ≤ Vin ≤ 21.5 Vdc, f = 120 Hz RR Dropout Voltage (IO = 1.0 A, TJ = +25°C) VI – VO Vdc mV mV mA mA dB Vdc µV/VO Output Noise Voltage (TA = +25°C) 10 Hz ≤ f ≤ 100 kHz Vn Output Resistance f = 1.0 kHz rO Short Circuit Current Limit (TA = +25°C) Vin = 35 Vdc ISC Peak Output Current (TJ = +25°C) Imax — 2.2 — — 2.2 — A TCVO — – 0.8 — — – 0.8 — mV/°C Average Temperature Coefficient of Output Voltage NOTES: mΩ A 1. Tlow = 0°C for MCT78XXC = – 40°C for MCT78XXB Thigh = +125°C for MCT78XXB, C. When the junction temperature exceeds +125°C, internal current limiting will reduce the output current to less than 1.0 A at a VI–VO of 15 V or greater. The MC7800 die will supply more current under the same conditions. 2. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. MCT7800 4 MOTOROLA MCT7800 ELECTRICAL CHARACTERISTICS (Vin = 15 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.) MCT7809B Characteristics Output Voltage (TJ = +25°C) Output Voltage (5.0 mA ≤ IO ≤ 1.0 A, PO ≤15 W) 11.5 Vdc ≤ Vin ≤ 24 Vdc 12.5 Vdc ≤ Vin ≤ 24 Vdc Line Regulation, TJ = +25°C (Note 2) 11.5 Vdc ≤ Vin ≤ 26 Vdc 11.5 Vdc ≤ Vin ≤ 17 Vdc Load Regulation, TJ = +25°C (Note 2) 5.0 mA ≤ IO ≤ 1.5 A 250 mA ≤ IO ≤ 750 mA Quiescent Current (TJ = +25°C) Quiescent Current Change 11.5 Vdc ≤ Vin ≤ 26 Vdc 12.5 Vdc ≤ Vin ≤ 26 Vdc 5.0 mA ≤ IO ≤ 1.0 A Symbol Min Typ Max Min Typ Max Unit VO VO 8.65 9.0 9.35 8.65 9.0 9.35 Vdc — 8.55 — 9.0 — 9.45 8.55 — 9.0 — 9.45 — — — 8.0 4.0 50 25 — — 8.0 4.0 50 25 — — 3.0 2.0 50 25 — — 3.0 2.0 50 25 — 5.5 8.0 — 5.5 8.0 — — — — — — — 1.0 0.5 — — — — — — 1.0 — 0.5 — 62 — — 62 — — 2.0 — — 2.0 — mV Regload IB ∆IB RR Dropout Voltage (IO = 1.0 A, TJ = +25°C) VI – VO Vn Output Resistance f = 1.0 kHz rO Short Circuit Current Limit (TA = +25°C) Vin = 35 Vdc Peak Output Current (TJ = +25°C) ISC Average Temperature Coefficient of Output Voltage Vdc Regline Ripple Rejection 11.5 Vdc ≤ Vin ≤ 21.5 Vdc, f = 120 Hz Output Noise Voltage (TA = +25°C) 10 Hz ≤ f ≤ 100 kHz MCT7809C Imax TCVO mV mA mA dB Vdc µV/VO — 10 — — 10 — — 18 — — 18 — — 0.2 — — 0.2 — — 2.2 — — 2.2 — A — –1.0 — — –1.0 — mV/°C mΩ A ELECTRICAL CHARACTERISTICS (Vin = 19 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.) MCT7812B Characteristics Output Voltage (TJ = +25°C) Output Voltage (5.0 mA ≤ IO ≤ 1.0 A, PO ≤15 W) 14.5 Vdc ≤ Vin ≤ 27 Vdc 15.5 Vdc ≤ Vin ≤ 27 Vdc Line Regulation, TJ = +25°C (Note 2) 14.5 Vdc ≤ Vin ≤ 30 Vdc 16 Vdc ≤ Vin ≤ 22 Vdc Load Regulation, TJ = +25°C (Note 2) 5.0 mA ≤ IO ≤ 1.5 A 250 mA ≤ IO ≤ 750 mA Quiescent Current (TJ = +25°C) Quiescent Current Change 14.5 Vdc ≤ Vin ≤ 30 Vdc 15 Vdc ≤ Vin ≤ 30 Vdc 5.0 mA ≤ IO ≤ 1.0 A NOTES: MCT7812C Symbol Min Typ Max Min Typ Max Unit VO VO 11.5 12 12.5 11.5 12 12.5 Vdc — 11.4 — 12 — 12.6 11.4 — 12 — 12.6 — — — 10 5.0 240 120 — — 10 5.0 240 120 — — 3.0 2.0 240 120 — — 3.0 2.0 240 120 — 5.5 8.0 — 5.5 8.0 — — — — — — — 1.0 0.5 — — — — — — 1.0 — 0.5 Vdc Regline mV Regload IB ∆IB mV mA mA 1. Tlow = 0°C for MCT78XXC = – 40°C for MCT78XXB Thigh = +125°C for MCT78XXB, C. When the junction temperature exceeds +125°C, internal current limiting will reduce the output current to less than 1.0 A at a VI–VO of 15 V or greater. The MC7800 die will supply more current under the same conditions. 2. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. MOTOROLA MCT7800 5 MCT7800 ELECTRICAL CHARACTERISTICS (continued) (Vin = 19 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.) MCT7812B Characteristics Ripple Rejection 15 Vdc ≤ Vin ≤ 25 Vdc, f = 120 Hz Dropout Voltage (IO = 1.0 A, TJ = +25°C) Output Noise Voltage (TA = +25°C) 10 Hz ≤ f ≤ 100 kHz Output Resistance f = 1.0 kHz Short Circuit Current Limit (TA = +25°C) Vin = 35 Vdc Peak Output Current (TJ = +25°C) Average Temperature Coefficient of Output Voltage Symbol MCT7812C Min Typ Max Min Typ Max — 62 — — 62 — — 2.0 — — 2.0 — — 10 — — 10 — — 18 — — 18 — — 0.2 — — 0.2 — — 2.2 — — 2.2 — A — –1.0 — — –1.0 — mV/°C RR VI – VO Vn rO ISC Imax TCVO Unit dB Vdc µV/VO mΩ A ELECTRICAL CHARACTERISTICS (Vin = 23 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.) MCT7815B Characteristics MCT7815C Symbol Min Typ Max Min Typ Max Unit Output Voltage (TJ = +25°C) VO 14.4 15 15.6 14.4 15 15.6 Vdc Output Voltage (5.0 mA ≤ IO ≤ 1.0 A, PO ≤15 W) 17.5 Vdc ≤ Vin ≤ 30 Vdc 18.5 Vdc ≤ Vin ≤ 30 Vdc VO — 14.25 — 15 — 15.75 14.25 — 15 — 15.75 — — — 11 5.0 300 150 — — 11 5.0 300 150 — — 3.0 2.0 300 150 — — 3.0 2.0 300 150 — 5.5 8.0 — 5.5 8.0 — — — — — — — 1.0 0.5 — — — — — — 1.0 — 0.5 — 60 — — 60 — — 2.0 — — 2.0 — — 10 — — 10 — — 19 — — 19 — — 0.2 — — 0.2 — Line Regulation, TJ = +25°C (Note 2) 17.5 Vdc ≤ Vin ≤ 30 Vdc 20 Vdc ≤ Vin ≤ 26 Vdc Regline Load Regulation, TJ = +25°C (Note 2) 5.0 mA ≤ Vin ≤ 1.5 A 250 mA ≤ Vin ≤ 750 mA Regload Quiescent Current (TJ = +25°C) IB Quiescent Current Change 17.5 Vdc ≤ Vin ≤ 30 Vdc 18.5 Vdc ≤ Vin ≤ 30 Vdc 5.0 mA ≤ IO ≤ 1.0 A ∆IB Ripple Rejection 18.5 Vdc ≤ Vin ≤ 28.5 Vdc, f = 120 Hz RR Dropout Voltage (IO = 1.0 A, TJ = +25°C) VI – VO Output Noise Voltage (TA = +25°C) 10 Hz ≤ f ≤ 100 kHz Vdc mV mV mA mA dB Vdc µV/VO Vn Output Resistance f = 1.0 kHz rO Short Circuit Current Limit (TA = +25°C) Vin = 35 Vdc ISC Peak Output Current (TJ = +25°C) Imax — 2.2 — — 2.2 — A TCVO — –1.0 — — –1.0 — mV/°C Average Temperature Coefficient of Output Voltage NOTES: mΩ A 1. Tlow = 0°C for MCT78XXC = – 40°C for MCT78XXB Thigh = +125°C for MCT78XXB, C. When the junction temperature exceeds +125°C, internal current limiting will reduce the output current to less than 1.0 A at a VI–VO of 15 V or greater. The MC7800 die will supply more current under the same conditions. 2. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. MCT7800 6 MOTOROLA MCT7800 ELECTRICAL CHARACTERISTICS (Vin = 27 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.) MCT7818B Characteristics Output Voltage (TJ = +25°C) Output Voltage (5.0 mA ≤ IO ≤ 1.0 A, PO ≤15 W) 21 Vdc ≤ Vin ≤ 33 Vdc 22 Vdc ≤ Vin ≤ 33 Vdc Line Regulation, TJ = +25°C (Note 2) 21 Vdc ≤ Vin ≤ 33 Vdc 24 Vdc ≤ Vin ≤ 30 Vdc Load Regulation, TJ = +25°C (Note 2) 5.0 mA ≤ Vin ≤ 1.5 A 250 mA ≤ Vin ≤ 750 mA Quiescent Current (TJ = +25°C) Quiescent Current Change 21 Vdc ≤ Vin ≤ 33 Vdc 22 Vdc ≤ Vin ≤ 33 Vdc 5.0 mA ≤ IO ≤ 1.0 A Ripple Rejection 22 Vdc ≤ Vin ≤ 32 Vdc, f = 120 Hz Dropout Voltage (IO = 1.0 A, TJ = +25°C) Output Noise Voltage (TA = +25°C) 10 Hz ≤ f ≤ 100 kHz Output Resistance f = 1.0 kHz Short Circuit Current Limit (TA = +25°C) Vin = 35 Vdc Peak Output Current (TJ = +25°C) Average Temperature Coefficient of Output Voltage MCT7818C Symbol Min Typ Max Min Typ Max Unit VO VO 17.3 18 18.7 17.3 18 18.7 Vdc — 17.1 — 18 — 18.9 17.1 — 18 — 18.9 — — — 11 5.0 360 180 — — 11 5.0 360 180 — — 4.0 3.0 360 180 — — 4.0 3.0 360 180 — 5.5 8.0 — 5.5 8.0 — — — — — — — 1.0 0.5 — — — — — — 1.0 — 0.5 — 59 — — 59 — — 2.0 — — 2.0 — Vdc Regline mV Regload IB ∆IB mV mA RR ViI – VO Vn rO ISC Imax TCVO mA dB Vdc µV/VO — 10 — — 10 — — 19 — — 19 — — 0.2 — — 0.2 — — 2.2 — — 2.2 — A — –1.0 — — –1.0 — mV/°C mΩ A ELECTRICAL CHARACTERISTICS (Vin = 33 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.) MCT7824B Characteristics Output Voltage (TJ = +25°C) Output Voltage (5.0 mA ≤ IO ≤ 1.0 A, PO ≤15 W) 27 Vdc ≤ Vin ≤ 38 Vdc 28 Vdc ≤ Vin ≤ 38 Vdc Line Regulation, TJ = +25°C (Note 2) 27 Vdc ≤ Vin ≤ 38 Vdc 30 Vdc ≤ Vin ≤ 36 Vdc Load Regulation, TJ = +25°C (Note 2) 5.0 mA ≤ IO ≤ 1.5 A 250 mA ≤ IO ≤ 750 mA Quiescent Current (TJ = +25°C) Quiescent Current Change 27 Vdc ≤ Vin ≤ 38 Vdc 28 Vdc ≤ Vin ≤ 38 Vdc 5.0 mA ≤ IO ≤ 1.0 A Ripple Rejection 28 Vdc ≤ Vin ≤ 38 Vdc, f = 120 Hz Dropout Voltage (IO = 1.0 A, TJ = +25°C) Output Noise Voltage (TA = +25°C) 10 Hz ≤ f ≤ 100 kHz Output Resistance f = 1.0 kHz Short Circuit Current Limit (TA = +25°C) Vin = 35 Vdc Peak Output Current (TJ = +25°C) Average Temperature Coefficient of Output Voltage NOTES: MCT7824C Symbol Min Typ Max Min Typ Max Unit VO VO 23 24 25 23 24 25 Vdc — 22.8 — 24 — 25.2 22.8 — 24 — 25.2 — — — 12 6.0 480 240 — — 12 6.0 480 240 — — 5.0 4.0 480 240 — — 5.0 4.0 480 240 — 5.5 8.0 — 5.5 8.0 — — — — — — — 1.0 0.5 — — — — — — 1.0 — 0.5 — 56 — — 56 — — 2.0 — — 2.0 — Vdc Regline mV Regload IB ∆IB mV mA RR VI – VO Vn rO ISC Imax TCVO mA dB Vdc µV/VO — 10 — — 10 — — 20 — — 20 — — 0.2 — — 0.2 — — 2.2 — — 2.2 — A — –1.5 — — –1.5 — mV/°C mΩ A 1. Tlow = 0°C for MCT78XXC = – 40°C for MCT78XXB Thigh = +125°C for MCT78XXB, C. When the junction temperature exceeds +125°C, internal current limiting will reduce the output current to less than 1.0 A at a VI–VO of 15 V or greater. The MC7800 die will supply more current under the same conditions. 2. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. MOTOROLA MCT7800 7 MCT7800 Figure 1. Peak Output Current as a Function of Input-Output Differential Voltage Figure 2. Ripple Rejection as a Function of Output Voltages (MCT78XXC) 80 3.0 2.0 TJ = – 40°C 1.0 TJ = +25°C RR, RIPPLE REJECTION (dB) I O , OUTPUT CURRENT (A) 4.0 TJ = +125°C 10 20 30 40 VI – VO, INPUT-OUPUT VOLTAGE DIFFERENTIAL (V) 0 0 60 Device 50 40 4.0 Figure 3. Ripple Rejection as a Function of Frequency (MCT78XXC) 6.0 8.0 Vin 10 V 19 V 23 V 10 12 14 16 18 VO, OUTPUT VOLTAGE (V) 20 22 24 1000 Z O, OUTPUT IMPEDANCE (mΩ ) RR, RIPPLE REJECTION (dB) MCT7805C MCT7812C MCT7815C Figure 4. Output Impedance as a Function of Output Voltage (MCT78XXC) 80 60 Vin = 10 V VO = 5.0 V IO = 20 mA 40 20 10 f = 120 Hz IO = 20 mA ∆Vin = 1.0 Vrms 70 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k 500 300 200 100 f = 120 Hz IO = 500 mA CL = 0 µF 50 30 20 10 4.0 8.0 12 16 VO, OUTPUT VOLTAGE (V) 20 24 Figure 5. Quiescent Current as a Function of Temperature I B, QUIESCENT CURRENT (mA) 6.0 4.0 2.0 1.0 0 –75 MCT7800 8 Vin = 10 V VO = 5.0 V IO = 20 mA 3.0 – 50 – 25 0 25 50 75 TJ, JUNCTION TEMPERATURE (°C) 100 125 MOTOROLA MCT7800 APPLICATIONS INFORMATION Design Considerations The MCT7800 Series of fixed voltage regulators are designed with thermal overload protection that shuts down the circuit when subjected to an excessive power overload condition, internal short circuit protection that limits the maximum current the circuit will pass, and output transistor safe-area compensation that reduces the output short circuit current as the voltage across the pass transistor is increased. In many low current applications, compensation capacitors are not required. However, it is recommended that the regulator input be bypassed with a capacitor if the regulator is connected to the power supply filter with long wire lengths, or if the output load capacitance is large. An input bypass capacitor should be selected to provide good high frequency characteristics to insure stable operation under all load conditions. A 0.33 µF or larger tantalum, mylar, or other capacitor having low internal impedance at high frequencies, should be chosen. The bypass capacitor should be mounted with the shortest possible leads directly across the regulators’ input terminals. Normally, good construction techniques should be used to minimize ground loops and lead resistance drops since the regulator has no external sense lead. Figure 6. Worst Case Power Dissipation versus Ambient Temperature (Case 221A) θHS = 0°C/W 16 θHS = 5°C/W 12 θHS = 15°C/W 8.0 4.0 0 – 50 2.5 θJC = 5°C/W θJA = 65°C/W TJ(max) = +150°C V I – VO , INPUT-OUTPUT VOLTAGE DIFFERENTIAL (V) PD, POWER DISSIPATION (W) 20 Figure 7. Input Output Differential as a Function of Junction Temperature No Heatsink – 25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (°C) 125 IO = 1.0 A 2.0 200 mA 500 mA 1.5 20 mA 0 mA 1.0 ∆VO = 2% of VO – – – Extended Curve for MCT78XXB 0.5 0 –75 150 – 50 – 25 0 25 50 75 TJ, JUNCTION TEMPERATURE (°C) 100 125 JUNCTION-TO-AIR (° C/W) R θ JA, THERMAL RESISTANCE 80 3.5 PD(max) for TA = 50°C 70 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Free Air Mounted Vertically 60 2.0 oz. Copper L Minimum Size Pad 50 L 40 RθJA 30 3.0 2.5 2.0 1.5 PD, MAXIMUM POWER DISSIPATION (W) Figure 8. D2PAK Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length 1.0 0 5.0 10 15 20 25 30 L, LENGTH OF COPPER (mm) DEFINITIONS Line Regulation — The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. Load Regulation — The change in output voltage for a change in load current at constant chip temperature. Maximum Power Dissipation — The maximum total device dissipation for which the regulator will operate within specifications. MOTOROLA Quiescent Current — That part of the input current that is not delivered to the load. Output Noise Voltage — The rms AC voltage at the output, with constant load and no input ripple, measured over a specified frequency range. Long Term Stability — Output voltage stability under accelerated life test conditions with the maximum rated voltage listed in the devices’ electrical characteristics and maximum power dissipation. MCT7800 9 MCT7800 OUTLINE DIMENSIONS T SUFFIX PLASTIC PACKAGE CASE 221A-06 -TF B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIM Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. SEATING PLANE C T S DIM A B C D F G H J K L N Q R S T U V Z 4 A Q 1 2 3 U H K Z R L J V G D INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 — — 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 — — 2.04 N D2T SUFFIX PLASTIC PACKAGE CASE 936-03 (D2PAK) OPTIONAL CHAMFER A TERMINAL 4 -T- U E S K V B H F 1 2 3 M P J N D R 0.010 (0.254) M T G C MCT7800 10 L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A AND K. 4. DIMENSIONS U AND V ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 4. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAXIMUM. DIM A B C D E F G H J K L M N P R S U V INCHES MIN MAX 0.386 0.403 0.356 0.368 0.170 0.180 0.026 0.036 0.045 0.055 0.051 REF 0.100 BSC 0.539 0.579 0.125 MAX 0.050 REF 0.000 0.010 0.088 0.102 0.018 0.026 0.058 0.078 5 _ REF 0.116 REF 0.200 MIN 0.250 MIN MILLIMETERS MIN MAX 9.804 10.236 9.042 9.347 4.318 4.572 0.660 0.914 1.143 1.397 1.295 REF 2.540 BSC 13.691 14.707 3.175 MAX 1.270 REF 0.000 0.254 2.235 2.591 0.457 0.660 1.473 1.981 5 _ REF 2.946 REF 5.080 MIN 6.350 MIN MOTOROLA MCT7800 NOTES MOTOROLA MCT7800 11 MCT7800 Motorola reserves the right to make changes without further notice to any products herein. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MCT7800 12 ◊ *MCT7800/D* 1PHX33530-3 PRINTED IN USA (8/94) MPS/POD LINEAR YCAAAA MCT7800/D MOTOROLA DISCRETE SEMICONDUCTORS DATA SHEET BS250 P-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor DESCRIPTION BS250 QUICK REFERENCE DATA P-channel enhancement mode vertical D-MOS transistor in TO-92 variant envelope and intended for use in relay, high-speed and line-transformer drivers. Drain-source voltage −VDS max. Gate-source voltage (open drain) ±VGSO max. 20 V Drain current (DC) −ID max. 0.25 A Ptot max. 0.83 W FEATURES Drain-source ON-resistance RDS(on) typ. max. 9 Ω 14 Ω Yfs typ. 125 mS Total power dissipation up to Tamb = 25 °C −ID = 200 mA; −VGS = 10 V • Low RDS(on) • Direct interface to C-MOS Transfer admittance • High-speed switching −ID = 200 mA; −VDS = 15 V • No second breakdown PINNING - TO-92 VARIANT 1 = source 2 = gate 3 = drain PIN CONFIGURATION d handbook, halfpage 1 2 3 g MAM147 s Note: Various pinout configurations available. Fig.1 Simplified outline and symbol. April 1995 45 V 2 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BS250 RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage −VDS max. Gate-source voltage (open drain) ± VGSO max. 20 V Drain current (DC) −ID max. 0.25 A Drain current (peak value) −IDM max. 0.5 A Total power dissipation up to Tamb = 25 °C (note 1) Ptot max. 0.83 W Storage temperature range Tstg Junction temperature Tj max. 150 °C Rth j-a = 150 K/W 45 V −65 to + 150 °C THERMAL RESISTANCE From junction to ambient (note 1) Note 1. Transistor mounted on printed-circuit board, max. lead length 4 mm. CHARACTERISTICS Tj = 25 °C unless otherwise specified Drain-source breakdown voltage − ID = 100 µA; VGS = 0 −V(BR)DSS min. 45 V −IDSS max. 0.5 µA −IGSS max. 20 nA −VGS(th) min. max. 1.0 V 3.5 V RDS(on) typ. max. 9 Ω 14 Ω Yfs typ. 125 mS Ciss typ. max. 30 pF 45 pF Coss typ. max. 20 pF 30 pF Crss typ. max. 5 pF 10 pF Drain-source leakage current −VDS = 25 V; VGS = 0 Gate-source leakage current −VGS = 15 V; VDS = 0 Gate threshold voltage −ID = 1 mA; VDS = VGS Drain-source ON-resistance −ID = 200 mA; −VGS = 10 V Transfer admittance −ID = 200 mA; −VDS = 15 V Input capacitance at f = 1 MHz −VDS = 10 V; VGS = 0 Output capacitance at f = 1 MHz −VDS = 10 V; VGS = 0 Feedback capacitance at f = 1 MHz −VDS = 10 V; VGS = 0 April 1995 3 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BS250 Switching times (see Figs 2 and 3) ton toff −ID = 200 mA; −VDD = 40 V; −VGS = 0 to 10 V Fig.2 Switching times test circuit. April 1995 typ. typ. 4 ns 10 ns Fig.3 Input and output waveforms. 4 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BS250 PACKAGE OUTLINES Plastic single-ended leaded (through hole) package; 3 leads (on-circle) SOT54 variant c L2 E d A L b 1 e1 2 e D 3 b1 L1 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A b b1 c D d E e e1 L L1(1) max L2 max mm 5.2 5.0 0.48 0.40 0.66 0.56 0.45 0.40 4.8 4.4 1.7 1.4 4.2 3.6 2.54 1.27 14.5 12.7 2.5 2.5 Notes 1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities. OUTLINE VERSION SOT54 variant April 1995 REFERENCES IEC JEDEC EIAJ TO-92 SC-43 5 EUROPEAN PROJECTION ISSUE DATE 97-04-14 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BS250 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. April 1995 6 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor NOTES April 1995 7 BS250 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 137107/00/01/pp8 Date of release: April 1995 Document order number: 9397 750 02458 BZX85C... TELEFUNKEN Semiconductors Silicon Epitaxial Planar Z–Diodes Features Sharp edge in reverse characteristics Low reverse current Low noise Very high stability Available with tighter tolerances Applications 94 9369 Voltage stabilization Absolute Maximum Ratings Tj = 25C Parameter Power dissipation Test Conditions Type l=4mm, TL=25C Junction temperature Storage temperature range Symbol Value Unit PV 1.3 W Tj 175 C Tstg –65...+175 C Symbol Value Unit RthJA 110 K/W Maximum Thermal Resistance Tj = 25C Parameter Junction ambient Test Conditions l=4mm, TL=constant Characteristics Tj = 25C Parameter Forward voltage Rev. A1: 12.12.1994 Test Conditions IF=200mA Type Symbol VF Min Typ Max Unit 1 V 1 BZX85C... Type 1) 2 TELEFUNKEN Semiconductors VZnorm IZT for VZT 1) and rzjT rzjk at IZK IR at VR TKVZ BZX85C... V mA V mA A V %/K 2V7 2.7 80 2.5 to 2.9 < 20 < 400 1 < 150 1 –0.08 to –0.05 3V0 3.0 80 2.8 to 3.2 < 20 < 400 1 < 100 1 –0.08 to –0.05 3V3 3.3 80 3.1 to 3.5 < 20 < 400 1 < 40 1 –0.08 to –0.05 3V6 3.6 60 3.4 to 3.8 < 20 < 500 1 < 20 1 –0.08 to –0.05 3V9 3.9 60 3.7 to 4.1 < 15 < 500 1 < 10 1 –0.07 to –0.02 4V3 4.3 50 4.0 to 4.6 < 13 < 500 1 <3 1 –0.07 to –0.01 4V7 4.7 45 4.4 to 5.0 < 13 < 600 1 <3 1 –0.03 to +0.04 5V1 5.1 45 4.8 to 5.4 < 10 < 500 1 <1 1.5 –0.01 to +0.04 5V6 5.6 45 5.2 to 6.0 <7 < 400 1 <1 2 0 to +0.045 6V2 6.2 35 5.8 to 6.6 <4 < 300 1 <1 3 +0.01 to +0.055 6V8 6.8 35 6.4 to 7.2 < 3.5 < 300 1 <1 4 +0.015 to +0.06 7V5 7.5 35 7.0 to 7.9 <3 < 200 0.5 <1 4.5 +0.02 to +0.065 8V2 8.2 25 7.7 to 8.7 <5 < 200 0.5 <1 6.2 0.03 to 0.07 9V1 9.1 25 8.5 to 9.6 <5 < 200 0.5 <1 6.8 0.035 to 0.075 10 10 25 9.4 to 10.6 <7 < 200 0.5 < 0.5 7 0.04 to 0.08 11 11 20 10.4 to 11.6 <8 < 300 0.5 < 0.5 8.2 0.045 to 0.08 12 12 20 11.4 to 12.7 <9 < 350 0.5 < 0.5 9.1 0.045 to 0.085 13 13 20 12.4 to 14.1 < 10 < 400 0.5 < 0.5 10 0.05 to 0.085 15 15 15 13.8 to 15.6 < 15 < 500 0.5 < 0.5 11 0.055 to 0.09 16 16 15 15.3 to 17.1 < 15 < 500 0.5 < 0.5 12 0.055 to 0.09 18 18 15 16.8 to 19.1 < 20 < 500 0.5 < 0.5 13 0.06 to 0.09 20 20 10 18.8 to 21.2 < 24 < 600 0.5 < 0.5 15 0.06 to 0.09 22 22 10 20.8 to 23.3 < 25 < 600 0.5 < 0.5 16 0.06 to 0.095 24 24 10 22.8 to 25.6 < 25 < 600 0.5 < 0.5 18 0.06 to 0.095 27 27 8 25.1 to 28.9 < 30 < 750 0.25 < 0.5 20 0.06 to 0.095 30 30 8 28 to 32 < 30 < 1000 0.25 < 0.5 22 0.06 to 0.095 33 33 8 31 to 35 < 35 < 1000 0.25 < 0.5 24 0.06 to 0.095 36 36 8 34 to 38 < 40 < 1000 0.25 < 0.5 27 0.06 to 0.095 39 39 6 37 to 41 < 50 < 1000 0.25 < 0.5 30 0.06 to 0.095 43 43 6 40 to 46 < 50 < 1000 0.25 < 0.5 33 0.06 to 0.095 47 47 4 44 to 50 < 90 < 1500 0.25 < 0.5 36 0.06 to 0.095 51 51 4 48 to 54 < 115 < 1500 0.25 < 0.5 39 0.06 to 0.095 56 56 4 52 to 60 < 120 < 2000 0.25 < 0.5 43 0.06 to 0.095 62 62 4 58 to 66 < 125 < 2000 0.25 < 0.5 47 0.06 to 0.095 68 68 4 64 to 72 < 130 < 2000 0.25 < 0.5 51 0.06 to 0.095 75 75 4 70 to 79 < 135 < 2000 0.25 < 0.5 56 0.06 to 0.095 Tighter tolerances available on request. Rev. A1: 12.12.1994 BZX85C... TELEFUNKEN Semiconductors R thJA – Therm. Resist. Junction / Ambient ( K/W ) Typical Characteristics (Tj = 25C unless otherwise specified) Ptot – Total Power Dissipation ( W ) 2.0 1.6 1.2 l=4mm 0.8 l=10mm l=20mm 0.4 0 –50 0 50 100 150 200 Tamb – Ambient Temperature ( °C ) 95 9612 250 200 150 l 50 0 5 10 15 20 25 30 l – Lead Length ( mm ) 95 9613 Figure 2 : Thermal Resistance vs. Lead Length 1000 1000 r Z – Differential Z-Resistance ( W ) C D – Diode Capacitance ( pF ) TL=constant 0 Figure 1 : Total Power Dissipation vs. Ambient Temperature 100 VR = 0V VR = 2V VR = 5V VR = 20V VR = 30V 10 f = 1 MHz Tamb= 25°C 1 0 10 20 IZ=1mA 2mA 100 5mA 10mA 20mA 10 1 30 50 40 60 1 VZ – Z-Voltage ( V ) 95 9616 10 100 VZ – Z-Voltage ( V ) 95 9615 Figure 3 : Diode Capacitance vs. Z–Voltage Z thp – Thermal Resistance for Pulse Cond. (K/W) l 100 Figure 4 : Differential Z–Resistance vs. Z–Voltage 1000 tp/T=0.01 tp/T=0.1 100 tp/T=0.5 RthJA=110K/W DT=Tjmax–Tamb tp/T=0.02 tp/T=0.05 tp/T=0.2 10 Single Pulse 1 10–1 100 iZM=(–VZ+(VZ2+4rzjDT/Zthp)1/2)/(2rzj) 101 102 103 tp – Pulse Length ( ms ) 95 9614 Figure 5 : Thermal Response Rev. A1: 12.12.1994 3 BZX85C... TELEFUNKEN Semiconductors Dimensions in mm Cathode Identification technical drawings according to DIN specifications ∅ 0.85 max. ∅ 2.5 max. Standard Glass Case 54 B 2 DIN 41880 JEDEC DO 41 Weight max. 0.3 g 4 26 min. 4.1 max. 26 min. 94 9368 Rev. A1: 12.12.1994 TELEFUNKEN Semiconductors BZX85C... OZONE DEPLETING SUBSTANCES POLICY STATEMENT It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to 1. Meet all present and future national and international statutory requirements and 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. Of particular concern is the control or elimination of releases into the atmosphere of those substances which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) will soon severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuous improvements to eliminate the use of any ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA and 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC can certify that our semiconductors are not manufactured with and do not contain ozone depleting substances. We reserve the right to make changes to improve technical design without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax Number: 49 ( 0 ) 7131 67 2423 Rev. A1: 12.12.1994 5 CD4093BM/CD4093BC Quad 2-Input NAND Schmitt Trigger Y General Description Y The CD4093B consists of four Schmitt-trigger circuits. Each circuit functions as a 2-input NAND gate with Schmitt-trigger action on both inputs. The gate switches at different points for positive and negative-going signals. The difference between the positive (VT a ) and the negative voltage (VTb) is defined as hysteresis voltage (VH). All outputs have equal source and sink currents and conform to standard B-series output drive (see Static Electrical Characteristics). Y Y Applications Y Features Y Y Y Y Wide supply voltage range Schmitt-trigger on each input with no external components Noise immunity greater than 50% 3.0V to 15V Equal source and sink currents No limit on input rise and fall time Standard B-series output drive Hysteresis voltage (any input) TA e 25§ C VH e 1.5V Typical VDD e 5.0V VDD e 10V VH e 2.2V VDD e 15V VH e 2.7V Guaranteed VH e 0.1 VDD Y Y Y Wave and pulse shapers High-noise-environment systems Monostable multivibrators Astable multivibrators NAND logic Connection Diagram Dual-In-Line Package TL/F/5982 – 1 Top View Order Number CD4093B C1995 National Semiconductor Corporation TL/F/5982 RRD-B30M105/Printed in U. S. A. CD4093BM/CD4093BC Quad 2-Input NAND Schmitt Trigger February 1993 Absolute Maximum Ratings (Notes 1 & 2) Recommended Operating Conditions (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4093BM CD4093BC b 0.5 to a 18 VDC b 0.5 to VDD a 0.5 VDC b 65§ C to a 150§ C 3 to 15 VDC 0 to VDD VDC b 55§ C to a 125§ C b 40§ C to a 85§ C 700 mW 500 mW 260§ C DC Electrical Characteristics CD4093BM (Note 2) Symbol Parameter b 55§ C Conditions Min Max IDD Quiescent Device Current VDD e 5V VDD e 10V VDD e 15V 0.25 0.5 1.0 VOL Low Level Output Voltage VIN e VDD, lIOl k 1 mA VDD e 5V VDD e 10V VDD e 15V 0.05 0.05 0.05 High Level Output Voltage VIN e VSS, lIOl k 1 mA VDD e 5V VDD e 10V VDD e 15V 4.95 9.95 14.95 Negative-Going Threshold Voltage (Any Input) lIOl k 1 mA VDD e 5V, VO e 4.5V VDD e 10V, VO e 9V VDD e 15V, VO e 13.5V 1.3 2.85 4.35 Positive-Going Threshold Voltage (Any Input) lIOl k 1 mA VDD e 5V, VO e 0.5V VDD e 10V, VO e 1V VDD e 15V, VO e 1.5V VH Hysteresis (VT a b VTb) (Any Input) IOL VOH VTb VT a IOH IIN a 25§ C Min Typ 0 0 0 a 125§ C Max Min Units Max 0.25 0.5 1.0 7.5 15.0 30.0 mA mA mA 0.05 0.05 0.05 0.05 0.05 0.05 V V V 4.95 9.95 14.95 5 10 15 2.25 4.5 6.75 1.5 3.0 4.5 1.8 4.1 6.3 2.25 4.5 6.75 1.5 3.0 4.5 2.3 4.65 6.9 V V V 2.75 5.5 8.25 3.65 7.15 10.65 2.75 5.5 8.25 3.3 6.2 9.0 3.5 7.0 10.5 2.65 5.35 8.1 3.5 7.0 10.5 V V V VDD e 5V VDD e 10V VDD e 15V 0.5 1.0 1.5 2.35 4.30 6.30 0.5 1.0 1.5 1.5 2.2 2.7 2.0 4.0 6.0 0.35 0.70 1.20 2.0 4.0 6.0 V V V Low Level Output Current (Note 3) VIN e VDD VDD e 5V, VO e 0.4V VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V 0.64 1.6 4.2 0.51 1.3 3.4 0.88 2.25 8.8 0.36 0.9 2.4 mA mA mA High Level Output Current (Note 3) VIN e VSS VDD e 5V, VO e 4.6V VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V b 0.64 b 1.6 b 4.2 0.51 b 1.3 b 3.4 b 0.88 b 2.25 b 8.8 b 0.36 b 0.9 b 2.4 mA mA mA Input Current VDD e 15V, VIN e 0V VDD e 15V, VIN e 15V 4.95 9.95 14.95 V V V b 0.1 b 10 b 5 b 0.1 b 1.0 0.1 10b5 0.1 1.0 mA mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: IOH and IOL are tested one output at a time. 2 DC Electrical Characteristics CD4093BC (Note 2) Symbol Parameter b 40§ C Conditions Min Max IDD Quiescent Device Current VDD e 5V VDD e 10V VDD e 15V 1.0 2.0 4.0 VOL Low Level Output Voltage VIN e VDD, lIOl k 1 mA VDD e 5V VDD e 10V VDD e 15V 0.05 0.05 0.05 High Level Output Voltage VIN e VSS, lIOl k 1 mA VDD e 5V VDD e 10V VDD e 15V 4.95 9.95 14.95 Negative-Going Threshold Voltage (Any Input) lIOl k 1 mA VDD e 5V, VO e 4.5V VDD e 10V, VO e 9V VDD e 15V, VO e 13.5V 1.3 2.85 4.35 Positive-Going Threshold Voltage (Any Input) lIOl k 1 mA VDD e 5V, VO e 0.5V VDD e 10V, VO e 1V VDD e 15V, VO e 1.5V VH Hysteresis (VT a b VTb) (Any Input) IOL VOH VTb VT a IOH IIN a 25§ C Min Typ 0 0 0 a 85§ C Max Min Units Max 1.0 2.0 4.0 7.5 15.0 30.0 mA mA mA 0.05 0.05 0.05 0.05 0.05 0.05 V V V 4.95 9.95 14.95 5 10 15 2.25 4.5 6.75 1.5 3.0 4.5 1.8 4.1 6.3 2.25 4.5 6.75 1.5 3.0 4.5 2.3 4.65 6.9 V V V 2.75 5.5 8.25 3.6 7.15 10.65 2.75 5.5 8.25 3.3 6.2 9.0 3.5 7.0 10.5 2.65 5.35 8.1 3.5 7.0 10.5 V V V VDD e 5V VDD e 10V VDD e 15V 0.5 1.0 1.5 2.35 4.3 6.3 0.5 1.0 1.5 1.5 2.2 2.7 2.0 4.0 6.0 0.35 0.70 1.20 2.0 4.0 6.0 V V V Low Level Output Current (Note 3) VIN e VDD VDD e 5V, VO e 0.4V VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V 0.52 1.3 3.6 0.44 1.1 3.0 0.88 2.25 8.8 0.36 0.9 2.4 mA mA mA High Level Output Current (Note 3) VIN e VSS VDD e 5V, VO e 4.6V VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V b 0.52 b 1.3 b 3.6 0.44 b 1.1 b 3.0 b 0.88 b 2.25 b 8.8 b 0.36 b 0.9 b 2.4 mA mA mA Input Current VDD e 15V, VIN e 0V VDD e 15V, VIN e 15V 4.95 9.95 14.95 V V V b 0.3 b 10 b 5 b 0.3 b 1.0 0.3 10b5 0.3 1.0 mA mA AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, RL e 200k, Input tr, tf e 20 ns, unless otherwise specified Typ Max Units tPHL, tPLH Symbol Propagation Delay Time Parameter VDD e 5V VDD e 10V VDD e 15V Conditions 300 120 80 450 210 160 ns ns ns tTHL, tTLH Transition Time VDD e 5V VDD e 10V VDD e 15V 90 50 40 145 75 60 ns ns ns CIN Input Capacitance (Any Input) 5.0 7.5 pF CPD Power Dissipation Capacitance (Per Gate) 24 *AC Parameters are guaranteed by DC correlated testing. Note 2: VSS e 0V unless otherwise specified. Note 3: IOH and IOL are tested one output at a time. 3 Min pF Typical Applications Gated Oscillator TL/F/5982 – 2 Assume t1 a t2 ll tPHL a tPLH then: t0 e RC fin [VDD/VTb] t1 e RC fin [(VDD b VTb)/(VDD b VT a )] t2 e RC fin [VT a /VTb] fe 1 e t1 a t2 1 (VT a ) (VDD b VTb) RC fin (VTb)(VDD b VT a ) TL/F/5982 – 3 Gated One-Shot TL/F/5982 – 4 TL/F/5982 – 5 (a) Negative-Edge Triggered TL/F/5982 – 6 TL/F/5982 – 7 (b) Positive-Edge Triggered 4 Typical Performance Characteristics Typical Transfer Characteristics Guaranteed Hysteresis vs VDD TL/F/5982 – 8 TL/F/5982 – 9 Guaranteed Trigger Threshold Voltage vs VDD Guaranteed Hysteresis vs VDD TL/F/5982 – 10 TL/F/5982 – 11 Input and Output Characteristics Output Characteristic Input Characteristic TL/F/5982–12 TL/F/5982 – 13 VNML e VIH(MIN) b VOL j VIH(MIN) e VT a (MIN) VNMH e VOH b VIL(MAX) j VDD b VIL(MAX) e VDD b VTb(MAX) AC Test Circuits and Switching Time Waveforms TL/F/5982 – 14 TL/F/5982 – 15 5 CD4093BM/CD4093BC Quad 2-Input NAND Schmitt Trigger Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number CD4093BMJ or CD4093BCJ NS Package Number J14A Molded Dual-In-Line Package (N) Order Number CD4093BM or CD4093BCN NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. HN58C256A Series HN58C257A Series 256k EEPROM (32-kword × 8-bit) Ready/Busy and RES function (HN58C257A) ADE-203-410D (Z) Rev. 4.0 Oct. 24, 1997 Description The Hitachi HN58C256A and HN58C257A are electrically erasable and programmable ROMs organized as 32768-word × 8-bit. They have realized high speed low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte page programming function to make their write operations faster. Features • Single 5 V supply: 5 V ±10% • Access time: 85 ns/100 ns (max) • Power dissipation Active: 20 mW/MHz, (typ) Standby: 110 µW (max) • On-chip latches: address, data, CE, OE, WE • Automatic byte write: 10 ms max • Automatic page write (64 bytes): 10 ms max • Ready/Busy (only the HN58C257A series) • Data polling and Toggle bit • Data protection circuit on power on/off • Conforms to JEDEC byte-wide standard • Reliable CMOS with MNOS cell technology • 105 erase/write cycles (in page mode) • 10 years data retention • Software data protection • Write protection by RES pin (only the HN58C257A series) • Industrial versions (Temperature range: – 20 to 85˚C and – 40 to 85°C) are also available. HN58C256A Series, HN58C257A Series Ordering Information Type No. Access time Package HN58C256AP-85 HN58C256AP-10 85 ns 100 ns 600 mil 28-pin plastic DIP (DP-28) HN58C256AFP-85 HN58C256AFP-10 85 ns 100 ns 400 mil 28-pin plastic SOP (FP-28D) HN58C256AT-85 HN58C256AT-10 85 ns 100 ns 28-pin plastic TSOP (TFP-28DB) HN58C257AT-85 HN58C257AT-10 85 ns 100 ns 8 × 14 mm2 32-pin plastic TSOP (TFP-32DA) Pin Arrangement HN58C256AP/AFP Series A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) HN58C256AT Series VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A3 A4 A5 A6 A7 A12 A14 VCC WE A13 A8 A9 A11 OE 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A4 A5 A6 A7 A12 A14 RDY/Busy VCC RES WE A13 A8 A9 A11 OE (Top view) HN58C257AT Series A2 A1 A0 NC I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 NC CE A10 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (Top view) 2 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HN58C256A Series, HN58C257A Series Pin Description Pin name Function A0 to A14 Address input I/O0 to I/O7 Data input/output OE Output enable CE Chip enable WE Write enable VCC Power supply VSS Ground RDY/Busy* RES* 1 1 Reset NC Note: Ready busy No connection 1. This function is supported by only the HN58C257A series. Block Diagram Note: This function is supported by only the HN58C257A series. I/O0 VCC to I/O7 RDY/Busy *1 High voltage generator VSS RES *1 I/O buffer and input latch OE CE Control logic and timing WE RES *1 A0 Y decoder to Y gating A5 Address buffer and latch X decoder Memory array A6 to A14 Data latch 3 HN58C256A Series, HN58C257A Series Operation Table Operation CE OE WE RES* 3 1 RDY/Busy* 3 I/O High-Z Dout VIL VIL VIH VH * Standby VIH ×* × × High-Z High-Z Write VIL VIH VIL VH High-Z to V OL Din Deselect VIL VIH VIH VH High-Z High-Z Write inhibit × × VIH × — — × VIL × × — — Data polling VIL VIL VIH VH VOL Dout (I/O7) Program reset × × × VIL High-Z High-Z Read 2 Notes: 1. Refer to the recommended DC operating condition. 2. × : Don’t care 3. This function is supported by only the HN58C257A series. Absolute Maximum Ratings Parameter Symbol Value Power supply voltage relative to V SS VCC –0.6 to +7.0 Vin 1 –0.5* to +7.0* Topr 0 to +70 °C Tstg –55 to +125 °C Input voltage relative to V SS Operating temperature range* Storage temperature range 2 Notes: 1. Vin min = –3.0 V for pulse width ≤ 50 ns 2. Including electrical characteristics and data retention 3. Should not exceed VCC + 1 V. 4 Unit V 3 V HN58C256A Series, HN58C257A Series Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 4.5 5.0 5.5 V VSS 0 0 0 V — 0.8 Input voltage 1 VIL –0.3* VIH VH * Operating temperature 3 Topr V 2 2.2 — VCC + 0.3* V VCC – 0.5 — VCC + 1.0 V 0 — 70 °C Notes: 1. VIL min: –1.0 V for pulse width ≤ 50 ns. 2. VIH max: VCC + 1.0 V for pulse width ≤ 50 ns. 3. This function is supported by only the HN58C257A series. DC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V±10%) Parameter Symbol Min Typ Max 1 Unit Test conditions µA VCC = 5.5 V, Vin = 5.5 V Input leakage current I LI — — 2* Output leakage current I LO — — 2 µA VCC = 5.5 V, Vout = 5.5/0.4 V Standby V CC current I CC1 — — 20 µA CE = VCC I CC2 — — 1 mA CE = VIH I CC3 — — 12 mA Iout = 0 mA, Duty = 100%, Cycle = 1 µs at VCC = 5.5 V — — 30 mA Iout = 0 mA, Duty = 100%, Cycle = 85 ns at VCC = 5.5 V Operating VCC current Output low voltage VOL — — 0.4 V I OL = 2.1 mA Output high voltage VOH 2.4 — — V I OH = –400 µA Note: 1. I LI on RES = 100 µA max (only the HN58C257A series) Capacitance (Ta = +25°C, f = 1 MHz) Parameter 1 Input capacitance* Output capacitance* Note: 1 Symbol Min Typ Max Unit Test conditions Cin — — 6 pF Vin = 0 V Cout — — 12 pF Vout = 0 V 1. This parameter is periodically sampled and not 100% tested. 5 HN58C256A Series, HN58C257A Series AC Characteristics (Ta = 0 to +70°C, VCC = 5 V±10%) Test Conditions • Input pulse levels: 0.4 V to 3.0 V 0 V to VCC (RES pin*2) • Input rise and fall time: ≤ 5 ns • Input timing reference levels: 0.8, 2.0 V • Output load: 1TTL Gate +100 pF • Output reference levels: 1.5 V, 1.5 V Read Cycle HN58C256A/HN58C257A -85 -10 Parameter Symbol Min Max Min Max Unit Test conditions Address to output delay t ACC — 85 — 100 ns CE = OE = VIL, WE = VIH CE to output delay t CE — 85 — 100 ns OE = VIL, WE = VIH OE to output delay t OE 10 40 10 50 ns CE = VIL, WE = VIH Address to output hold t OH 0 — 0 — ns CE = OE = VIL, WE = VIH OE (CE) high to output float*1 t DF 0 40 0 40 ns CE = VIL, WE = VIH RES low to output float* t DFR 0 350 0 350 ns CE = OE = VIL, WE = VIH t RR 0 450 0 450 ns CE = OE = VIL, WE = VIH RES to output delay*2 6 1, 2 HN58C256A Series, HN58C257A Series Write Cycle Parameter Symbol Min*3 Typ Max Unit Address setup time t AS 0 — — ns Address hold time t AH 50 — — ns CE to write setup time (WE controlled) t CS 0 — — ns CE hold time (WE controlled) t CH 0 — — ns WE to write setup time (CE controlled) t WS 0 — — ns WE hold time (CE controlled) t WH 0 — — ns OE to write setup time t OES 0 — — ns OE hold time t OEH 0 — — ns Data setup time t DS 50 — — ns Data hold time t DH 0 — — ns WE pulse width (WE controlled) t WP 100 — — ns CE pulse width (CE controlled) t CW 100 — — ns Data latch time t DL 50 — — ns Byte load cycle t BLC 0.2 — 30 µs Byte load window t BL 100 — — µs 4 Write cycle time t WC — — 10* Time to device busy t DB 120 — — ns — — ns Write start time Reset protect time* 2, 6 Reset high time* 2 5 Test conditions ms t DW 0* t RP 100 — — µs t RES 1 — — µs Notes: 1. t DF and t DFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. This function is supported by only the HN58C257A series. 3. Use this device in longer cycle than this value. 4. t WC must be longer than this value unless polling techniques or RDY/Busy (only the HN58C257A series) are used. This device automatically completes the internal write operation within this value. 5. Next read or write operation can be initiated after t DW if polling techniques or RDY/Busy (only the HN58C257A series) are used. 6. This parameter is sampled and not 100% tested. 7. A6 through A14 are page address and these addresses are latched at the first falling edge of WE. 8. A6 through A14 are page address and these addresses are latched at the first falling edge of CE. 9. See AC read characteristics. 7 HN58C256A Series, HN58C257A Series Read Timing Waveform Address tACC CE tOH tCE OE tDF tOE WE High Data Out Data out valid tRR tDFR RES *2 8 HN58C256A Series, HN58C257A Series Byte Write Timing Waveform (1) (WE Controlled) tWC Address tCS tAH tCH CE tAS tBL tWP WE tOES tOEH OE tDS tDH Din tDW High-Z RDY/Busy *2 tDB High-Z tRP tRES RES *2 VCC 9 HN58C256A Series, HN58C257A Series Byte Write Timing Waveform (2) (CE Controlled) Address tWS tAH tBL tWC tCW CE tAS tWH WE tOES tOEH OE tDS tDH Din tDW RDY/Busy *2 tDB High-Z tRP tRES RES *2 VCC 10 High-Z HN58C256A Series, HN58C257A Series Page Write Timing Waveform (1) (WE Controlled) *7 Address A0 to A14 tAS tAH tBL tWP WE tDL tCS tBLC tWC tCH CE tOEH tOES OE tDH tDS Din RDY/Busy *2 High-Z tDB tDW High-Z tRP RES *2 tRES VCC 11 HN58C256A Series, HN58C257A Series Page Write Timing Waveform (2) (CE Controlled) *8 Address A0 to A14 tAS CE tAH tBL tCW tDL tWS tBLC tWC tWH WE tOEH tOES OE tDH tDS Din RDY/Busy *2 High-Z tRP RES *2 VCC 12 tRES tDB tDW High-Z HN58C256A Series, HN58C257A Series Data Polling Timing Waveform Address An An An CE WE tOEH tCE *9 tOES OE tDW tOE*9 I/O7 Din X Dout X Dout X tWC 13 HN58C256A Series, HN58C257A Series Toggle bit This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program. Toggle bit Waveform Notes: 1. 2. 3. 4. I/O6 beginning state is "1". I/O6 ending state will vary. See AC read characteristics. Any address location can be used, but the address must be fixed. Next mode *4 Address tCE *3 CE WE *3 tOE OE tOES tOEH *1 I/O6 Din Dout Dout tWC 14 *2 *2 Dout Dout tDW HN58C256A Series, HN58C257A Series Software Data Protection Timing Waveform (1) (in protection mode) VCC CE WE tBLC Address Data 5555 AA 2AAA 55 5555 A0 tWC Write address Write data Software Data Protection Timing Waveform (2) (in non-protection mode) VCC tWC Normal active mode CE WE Address Data 5555 2AAA 5555 5555 2AAA 5555 AA 55 80 AA 55 20 15 HN58C256A Series, HN58C257A Series Functional Description Automatic Page Write Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or C E. When CE or WE is high for 100 µs after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Data Polling Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is performing a write operation. RDY/Busy Signal (only the HN58C257A series) RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high impedance except in write cycle and is lowered to V OL after the first write signal. At the end of a write cycle, the RDY/Busy signal changes state to high impedance. RES Signal (only the HN58C257A series) When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low when VCC is switched. RES should be high during read and programming because it doesn't provide a latch function. VCC Read inhibit Read inhibit RES Program inhibit 16 Program inhibit HN58C256A Series, HN58C257A Series WE, CE Pin Operation During a write cycle, addresses are latched by the falling edge of WE or C E, and data is latched by the rising edge of WE or CE. Write/Erase Endurance and Data Retention Time The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed less than 104 cycles. Data Protection 1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20 ns or less. Be careful not to allow noise of a width of more than 20 ns on the control pins. WE CE VIH 0V VIH OE 0V 20 ns max 17 HN58C256A Series, HN58C257A Series 2. Data Protection at VCC On/Off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state. Note: The EEPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET signal. VCC CPU RESET * Unprogrammable * Unprogrammable (1) Protection by CE, OE, WE To realize the unprogrammable state, the input level of control pins must be held as shown in the table below. CE VCC × × OE × VSS × WE × × VCC ×: Don’t care. VCC: Pull-up to VCC level. VSS : Pull-down to V SS level. 18 HN58C256A Series, HN58C257A Series (2) Protection by RES (only the HN58C257A series) The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the EEPROM’s RES pin. RES should be kept VSS level during VCC on/off. The EEPROM breaks off programming operation when RES becomes low, programming operation doesn’t finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms after the last data input. VCC RES Program inhibit WE or CE 1 µs min 100 µs min Program inhibit 10 ms min 19 HN58C256A Series, HN58C257A Series 3. Software data protection To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes code is input. To program data in the SDP enable mode, 3 bytes code must be input before write data. Address Data 5555 AA ↓ ↓ 2AAA 55 ↓ ↓ 5555 A0 ↓ ↓ Write address Write data } Normal data input The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP disable cycle, data can not be written. Address Data 5555 ↓ 2AAA ↓ 5555 ↓ 5555 ↓ 2AAA ↓ 5555 AA ↓ 55 ↓ 80 ↓ AA ↓ 55 ↓ 20 The software data protection is not enabled at the shipment. Note: There are some differences between Hitachi’s and other company’s for enable/disable sequence of software data protection. If there are any questions , please contact with Hitachi sales offices. 20 HN58C256A Series, HN58C257A Series Package Dimensions HN58C256AP Series (DP-28) Unit: mm 35.6 36.5 Max 15 13.4 14.6 Max 28 14 1.2 2.54 ± 0.25 0.48 ± 0.10 0.51 Min 1.9 Max 15.24 2.54 Min 5.70 Max 1 + 0.11 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-28 — Conforms 4.6 g 21 HN58C256A Series, HN58C257A Series Package Dimensions (cont.) HN58C256AFP Series (FP-28D) Unit: mm 18.3 18.8 Max 15 14 1.12 Max 0.17 ± 0.05 0.15 ± 0.04 1 2.50 Max 8.4 28 11.8 ± 0.3 1.7 1.27 0.15 0.40 ± 0.08 0.38 ± 0.06 0.20 M Dimension including the plating thickness Base material dimension 22 0.20 ± 0.10 0° – 8° 1.0 ± 0.2 Hitachi Code JEDEC EIAJ Weight (reference value) FP-28D Conforms — 0.7 g HN58C256A Series, HN58C257A Series Package Dimensions (cont.) HN58C256AT Series (TFP-28DB) Unit: mm 8.00 8.20 Max 15 1 14 11.80 28 0.55 0.22 ± 0.08 0.10 M 0.20 ± 0.06 0.45 Max 0.80 13.40 ± 0.30 Dimension including the plating thickness Base material dimension +0.07 0.13 –0.08 0.10 0.17 ± 0.05 0.15 ± 0.04 1.20 Max 0° – 5° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TFP-28DB — — 0.23 g 23 HN58C256A Series, HN58C257A Series Package Dimensions (cont.) HN58C257AT Series (TFP-32DA) Unit: mm 8.00 8.20 Max 17 1 16 12.40 32 0.50 0.08 M Dimension including the plating thickness Base material dimension 24 0.17 ± 0.05 0.125 ± 0.04 1.20 Max 0.10 0.80 14.00 ± 0.20 0.45 Max 0.13 ± 0.05 0.22 ± 0.08 0.20 ± 0.06 0° – 5° Hitachi Code JEDEC EIAJ Weight (reference value) 0.50 ± 0.10 TFP-32DA Conforms Conforms 0.26 g HN58C256A Series, HN58C257A Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 25 HN58C256A Series, HN58C257A Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.0 Jun. 19, 1995 Initial issue Y. Nagai T. Muto T. Wada 1.0 May. 17, 1996 Change of format Absolute Maximun Ratings Addition of note 4 Recommended DC Operating Conditions VIH (min): 3.0 V to 2.2 V AC Characteristics VOH (min): VCC × 0.8 V to 2.4 V AC Characteristics Input pulse levels: 0 V to 3.0 V to 0.4 V to 3.0 V Data Polling Timing Waveform Addition of note 1 Toggle bit Waveform Addition of note 4 Y. Nagai 2.0 Feb. 27, 1997 Recommended DC Operating Conditions VIL (max): 0.6 V to 0.8 V Functional Description Data Protection 3: Addition of note Y. Nagai K. Furusawa 3.0 May. 20, 1997 Functional Description Data Protection 3: Change of Description M. Terasawa K. Furusawa 4.0 Oct. 24, 1997 Timing Waveforms Read Timing Waveform: Correct error 26 IRF540 IRF540FI N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTORS TYPE IRF540 IRF540FI ■ ■ ■ ■ ■ ■ ■ V DSS R DS( on) ID 100 V 100 V < 0.077 Ω < 0.077 Ω 30 A 16 A TYPICAL RDS(on) = 0.045 Ω AVALANCHE RUGGED TECHNOLOGY 100% AVALANCHE TESTED REPETITIVE AVALANCHE DATA AT 100oC LOW GATE CHARGE HIGH CURRENT CAPABILITY 175oC OPERATING TEMPERATURE APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ SOLENOID AND RELAY DRIVERS ■ REGULATORS ■ DC-DC & DC-AC CONVERTERS ■ MOTOR CONTROL, AUDIO AMPLIFIERS ■ AUTOMOTIVE ENVIRONMENT (INJECTION, ABS, AIR-BAG, LAMPDRIVERS, Etc.) 3 1 3 2 TO-220 1 2 ISOWATT220 INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value IRF540 VD S V DG R V GS Drain-source Voltage (V GS = 0) 100 V Drain- gate Voltage (R GS = 20 kΩ) 100 V ± 20 Gate-source Voltage ID Drain Current (cont.) at Tc = 25 oC ID o ID M(•) P tot V ISO T stg Tj Unit IRF540FI 30 V 16 A Drain Current (cont.) at Tc = 100 C 21 11 A Drain Current (pulsed) 120 120 A Total Dissipation at Tc = 25 o C 150 45 W Derating Factor 1 0.3 W/ o C Insulation Withstand Voltage (DC) ⎯ 2000 Storage Temperature Max. Operating Junction Temperature V -65 to 175 o C 175 o C (•) Pulse width limited by safe operating area July 1993 1/9 IRF540/FI THERMAL DATA R thj-cas e Rthj- amb R th c-s Tl Thermal Resistance Junction-case TO-220 ISOWATT220 1 3.33 Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose o C/W 62.5 0.5 300 o C/W C/W o C Max Value Unit o AVALANCHE CHARACTERISTICS Symbol Parameter IA R Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by T j max, δ < 1%) 30 A E AS Single Pulse Avalanche Energy (starting T j = 25 o C, ID = I AR, VD D = 25 V) 200 mJ E AR Repetitive Avalanche Energy (pulse width limited by T j max, δ < 1%) 50 mJ IA R Avalanche Current, Repetitive or Not-Repetitive (T c = 100 o C, pulse width limited by T j max, δ < 1%) 21 A o ELECTRICAL CHARACTERISTICS (Tcase = 25 C unless otherwise specified) OFF Symbol V( BR)DSS Parameter Drain-source Breakdown Voltage Test Conditions I D = 250 μA VG S = 0 I DS S V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating x 0.8 IG SS Gate-body Leakage Current (V D S = 0) Min. Typ. Max. 100 Unit V 250 1000 μA μA ± 100 nA Max. Unit 2.9 4 V 0.045 0.077 Ω T c = 125 oC V GS = ± 20 V ON (∗) Symbol Parameter Test Conditions V G S(th) Gate Threshold Voltage V DS = V GS ID = 250 μA R DS( on) Static Drain-source On Resistance V GS = 10V ID = 17 A I D( on) On State Drain Current V DS > ID( on) x RD S(on) max Min. 2 VG S = 10 V Typ. 30 A DYNAMIC Symbol gfs (∗) C iss C oss C rss 2/9 Parameter Test Conditions Forward Transconductance V DS > ID( on) x RD S(on) max Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V f = 1 MHz ID = 17 A VG S = 0 Min. Typ. 10 18 1600 460 140 Max. Unit S 2100 600 200 pF pF pF IRF540/FI ELECTRICAL CHARACTERISTICS (continued) SWITCHING RESISTIVE LOAD Symbol Typ. Max. Unit t d(on) tr t d(off ) tf Turn-on Time Rise Time Turn-off Delay Time Fall Time Parameter V DD = 50 V ID = 5 A VG S = 10 V R i = 50 Ω (see test circuit) Test Conditions Min. 55 110 290 125 80 160 410 180 ns ns ns ns Qg Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge I D = 30 A V GS = 10 V V DD = Max Rating x 0.8 (see test circuit) 55 11 26 80 nC nC nC Typ. Max. Unit 30 120 A A SOURCE DRAIN DIODE Symbol Parameter Test Conditions IS D I SDM(•) Source-drain Current Source-drain Current (pulsed) V S D (∗) Forward On Voltage I SD = 30 A Reverse Recovery Time Reverse Recovery Charge I SD = 30 A di/dt = 100 A/μs T j = 150 o C VDD = 50 V t rr Q rr Min. VG S = 0 1.6 V 140 ns 0.7 μC (∗) Pulsed: Pulse duration = 300 μs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area for TO-220 Package Safe Operating Area for ISOWATT220 Package 3/9 IRF540/FI Thermal Impedance for TO-220 Package Thermal Impedance for ISOWATT220 Package Derating Curve for TO-220 Package Derating Curve for ISOWATT220 Package Output Characteristics Transfer Characteristics 4/9 IRF540/FI Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature 5/9 IRF540/FI Source-drain Diode Forward Characteristics Unclamped Inductive Load Test Circuit Unclamped Inductive Waveforms Switching Time Test Circuit Gate Charge Test Circuit 6/9 IRF540/FI TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 0.106 G1 2.4 2.7 0.094 H2 10.0 10.40 0.393 L2 0.409 16.4 0.645 L4 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 3.5 3.93 0.137 0.154 3.75 3.85 0.147 0.151 D1 C D A E L9 DIA. H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 7/9 IRF540/FI ISOWATT220 MECHANICAL DATA mm DIM. MIN. inch MAX. MIN. A 4.4 TYP. 4.6 0.173 TYP. 0.181 MAX. B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.4 0.7 0.015 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 L2 0.409 16 0.630 28.6 30.6 1.126 1.204 L4 9.8 10.6 0.385 0.417 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 B D A E L3 L3 L6 F F1 L7 F2 H G G1 Ø 1 2 3 L2 8/9 L4 P011G IRF540/FI Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. © 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A 9/9 SFH 309 SFH 309 FA SFH 309 SFH 309 FA feof6653 feo06653 NPN-Silizium-Fototransistor Silicon NPN Phototransistor Maße in mm, wenn nicht anders angegeben/Dimensions in mm, unless otherwise specified Wesentliche Merkmale Features ● Speziell geeignet für Anwendungen im ● Especially suitable for applications from Bereich von 380 nm bis 1180 nm (SFH 309) und bei 880 nm (SFH 309 FA) ● Hohe Linearität ● 3 mm-Plastikbauform im LED-Gehäuse ● Gruppiert lieferbar 380 nm to 1180 nm (SFH 309) and of 880 nm (SFH 309 FA) ● High linearity ● 3 mm LED plastic package ● Available in groups Anwendungen ● Lichtschranken für Gleich- und Wechsellichtbetrieb ● Industrieelektronik ● “Messen/Steuern/Regeln” Applications ● Photointerrupters ● Industrial electronics ● For control and drive circuits Semiconductor Group 1 01.97 SFH 309 SFH 309 FA Typ Type Bestellnummer Ordering Code Typ (*vorher) Type (*formerly) Bestellnummer Ordering Codes SFH 309 Q62702-P859 SFH 309 FA (*SFH 309 F) Q62702-P941 SFH 309-3 Q62702-P997 SFH 309 FA-2 (*SFH 309 F-2) Q62702-P174 SFH 309-4 Q62702-P998 SFH 309 FA-3 (*SFH 309 F-3) Q62702-P176 SFH 309-5 Q62702-P999 SFH 309 FA-4 (*SFH 309 F-4) Q62702-P178 SFH 309-61) Q62702-P1000 SFH 309 FA-5 (*SFH 309 F-51)) Q62702-P180 1) 1) Eine Lieferung in dieser Gruppe kann wegen Ausbeuteschwankungen nicht immer sichergestellt werden. Wir behalten uns in diesem Fall die Lieferung einer Ersatzgruppe vor. Supplies out of this group cannot always be guaranteed due to unforseeable spread of yield. In this case we will reserve us the right of delivering a substitute group. Grenzwerte Maximum Ratings Bezeichnung Description Symbol Symbol Wert Value Einheit Unit Betriebs- und Lagertemperatur Operating and storage temperature range Top; Tstg – 55 ... + 100 °C Löttemperatur bei Tauchlötung Lötstelle ≥ 2 mm vom Gehäuse, Lötzeit t ≤ 5 s Dip soldering temperature ≥ 2 mm distance from case bottom, soldering time t ≤ 5 s TS 260 °C Löttemperatur bei Kolbenlötung Lötstelle ≥ 2 mm vom Gehäuse, Lötzeit t ≤ 3 s Iron soldering temperature ≥ 2 mm distance from case bottom, soldering time t ≤ 3 s TS 300 °C Kollektor-Emitterspannung Collector-emitter voltage VCE 35 V Kollektorstrom Collector current IC 15 mA Kollektorspitzenstrom, τ < 10 µs Collector surge current ICS 75 mA Semiconductor Group 2 SFH 309 SFH 309 FA Grenzwerte Maximum Ratings (cont’d) Bezeichnung Description Symbol Symbol Wert Value Einheit Unit Verlustleistung, TA = 25 °C Total power dissipation Ptot 165 mW Wärmewiderstand Thermal resistance RthJA 450 K/W Kennwerte (TA = 25 °C, λ = 950 nm) Characteristics Bezeichnung Description Symbol Symbol Wert Value SFH 309 SFH 309 FA 900 Einheit Unit Wellenlänge der max. Fotoempfindlichkeit Wavelength of max. sensitivity λS max 860 Spektraler Bereich der Fotoempfindlichkeit S = 10 % von Smax Spectral range of sensitivity S = 10 % of Smax λ 380 ... 1150 730 ... 1120 nm Bestrahlungsempfindliche Fläche (∅ 240 µm) A Radiant sensitive area nm 0.2 0.2 mm2 Abmessung der Chipfläche Dimensions of chip area L×B L×W 0.45 × 0.45 0.45 × 0.45 mm × mm Abstand Chipoberfläche zu Gehäuseoberfläche Distance chip front to case surface H 2.4 ... 2.8 2.4 ... 2.8 mm Halbwinkel Half angle ϕ ± 12 ± 12 Grad deg. Kapazität, VCE = 0 V, f = 1 MHz, E = 0 Capacitance CCE 5.0 5.0 pF Dunkelstrom Dark current VCE = 25 V, E = 0 ICEO 1 (≤ 200) 1 (≤ 200) nA Semiconductor Group 3 SFH 309 SFH 309 FA Die Fototransistoren werden nach ihrer Fotoempfindlichkeit gruppiert und mit arabischen Ziffern gekennzeichnet. The phototransistors are grouped according to their spectral sensitivity and distinguished by arabian figures. Bezeichnung Description Symbol Symbol Wert Value -2 Fotostrom, λ = 950 nm Photocurrent Ee = 0.5 mW/cm2, VCE = 5 V SFH 309: Ev = 1000 Ix, Normlicht/ standard light A, VCE = 5 V IPCE IPCE -3 -4 Einheit Unit -5 0.4 ... 0.8 0.63 ... 1. 1.0 ... 2.0 1.6 ... 3.2 mA 25 1.5 4.5 7.2 mA 2.8 Anstiegszeit/Abfallzeit Rise and fall time IC = 1 mA, VCC = 5 V, RL = 1 kΩ tr, tf 5 6 7 8 µs Kollektor-EmitterSättigungsspannung Collector-emitter saturation voltage IC = IPCEmin1) × 0.3, Ee = 0.5 mW/cm2 VCEsat 200 200 200 200 mV 1) 1) IPCEmin ist der minimale Fotostrom der jeweiligen Gruppe IPCEmin is the min. photocurrent of the specified group Directional characteristics Srel = f (ϕ) Semiconductor Group 4 SFH 309 SFH 309 FA Semiconductor Group 5 SFH 309 SFH 309 FA Relative spectral sensitivity, SFH 309 Srel = f (λ) Relative spectral sensitivity, SFH 309 FA Srel = f (λ) Photocurrent IPCE = f (Ee), VCE = 5 V Total power dissipation Ptot = f (TA) Photocurrent IPCE = f (VCE), Ee = Parameter Dark current ICEO = f (VCE), E = 0 Dark current ICEO = f (TA), VCE = 25 V, E = 0 Capacitance CCE= f (VCE), f = 1 MHz, E = 0 Photocurrent IPCE/IPCE25o = f (TA), VCE = 5 V Semiconductor Group 6 P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET ZVP2106A ISSUE 2 – MARCH 94 FEATURES * 60 Volt VDS * RDS(on)=5Ω ID(On) -On-State Drain Current (Amps) ID(On) -On-State Drain Current (Amps) TYPICAL CHARACTERISTICS -3.5 VGS= -20V -18V -14V -3.0 -2.5 -12V -2.0 -10V -1.5 -9V -8V -1.0 -7V -6V -0.5 -5V -4V 0 0 -10 -20 -30 -40 -50 -2.0 -1.8 VGS= -10V -1.6 -1.4 -1.2 -9V -1.0 -8V -0.8 -7V -0.6 -6V -0.4 -5V -4V -3.5V -0.2 0 0 VDS - Drain Source Voltage (Volts) VDS-Drain Source Voltage (Volts) -8 -6 -4 ID= -1A -2 -0.5A -0.25A 0 -2 -4 -6 -8 -10 -1.0 VDS=-10V -0.8 -0.6 -0.4 PARAMETER SYMBOL VALUE UNIT Drain-Source Voltage V DS -60 V Continuous Drain Current at T amb=25°C ID -280 mA Pulsed Drain Current I DM -4 A Gate Source Voltage V GS ± 20 V Power Dissipation at T amb=25°C P tot 700 mW Operating and Storage Temperature Range T j :T stg -55 to +150 °C PARAMETER SYMBOL MIN. Drain-Source Breakdown Voltage BV DSS -60 Gate-Source Threshold Voltage V GS(th) -1.5 MAX. UNIT CONDITIONS. V I D=-1mA, V GS=0V -3.5 V ID=-1mA, V DS= V GS -0.2 0 -2 -4 -6 -8 -10 Gate-Body Leakage I GSS 20 nA V GS=± 20V, V DS=0V Zero Gate Voltage Drain Current I DSS -0.5 -100 µA µA V DS=-60 V, V GS=0 V DS=-48 V, V GS=0V, T=125°C (2) On-State Drain Current(1) I D(on) A V DS=-18 V, V GS=-10V 5 Ω V GS=-10V,I D=-500mA mS V DS=-18V,I D=-500mA -1 Static Drain-Source On-State R DS(on) Resistance (1) Forward Transconductance (1)(2) 2.6 -2.0 ID-Drain Current (Amps) On-resistance v drain current ABSOLUTE MAXIMUM RATINGS. ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated). -1.2 -7V -8V -9V -10V -1.0 2.4 2.2 n) (o DS 2.0 1.8 1.6 1.4 Dr 1.2 1.0 Gate Thresh old 0.8 0.6 eR nc ta sis e eR rc ou -S n ai VGS=-10V ID=-0.5A VGS=VDS ID=-1mA Voltage VGS (th ) -40 -20 0 20 40 60 80 100 120 140 160 180 Tj-Junction Temperature (°C) Normalised RDS(on) and VGS(th) vs Temperature 3-418 S E-Line TO92 Compatible VGS-Gate Source Voltage (Volts) 5 1 -0.1 D G -10 Transfer Characteristics Normalised RDS(on) and VGS(th) RDS(ON) -Drain Source Resistance (Ω) -6V -8 -1.4 VGS-Gate Source Voltage (Volts) VGS=-5V -6 -1.6 Voltage Saturation Characteristics 10 -4 Saturation Characteristics ID(On)-On-State Drain Current (Amps) Output Characteristics 0 -2 VDS - Drain Source Voltage (Volts) -10 ZVP2106A g fs 150 Input Capacitance (2) C iss 100 pF Common Source Output Capacitance (2) C oss 60 pF Reverse Transfer Capacitance (2) C rss 20 pF Turn-On Delay Time (2)(3) t d(on) 7 ns Rise Time (2)(3) tr 15 ns Turn-Off Delay Time (2)(3) t d(off) 12 ns Fall Time (2)(3) tf 15 ns V DS=-18V, V GS=0V, f=1MHz V DD ≈-18V, I D=-500mA (1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2% (2) Sample test. 3-417 Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator ( 3 ) P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET ZVP2106A ISSUE 2 – MARCH 94 FEATURES * 60 Volt VDS * RDS(on)=5Ω ID(On) -On-State Drain Current (Amps) ID(On) -On-State Drain Current (Amps) TYPICAL CHARACTERISTICS -3.5 VGS= -20V -18V -14V -3.0 -2.5 -12V -2.0 -10V -1.5 -9V -8V -1.0 -7V -6V -0.5 -5V -4V 0 0 -10 -20 -30 -40 -50 -2.0 -1.8 VGS= -10V -1.6 -1.4 -1.2 -9V -1.0 -8V -0.8 -7V -0.6 -6V -0.4 -5V -4V -3.5V -0.2 0 0 VDS - Drain Source Voltage (Volts) VDS-Drain Source Voltage (Volts) -8 -6 -4 ID= -1A -2 -0.5A -0.25A 0 -2 -4 -6 -8 -10 -1.0 VDS=-10V -0.8 -0.6 -0.4 PARAMETER SYMBOL VALUE UNIT Drain-Source Voltage V DS -60 V Continuous Drain Current at T amb=25°C ID -280 mA Pulsed Drain Current I DM -4 A Gate Source Voltage V GS ± 20 V Power Dissipation at T amb=25°C P tot 700 mW Operating and Storage Temperature Range T j :T stg -55 to +150 °C PARAMETER SYMBOL MIN. Drain-Source Breakdown Voltage BV DSS -60 Gate-Source Threshold Voltage V GS(th) -1.5 MAX. UNIT CONDITIONS. V I D=-1mA, V GS=0V -3.5 V ID=-1mA, V DS= V GS -0.2 0 -2 -4 -6 -8 -10 Gate-Body Leakage I GSS 20 nA V GS=± 20V, V DS=0V Zero Gate Voltage Drain Current I DSS -0.5 -100 µA µA V DS=-60 V, V GS=0 V DS=-48 V, V GS=0V, T=125°C (2) On-State Drain Current(1) I D(on) A V DS=-18 V, V GS=-10V 5 Ω V GS=-10V,I D=-500mA mS V DS=-18V,I D=-500mA -1 Static Drain-Source On-State R DS(on) Resistance (1) Forward Transconductance (1)(2) 2.6 -2.0 ID-Drain Current (Amps) On-resistance v drain current ABSOLUTE MAXIMUM RATINGS. ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated). -1.2 -7V -8V -9V -10V -1.0 2.4 2.2 n) (o DS 2.0 1.8 1.6 1.4 Dr 1.2 1.0 Gate Thresh old 0.8 0.6 eR nc ta sis e eR rc ou -S n ai VGS=-10V ID=-0.5A VGS=VDS ID=-1mA Voltage VGS (th ) -40 -20 0 20 40 60 80 100 120 140 160 180 Tj-Junction Temperature (°C) Normalised RDS(on) and VGS(th) vs Temperature 3-418 S E-Line TO92 Compatible VGS-Gate Source Voltage (Volts) 5 1 -0.1 D G -10 Transfer Characteristics Normalised RDS(on) and VGS(th) RDS(ON) -Drain Source Resistance (Ω) -6V -8 -1.4 VGS-Gate Source Voltage (Volts) VGS=-5V -6 -1.6 Voltage Saturation Characteristics 10 -4 Saturation Characteristics ID(On)-On-State Drain Current (Amps) Output Characteristics 0 -2 VDS - Drain Source Voltage (Volts) -10 ZVP2106A g fs 150 Input Capacitance (2) C iss 100 pF Common Source Output Capacitance (2) C oss 60 pF Reverse Transfer Capacitance (2) C rss 20 pF Turn-On Delay Time (2)(3) t d(on) 7 ns Rise Time (2)(3) tr 15 ns Turn-Off Delay Time (2)(3) t d(off) 12 ns Fall Time (2)(3) tf 15 ns V DS=-18V, V GS=0V, f=1MHz V DD ≈-18V, I D=-500mA (1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2% (2) Sample test. 3-417 Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator ( 3 ) ZVP2106A TYPICAL CHARACTERISTICS 300 gfs-Transconductance (mS) gfs-Transconductance (mS) 300 250 VDS=-10V 200 150 100 50 0 250 150 100 50 0 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 0 Transconductance v drain current 60 Ciss 40 Coss 20 Crss 0 -30 -40 VGS-Gate Source Voltage (Volts) C-Capacitance (pF) 80 -20 -4 -6 -8 -10 Transconductance v gate-source voltage 100 -10 -2 VGS-Gate Source Voltage (Volts) ID- Drain Current (Amps) 0 VDS=-10V 200 0 -2 -4 VDS= -20V -30V -50V -6 -8 -10 -12 -14 -16 0 -50 VDS-Drain Source Voltage (Volts) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 Q-Charge (nC) Capacitance v drain-source voltage Gate charge v gate-source voltage 3-419
