Download HT9170 DTMF Receiver

HT9170
DTMF Receiver
Features
·
·
·
·
·
Operating voltage: 2.5V~5.5V
Minimal external components
No external filter is required
Low standby current (on power down mode)
Excellent performance
·
·
·
·
Tristate data output for mC interface
3.58MHz crystal or ceramic resonator
1633Hz can be inhibited by the INH pin
HT9170B: 18-pin DIP package
HT9170D: 18-pin SOP package
General Description
DTMF tone pairs into a 4-bit code output.
The HT9170 series are Dual Tone Multi Frequency (DTMF) receivers integrated with digital decoder and bandsplit filter functions. The
H T 9 1 7 0 B a nd H T 9 1 7 0 D t y p es s u p p l y
power-down mode and inhibit mode operations.
All types of the HT9170 series use digital counting techniques to detect and decode all the 16
Highly accurate switched capacitor filters are
employed to divide tone (DTMF) signals into
low and high group signals. A built-in dial tone
rejection circuit is provided to eliminate the
need for pre-filtering.
Selection Table
Function Operating
OSC
Tristate
Power 1633Hz
Voltage Frequency Data Output Down Inhibit
Part No.
DV DVB Package
HT9170B
2.5V~5.5V
3.58MHz
Ö
Ö
Ö
Ö
¾
18 DIP
HT9170D
2.5V~5.5V
3.58MHz
Ö
Ö
Ö
Ö
¾
18 SOP
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December 20, 1999
HT9170
Block Diagram
P W D N
V R E F
B ia s
C ir c u it
V re f
G e n e ra to r
R T /G T
E S T
D V
D V B
X 2
3 .5 8 M H z
C ry s ta l
O s c illa to r
X 1
L o w
V P
G ro u p
F ilte r
F re q u e n c y
P r e - F ilte r
O P A
V N
S te e r in g C o n tr o l C ir c u it
D e te c to r
H ig h G r o u p
F ilte r
G S
C o d e
D e te c to r
L a tc h
&
O u tp u t
B u ffe r
D 0
D 1
D 2
D 3
IN H
O E
Pin Assignment
V P
1
1 8
V D D
V P
1
1 8
V D D
V N
2
1 7
R T /G T
V N
2
1 7
R T /G T
G S
3
1 6
E S T
G S
3
1 6
E S T
V R E F
4
1 5
D V
V R E F
4
1 5
D V
IN H
5
1 4
D 3
IN H
5
1 4
D 3
P W D N
6
1 3
D 2
P W D N
6
1 3
D 2
X 1
7
1 2
D 1
X 1
7
1 2
D 1
X 2
8
1 1
D 0
X 2
8
1 1
D 0
V S S
9
1 0
O E
V S S
9
1 0
O E
H T 9 1 7 0 B
1 8 D IP
H T 9 1 7 0 D
1 8 S O P
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December 20, 1999
HT9170
Pin Description
Pin Name I/O
Internal
Connection
Description
OPERATIONAL
Operational amplifier non-inverting input
AMPLIFIER
VP
I
VN
I
Operational amplifier inverting input
GS
O
Operational amplifier output terminal
VREF
O
X1
I
X2
O
PWDN
VREF
Reference voltage output, normally VDD/2
OSCILLATOR
The system oscillator consists of an inverter, a bias resistor
and the necessary load capacitor on chip.
A standard 3.579545MHz crystal connected to X1 and X2 terminals implements the oscillator function.
I
CMOS IN
Pull-low
Active high. This enables the device to go into power down
mode and inhibits the oscillator. This pin input is internally
pulled down.
INH
I
CMOS IN
Pull-low
Logic high. This inhibits the detection of tones representing
characters A, B, C and D. This pin input is internally pulled
down.
VSS
¾
¾
OE
I
CMOS IN
Pull-high
D0~D3 output enable, high active
D0~D3
O
CMOS OUT
Tristate
Receiving data output terminals
OE=²H²: Output enable
OE=²L²: High impedance
DV
O
CMOS OUT
Data valid output
When the chip receives a valid tone (DTMF) signal, the DV
goes high; otherwise it remains low.
EST
O
CMOS OUT
Early steering output (see Functional Description)
RT/GT
I/O
CMOS IN/OUT
VDD
¾
¾
DVB
O
CMOS OUT
Negative power supply
Tone acquisition time and release time can be set through
connection with external resistor and capacitor.
Positive power supply, 2.5V~5.5V for normal operation
One-shot type data valid output, normal high, when the chip
receives a valid time (DTMF) signal, the DVB goes low for
10ms.
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December 20, 1999
HT9170
Approximate internal connection circuits
O P E R A T IO N A L
A M P L IF IE R
V R E F
X 1
V O P A
V +
V N
V P
C M O S O U T
T r is ta te
X 2
E N
O P A
G S
1 0 M
2 0 p F
C M O S O U T
C M O S IN
P u ll- h ig h
O S C IL L A T O R
1 0 p F
C M O S IN
P u ll- lo w
C M O S IN /O U T
Absolute Maximum Ratings
Supply Voltage.................................-0.3V to 6V
Storage Temperature.................-50°C to 125°C
Input Voltage .................VSS-0.3V to VDD+0.3V
Operating Temperature ..............-20°C to 75°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
¾
¾
2.5
5
5.5
V
IDD
Operating Current
5V
¾
¾
3.0
7
mA
ISTB
Standby Current
5V
PWDN=5V
¾
10
25
mA
VIL
²Low² Input Voltage
5V
¾
¾
¾
1.0
V
VIH
²High² Input Voltage
5V
¾
4.0
¾
¾
V
IIL
²Low² Input Current
5V
VVP=VVN=0V
¾
¾
0.1
mA
IIH
²High² Input Current
5V
VVP=VVN=5V
¾
¾
0.1
mA
ROE
Pull-high Resistance (OE)
5V
VOE=0V
60
100
150
kW
RIN
Input Impedance (VN, VP)
5V
¾
10
¾
MW
¾
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December 20, 1999
HT9170
Symbol
Parameter
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
IOH
Source Current
(D0~D3, EST, DV)
5V
VOUT=4.5V
-0.4
-0.8
¾
mA
IOL
Sink Current
(D0~D3, EST, DV)
5V
VOUT=0.5V
1.0
2.5
¾
mA
fOSC
System Frequency
5V
Crystal=3.5795MHz 3.5759 3.5795 3.5831
A.C. Characteristics
Symbol
Parameter
MHz
fOSC=3.5795MHz, Ta=25°C
Test Conditions
Conditions
VDD
Min. Typ. Max. Unit
DTMF Signal
3V
-36
¾
-6
5V
-29
¾
1
Twist Accept Limit (Positive)
5V
¾
10
¾
dB
Twist Accept Limit (Negative)
5V
¾
10
¾
dB
Dial Tone Tolerance
5V
¾
18
¾
dB
Noise Tolerance
5V
¾
-12
¾
dB
Third Tone Tolerance
5V
¾
-16
¾
dB
Frequency Deviation
Acceptance
5V
¾
¾
±1.5
%
Frequency Deviation Rejection
5V
±3.5
¾
¾
%
Power Up Time (tPU)
(See Figure 4.)
5V
¾
30
¾
ms
Input Signal Level
dBm
Gain Setting Amplifier
RIN
Input Resistance
5V
¾
¾
10
¾
MW
IIN
Input Leakage Current
5V
VSS<(VVP,VVN)<VDD
¾
0.1
¾
mA
VOS
Offset Voltage
5V
¾
¾
±25
¾
mV
PSRR
Power Supply Rejection
5V
¾
60
¾
dB
CMRR
Common Mode Rejection
5V
¾
60
¾
dB
AVO
Open Loop Gain
5V
¾
65
¾
dB
fT
Gain Band Width
5V
¾
1.5
¾
MHz
VOUT
Output Voltage Swing
5V
¾
4.5
¾
VPP
100 Hz
-3V<VIN<3V
¾
RL>100kW
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December 20, 1999
HT9170
Symbol
Test Conditions
Parameter
VDD
Conditions
Min. Typ. Max. Unit
RL
Load Resistance (GS)
5V
¾
¾
50
¾
kW
CL
Load Capacitance (GS)
5V
¾
¾
100
¾
pF
VCM
Common Mode Range
5V
¾
3.0
¾
VPP
No load
Steering Control
tDP
Tone Present Detection Time
5
16
22
ms
tDA
Tone Absent Detection Time
¾
4
8.5
ms
tACC
Acceptable Tone Duration
¾
¾
42
ms
tREJ
Rejected Tone Duration
20
¾
¾
ms
tIA
Acceptable Inter-digit Pause
¾
¾
42
ms
tIR
Rejected Inter-digit Pause
20
¾
¾
ms
tPDO
Propagation Delay
(RT/GT to DO)
¾
8
11
ms
tPDV
Propagation Delay
(RT/GT to DV)
¾
12
¾
ms
tDOV
Output Data Set Up (DO to DV)
¾
4.5
¾
ms
tDDO
Disable Delay (OE to DO)
¾
300
¾
ns
tEDO
Enable Delay (OE to DO)
¾
50
60
ns
Note: DO=D0~D3
V
1
1 0 0 k W
T o n e
0 .1 m F
2
3
4
1 0 0 k W
5
6
3 .5 7 9 5 4 5 M H z
8
7
2 0 p F
2 0 p F
V S S
9
V P
V D D
V N
R T /G T
G S
E S T
V R E F
D V
(IN H )
D 3
(P W D N )
D 2
X 1
D 1
X 2
D 0
V S S
O E
1 8
D D
0 .1 m F
1 7
1 6
1 5
3 0 0 k W
1 4
1 3
1 2
1 1
1 0
H T 9 1 7 0 /B /D
Figure 1. Test circuit
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December 20, 1999
HT9170
Functional Description
Overview
Steering control circuit
The HT9170 series tone decoders consist of
three band pass filters and two digital decode
circuits to convert a tone (DTMF) signal into
digital code output.
The steering control circuit is used for measuring the effective signal duration and for protecting against drop out of valid signals. It employs
the analog delay by external RC time-constant
controlled by EST.
An operational amplifier is built-in to adjust
the input signal (refer to Figure 2).
C
V
V P
R 1
i
The timing is shown in Figure 3. The EST pin is
normally low and draws the RT/GT pin to keep
low through discharge of external RC. When a
valid tone input is detected, EST goes high to
charge RT/GT through RC.
V N
R F
When the voltage of RT/GT changes from 0 to
VTRT (2.35V for 5V supply), the input signal is
effective, and the correct code will be created by
the code detector. After D0~D3 are completely
latched, DV output becomes high. When the
voltage of RT/GT falls down from VDD to VTRT
(i.e.., when there is no input tone), DV output
becomes low, and D0~D3 keeps data until a
next valid tone input is produced.
H T 9 1 7 0
S e r ie s
G S
V R E F
( a ) S ta n d a r d in p u t c ir c u it
C
V
i1
V
i2
R 1
V P
V N
C
By selecting adequate external RC value, the minimum acceptable input tone duration (tACC) and
the minimum acceptable inter-tone rejection (tIR)
can be set. External components (R, C) are chosen
by the formula (refer to Figure 5.):
R 2
R 3
R 4
R 5
G S
H T 9 1 7 0
S e r ie s
V R E F
tACC=tDP+tGTP;
( b ) D iffe r e n tia l in p u t c ir c u it
tIR=tDA+tGTA;
Figure 2. Input operation for amplifier application circuits
where tACC: Tone duration acceptable time
tDP: EST output delay time (²L²®²H²)
The pre-filter is a band rejection filter which reduces the dialing tone from 350Hz to 400Hz.
tGTP: Tone present time
The low group filter filters low group frequency
signal output whereas the high group filter filters high group frequency signal output.
tDA: EST output delay time (²H²®²L²)
tIR: Inter-digit pause rejection time
tGTA: Tone absent time
Each filter output is followed by a zero-crossing
detector with hysteresis. When each signal amplitude at the output exceeds the specified
level, it is transferred to full swing logic signal.
When input signals are recognized to be effective, DV becomes high, and the correct tone
code (DTMF) digit is transferred.
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December 20, 1999
HT9170
Timing Diagrams
tR
E J
t IR
t IA
T o n e n
T o n e
tD
P
tD
T o n e n + 1
tD
P
tD
A
P
E S T
tA
R T /G T
V
C C
T R T
tG
tP
D 0 ~ D 3
T o n e C o d e n
1
tG
T A
T o n e C o d e n + 1
T o n e C o d e n
tD
tP
T P
D O
O V
tP
D V
D V
D V
tD
D O
tE
D O
O E
Figure 3. Steering timing
T o n e
T o n e
P W D N
E S T
tP
U
Figure 4. Power up timing
8
December 20, 1999
HT9170
V
V
D D
V D D
H T 9 1 7 0
S e r ie s
H T 9 1 7 0
S e r ie s
C
R T /G T
V D D
C
R T /G T
R
E S T
R 1
E S T
D 1
(a) Fundamental circuit:
tGTP = R ´ C ´ Ln (VDD / (VDD - VTRT))
tGTA = R ´ C ´ Ln (VDD / VTRT)
V
D D
R 2
(c) tGTP > tGTA :
tGTP = R1 ´ C ´ Ln (VDD / (VDD - VTRT))
tGTA = (R1 // R2) ´ C ´ Ln (VDD / VTRT)
D D
V D D
H T 9 1 7 0
S e r ie s
C
R T /G T
R 1
E S T
D 1
R 2
(b) tGTP < tGTA :
tGTP = (R1 // R2) ´ C ´ Ln (VDD - VTRT))
tGTA = R1 ´ C ´ Ln (VDD / VTRT)
Figure 5. Steering time adjustment circuits
DTMF dialing matrix
C O L 1 C O L 2
C O L 3
C O L 4
R O W 1
1
2
3
A
R O W 2
4
5
6
B
R O W 3
7
8
9
C
0
#
D
R O W 4
*
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December 20, 1999
HT9170
DTMF data output table
Low Group (Hz)
High Group (Hz)
Digit
OE
D3
D2
D1
D0
697
1209
1
H
L
L
L
H
697
1336
2
H
L
L
H
L
697
1477
3
H
L
L
H
H
770
1209
4
H
L
H
L
L
770
1336
5
H
L
H
L
H
770
1477
6
H
L
H
H
L
852
1209
7
H
L
H
H
H
852
1336
8
H
H
L
L
L
852
1477
9
H
H
L
L
H
941
1336
0
H
H
L
H
L
941
1209
*
H
H
L
H
H
941
1477
#
H
H
H
L
L
697
1633
A
H
H
H
L
H
770
1633
B
H
H
H
H
L
852
1633
C
H
H
H
H
H
941
1633
D
H
L
L
L
L
¾
¾
ANY
L
Z
Z
Z
Z
Z: High impedance
Data output
The data outputs (D0~D3) are tristate outputs. When OE input becomes low, the data outputs
(D0~D3) are high impedance.
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December 20, 1999
HT9170
Application Circuits
V
1
1 0 0 k W
D T M F
2
3
0 .1 m F
4
1 0 0 k W
5
6
T o o th e r d e v ic e
7
8
X 'T A L
9
C 1
C 2
V S S
V P
V D D
V N
R T /G T
G S
E S T
V R E F
D V
IN H
D 3
P W D N
D 2
X 1
D 1
X 2
D 0
V S S
O E
1 8
D D
0 .1 m F
1 7
1 6
1 5
3 0 0 k W
1 4
1 3
1 2
T o o th e r d e v ic e
1 1
1 0
H T 9 1 7 0 B /D
1 8 D IP /S O P
N o t e : ( a ) X 'T A L = 3 . 5 7 9 5 4 5 M H z c r y s t a l
C 1 = C 2 @ 2 0 p F
( b ) X 'T A L = 3 . 5 8 M H z c e r a m ic r e s o n a t o r
C 1 = C 2 @ 3 9 p F
11
December 20, 1999
HT9170
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Copyright Ó 1999 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
12
December 20, 1999
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