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LOW VOLTAGE TEMPERATURE SENSOR DESIGN FOR ON-CHIP THERMAL
MANAGEMENT
by
Li Lu, B.S.E.E, M.S.E.E
A Dissertation
In
ELECTRICAL AND COMPUTER ENGINEERING
Submitted to the Graduate Faculty
of Texas Tech University in
Partial Fulfillment of
the Requirements for
the Degree of
DOCTOR OF PHILOSOPHY
Approved
Dr. Changzhi Li
Chairperson of Committee
Dr. Sunanda Mitra
Dr. Stephen Bayne
Dr. Mohammad Saed
Dr. Yuanlin Zhang
Dominick Casadonte
Interim Dean of the Graduate School
May, 2013
Copyright 2013, Li Lu
Texas Tech University, Li Lu, May 2013
ACKNOWLEDGEMENTS
I would like to thank all the people who have been helping me during the past
four years. First and foremost, my utmost gratitude is due to my adviser, Dr. Changzhi
Li, who has been supporting and encouraging me since the summer of 2009 when I
first landed in this country. Dr. Li has been not only a good academic adviser, but also
a mentor who cares my daily life. This dissertation would never have been possible
without Dr. Li’s detailed and patient guidance. I also thank Dr. Sunanda Mitra, Dr.
Stephen Bayne and Dr. Mohammad Saed for spending their precious time to serve as
my dissertation committee, and Dr. Yuanlin Zhang for serving as the graduate school
Dean’s representative on my doctoral dissertation defense.
I thank the labmates in Dr. Li’s lab who have been helping on my research and
sharing happiness: Scott Block, Changzhan Gu, Lola Li, Yihong Yang, Bozorgmehr
Vosooghi, Guochao Wang, Satyabh Mishra, Devashish Deshpande, etc.
I also owe thanks to the colleagues in Qualcomm Technology, Inc., where I
spent 3 month valuable time on a Mixed-signal internship. Special thanks to Dr. Liang
Dai, who was my mentor during the internship and offered very detailed guidance on
the high precision on-chip temperature sensor designs. I also would like to thank the
professors who provided me very useful suggestion on the temperature sensor designs
and paper writings: Dr. Michiel A.P. Pertijs from Delft University of Technology, Dr.
Jinghong Chen from Southern Methodist University, Dr. David E. Duarte from Intel
Coroperation and Dr. Jenshan Lin from University of Florida.
Finally, I’m very grateful to my parents and big brother for their supporting
and encouraging, and my girlfirend Ms. Jing Zhao for her love and understanding.
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Texas Tech University, Li Lu, May 2013
TABLE OF CONTENTS
ACKNOWLEDGMENTS ............................................................................................. ii
ABSTRACT ............................................................................................................... v
LIST OF TABLES ..................................................................................................... vi
LIST OF FIGURES .................................................................................................. vii
CHAPTER I MOTIVATION AND BACKGROUNDS .................................................... 1
1.1. Pulse-todigital-based temperature sensor ..................................................... 2
1.2. Oscillator-based temperature sensor ............................................................ 4
1.3. Thermal-diffusivity-based temperature sensor ............................................ 4
1.4. Bandgap-based temperature sensor .............................................................. 6
1.4.1. Sigma-delta ADC ............................................................................................. 8
1.4.2. Pulse-to-digital converter ................................................................................. 9
1.4.3. Thresholding-based converter ....................................................................... 11
CHAPTER II BANDGAP-BASED TEMPERATURE SENSOR FRONT-ENDS .............. 14
2.1. Operation principle of bandgap circuits ..................................................... 14
2.2. Bandgap-based temperature sensor front-ends .......................................... 17
CHAPTER III THE PROPOSED LOW-VOLTAGE TEMPERATURE SENSORS ......... 20
3.1. Theory behind using subthreshold MOSFETs as sensing device .............. 22
3.2. A low voltage temperature sensor front-end based on an error corrected current
mirror structure.................................................................................................. 24
3.3. A low voltage temperature sensor front-end based on an regulated current
mirror structure.................................................................................................. 25
3.4. Error sources and error correction techniques for the low-voltage temperature
sensor front-ends ............................................................................................... 26
3.4.1. Dynamic element matching and dynamic offset cancellation ........................ 28
3.4.2. Gain boosting for the bulk-driven error correction amplifier ........................... 30
3.4.3. Clock boosting ................................................................................................ 31
3.5. Introduction to the sigma-delta modulator ................................................. 32
CHAPTER IV DETAILED PROTOTYPE DESIGNS .................................................. 37
4.1. A subthreshold MOSFET-based subbandgap reference voltage generator 37
4.1.1. Operation principles and circuit design .......................................................... 37
4.1.2. Experimental results ....................................................................................... 39
4.1.3. Conclusion ..................................................................................................... 40
4.2. A subthreshold MOSFETs-based subbandgap reference generator with a gain
boosted error correction amplifier ..................................................................... 41
4.2.1. Operation principles and design details ......................................................... 41
4.2.2. Experimental results ....................................................................................... 45
4.2.3. Conclusion ..................................................................................................... 48
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Texas Tech University, Li Lu, May 2013
4.3. A subthreshold MOSFETs-based PTAT voltage generator with mismatch error
correction techniques ........................................................................................ 48
4.3.1. Theory and design details .............................................................................. 48
4.3.2. Simulation and experimental results .............................................................. 50
4.3.3. Conclusion ..................................................................................................... 53
4.4. An all-CMOS low voltage scattered thermal monitoring front-end .......... 53
4.4.1. Circuit design details ...................................................................................... 53
4.4.2. Experimental results ....................................................................................... 54
4.4.3. Conclusion ..................................................................................................... 57
4.5. A subthreshold MOSFETs-based scattered relative temperature sensor frontend with a non-calibrated ±2.5 C 3σ relative inaccuracy from -40 C to 100 C 57
4.5.1. Theory and design details .............................................................................. 57
4.5.2. Error sources analysis .................................................................................... 59
4.5.3. Experimental results ....................................................................................... 60
4.5.4. Conclusion ..................................................................................................... 65
4.6. A 0.45 V MOSFETs-based temperature sensor front-end in 90nm CMOS with
a non-calibrated ±3.5 C 3σ relative inaccuracy from -55 C to 105 C ............... 66
4.6.1. Theory ........................................................................................................... 66
4.6.2. Circuit design details ...................................................................................... 67
4.6.3. Error sources analysis.................................................................................... 70
4.6.4. Experimental results ....................................................................................... 71
4.6.5. Conclusion ..................................................................................................... 76
CHAPTER V CONCLUSION AND FUTURE WORKS ................................... 77
BIBLIOGRAPHY ..................................................................................................... 79
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Texas Tech University, Li Lu, May 2013
ABSTRACT
As the integration density and power density of modern very-large-scaleintegrated (VLSI) circuits keep increasing, on-chip overheating issue is causing
performance degrading and even function failures. Thermal management system is
therefore integrated on-chip, where a temperature sensor is the most important
function block. As the process technologies keep shrinking down and the demands for
battery operation increase, low voltage operation has been an important design
criterion. Temperature sensors with low and process scalable supply voltages are
proposed in this dissertation. Specifically, subthrehsold MOSFET diodes are used as
sensing devices. Compared with traditional bipolar junction transistor (BJT) diodes,
MOSFETs working in subthreshold region exhibit similar temperature characteristics
but need lower and process scalable supply voltage. Other blocks in the sensor such as
the error correction amplifier, ADC, etc, have been re-designed to support low voltage
operation. Device mismatches in the sensing diodes, the current mirrors, the error
correction amplifier, etc, result in large error in the measured temperature, which leads
to worse accuracy performance than the BJT-based temperature sensor. Various error
correction techniques have been studied and implemented in the dissertation in order
to minimize the mismatch induced error and improve the sensing accuracy.
Furthermore, scattered temperature sensors with multiple remote sensor nodes
distributed across the chip are proposed for modern multi-core digital processer, where
multiple hot spots need thermal monitoring simultaneously. Relative inaccuracy has
been evaluated and optimized in the scattered temperature sensor which is necessary
to improve the performance of the processer through load balancing. Several prototype
designs have been taped out in different process technologies and the experimental
results demonstrate the low voltage operation as well as the improved sensing
accuracy.
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Texas Tech University, Li Lu, May 2013
LIST OF TABLES
1.1
Performance comparison of the state-of-the-art on-chip
temperature sensor solutions. ......................................................................... 8
1.2
State-of-the-art performance of the bandgap-based
individual temperature sensors ..................................................................... 19
4.1
Performance summary of the front-end ....................................................... 58
4.2
Performance summary of the proposed scattered relative
temperature sensor front-end in AMI 0.5μm process .................................. 65
4.3
Performance summary of the proposed scattered relative
temperature sensor front-end in IBM 90nm process .................................... 76
4.4
Temperature reading of each sensor node .................................................... 78
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Texas Tech University, Li Lu, May 2013
LIST OF FIGURES
1.1
The AMD quad-core OpteronTM process has 8 remote
temperature sensors in each core.................................................................... 2
1.2
Simplified block diagram of a time-to-digital-based
temperature sensor. ........................................................................................ 3
1.3
Simplified block diagram of an oscillator-based
temperature sensor. ........................................................................................ 4
1.4
(a) Schematic layout of an ETF (b) Photograph of the ETF .......................... 5
1.5
A simplified block diagram of a bandgap-based
temperature sensor with a 1st order sigma-delta ADC ................................... 7
1.6
A z-domain block diagram of a 1st order sigma-delta
modulator ....................................................................................................... 9
1.7
A schematic of a pulse-to-digital converter ................................................. 11
1.8
(a) A simple thresholding-based converter. (b) The
comparison between the PTAT voltage and the preselected reference voltages ........................................................................... 12
2.1
Block diagram of a typical bandgap-based temperature
sensor ........................................................................................................... 14
2.2
(a) A bandgap reference circuit (b) The reference voltage
is obtained by combining the PTAT and CTAT signals .............................. 15
2.3
A simplified bandgap-based temperature sensor front-end. ........................ 19
3.1
The 2011 international technology roadmap for
semiconductors (a) the scaling roadmap for transistor gate
length (b) the scaling roadmap for the supply voltages of
different types of devices: high performance (HP), low
operating power (LOP), low standby power (LSTP) and
III-V family semiconductor/Germanium devices (IIIV/Ge) ............................................................................................................ 22
3.2
A low voltage bandgap circuit with subthreshold
MOSFET diodes .......................................................................................... 23
3.3
Using MOSFETs as sensing devices ........................................................... 24
3.4
A subthreshold MOSFET-based bandgap core with a
bulk-driven semi-folded-cascode error correction
amplifier ....................................................................................................... 26
3.5
A simplified schematic of a temperature sensor front-end
in a regulated current mirror structure ......................................................... 27
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Texas Tech University, Li Lu, May 2013
3.6
PTAT signal generator with device mismatches .......................................... 28
3.7
(a) The operation principle of dynamic element matching
(b) The output of the design with DEM compared with the
ideal output value without any mismatch..................................................... 30
3.8
The operation principle of the dynamic offset cancellation ........................ 31
3.9
A simplified schematic of the reference signal generator
along with the proposed gate-bulk-driven error correction
amplifier ....................................................................................................... 32
3.10
(a) A simplified clock boosting circuit (b) The simulation
results of the clock boosting in AMI 0.5μm CMOS
process .......................................................................................................... 33
3.11
(a) Block diagram of a second order sigma-delta
modulator (b) Linear z-domain model of the modulator ............................. 34
3.12
Noise shaping of the 2nd order sigma-delta modulator ............................... 35
3.13
(a) Simplified realization of the transfer of a first order
sigma-delta modulator (b) Timing of the modulator.................................... 36
4.1
Schematic of the MOSFETs-based subbandgap reference
circuit with a semi-folded-cascode bulk-driven amplifier ........................... 40
4.2
Photomicrograph of the subbandgap reference circuit ................................ 41
4.3
Measured minimum supply voltage and line sensitivity at
room temperature in AMI 0.5 μm CMOS process ....................................... 42
4.4
Measured minimum supply voltage and line sensitivity at
room temperature in UMC 130nm CMOS process ..................................... 42
4.5
Schematic of the reference voltage generator with the
proposed gate-bulk-driven gain-boosted error correction
amplifier ....................................................................................................... 44
4.6
Simulated loop gains of a semi-folded-cascode bulkdriven amplifier and the proposed gate-bulk-driven
realization ..................................................................................................... 45
4.7
Simulated loop gain, minimum supply voltage, relative
STD of the output spread and the supply sensitivity of the
subbandgap reference as a function of the scaling factor r .......................... 45
4.8
The simulated I-V curves of the two diode branches in the
reference core (I) w/o the parallel resistors R1, R1′ R2 and
R2′, and (II) w/ the parallel resistors R1, R1′ R2 and R2′.
The adopted startup circuit is presented on the right hand
side ............................................................................................................... 46
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Texas Tech University, Li Lu, May 2013
4.9
Chip microphotograph and test setup........................................................... 47
4.10
Measured reference output spreads at room temperature
from 18 samples ........................................................................................... 48
4.11
Measured line sensitivities at room temperature .......................................... 48
4.12
Measured line sensitivities with r = 12% (a) and
temperature sensitivities with 1.15 V supply voltage (b) ............................. 49
4.13
Block diagram of the individual PTAT generator........................................ 51
4.14
The clock boosting circuit used in this design and
simulation result ........................................................................................... 52
4.15
Simulated PTAT voltage when various mismatches (MS)
exist. The corresponding average output (Av) level is
marked in the legend .................................................................................... 53
4.16
Chip microphotograph and test setup........................................................... 53
4.17
(a) Measured PTAT voltage generator output at different
temperatures. (b) The averaged PTAT voltage along with
outputs of different mismatch status as a function of
temperature................................................................................................... 54
4.18
Schematic of the scattered thermal monitor ................................................. 55
4.19
Chip microphotograph and test setup........................................................... 56
4.20
(a) Measured PTAT voltage generator output at different
temperatures. (b) The averaged PTAT voltages vs.
temperature................................................................................................... 57
4.21
Thermal monitoring behavior with uneven temperature
changes ......................................................................................................... 59
4.22
Block diagram of the proposed relative temperature sensor
front-end ....................................................................................................... 60
4.23
Clock signals for DEM1, DOC and DEM2 ................................................. 61
4.24
Chip photograph and test setup. The red dots represent the
hot spots realized by heating resistors for testing purpose ........................... 63
4.25
Measured line sensitivities at different temperatures ................................... 64
4.26
Measured PTAT outputs vs. chamber temperature for the
twenty-five sensor nodes. The PTAT outputs have been
low-pass filtered ........................................................................................... 64
4.27
Measured relative inaccuracy among the 25 sensor nodes .......................... 65
4.28
Thermal maps of the chip during the heating experiments.
(a)~ (c): The center heating resistor was powered on.
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Texas Tech University, Li Lu, May 2013
Relative error information at -40 0C, 20 0C and 100 0C
were used to compensate the thermal map in (a), (b) and
(c) respectively. (d): The upper right heating resistor was
powered on ................................................................................................... 65
4.29
Simplified schematics of a PTAT voltage/current
generator based on a regulated current mirror structure .............................. 69
4.30
Block diagram of the proposed relative temperature sensor
front-end ....................................................................................................... 70
4.31
Simulated line sensitivities of three different versions of
designs .......................................................................................................... 71
4.32
Clock signals for DEM1 and DEM2. The usage of clock
signal for the error correction chopping as in [35] has been
avoided in this design ................................................................................... 72
4.33
Chip photograph and the chamber testing setup .......................................... 74
4.34
Measured line sensitivities at different temperatures with
sensor node #6 enabled ................................................................................ 75
4.35
(a) Measured relative inaccuracy among 27 sensor nodes
from 3 chips. (b) Relative inaccuracy after one-point
digital trimming at 25 0C .............................................................................. 76
4.35
Thermal maps of the chip during the heating experiments
when the soldering iron is (a) 300 0F, (b) 350 0F and (c)
400 0F ........................................................................................................... 78
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Texas Tech University, Li Lu, May 2013
CHAPTER I
MOTIVATION AND BACKGROUNDS
Temperature sensors have been widely used in instrumentation, measurement and
control systems. Conventional temperature sensors such as platinum resistive ones have
the advantage of high accuracy. However, they are usually bulky and expensive.
Temperature sensors are made on semiconductors using modern CMOS technologies in
order to reduce the cost. Besides, on-chip temperature sensors are much easier to
interface with other control units compared with the conventional ones. As the integration
density and power density of modern very-large-scale-integrated (VLSI) circuits keep
increasing, thermal issue has been limiting the circuit performance or even causing
function failures. Therefore, on-chip temperature sensors become desirable for on-chip
thermal and power management. For example, the temperature sensor integrated on a
CPU can provide temperature information of the chip and the CPU can take appropriate
actions such as clock throttling once overheat is detected to improve the performance and
protect the chip. On the other hand, As the CMOS process technologies keep shrinking
down and the demand for battery operation increases, low supply voltage has been more
and more desired. The low supply voltage is also desired for low power consumption,
which is also a key design target for modern circuit designers.
As the multi-core era arrives, multi-location hot-spots temperature monitoring is
necessary to limit leakage and improve computational capabilities through load balancing
[1]. Fig. 1.1 shows an example of AMD quad-core OpteronTM process with 8 remote
sensors distributed in each core. Compared with the absolute sensing accuracy (inter-chip
accuracy), the relative sensing accuracy (intra-chip accuracy) may be more important [1].
Therefore, relative temperature sensors with distributed sensor nodes become an attracted
solution. Instead of using multiple individual temperature sensors for multi-core digital
processer thermal monitoring, a scattered temperature system with only the sensing
elements distributed remotely and other function blocks shared can be adopt for power
and chip area efficiency. Compared with individual temperature sensors, more error
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Texas Tech University, Li Lu, May 2013
sources exist in the scattered temperature sensors which can degrade the sensing
accuracy. Therefore, system level as well as circuit level optimization have to be
performed for the scattered temperature sensors.
HT
pll
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H
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L3
CORE
L2
pll
L2
CORE
pll
FIFO
FIFO
NORTHBRIDGE
FIFO
pll
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H
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pll
L3
CORE
L2
pll
HT
L2
CORE
pll
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Remote sensor
Thermal evaluation (TCEN) circuit
Thermal control (TCON) circuit
Fig. 1.1. The AMD quad-core OpteronTM process with remote temperature sensors in
each core.
Usually an on-chip temperature sensor includes two parts: a sensor front-end
which generates temperature dependent signals and a signal-to-digital converter which
converts the temperature dependent signals into digital readings. The temperature
dependent signals can be voltage, current, time, frequency, etc, depending on specific
approaches, and, the signal-to-digital converter can be correspondingly different. We
summarize several types of on-chip temperature sensors and review the advantages and
disadvantages of each approach. Since the scattered temperature sensors have been barely
reported, the reviewed temperature sensors here are individual sensors.
1.1.
Pulse-to-digital-based temperature sensor
A simple idea of temperature representing is the common sense that the
propagating delay of digital logic gates is temperature dependent. Researchers in [2]
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Texas Tech University, Li Lu, May 2013
proposed a temperature-to-pulse generator, which is a special inverter, to generate a
temperature dependent (proportional-to-absolute-temperature or PTAT) pulse width.
Detailed analysis on the PTAT pulse width generation was provided. The output pulse is
then fed to the input of a cyclic time-to-digital (TDC) to generate the corresponding digital
output. Fig. 1.2 shows the simplified block diagram of the system. Two important
features of the PTAT signal that can decide the accuracy performance of the temperature
sensor are spread due to process variation/device mismatch and the linearity of the PTAT
signal. The authors of [2, 3] obtained a PTAT pulse width with decent linearity but large
spread, which results in a sensor needing no curvature correction but requiring 2-point
calibration. The state-of-the-art of the pulse-to-digital-based temperature sensor [3]
achieved an accuracy of ±0.5 °C after 2-point individual calibration.
Temp. Dependent
Delay Line
A
START
Td1
Pout
Counter
START
Reference
Delay Line
B
W=Td1-Td2
Td2
W
Pout
Fig. 1.2. Simplified block diagram of a time-to-digital-based temperature sensor. From
[2].
Compared with other approaches, which usually have analog circuits for the
sensor front-ends, the pulse-to-digital-based designs adopts pure digital circuit for
temperature dependent signal generating. The implementation can be simpler and the
occupied area can be smaller than other approaches using complicated analog circuitry.
However, the disadvantages of this approach may be high cost calibration since the
spread of digital circuitry can be large. Besides, the supply sensitivity is not expected to
be good considering the adopted simple logic gate is sensitive to supply fluctuation.
Furthermore, the TDC was simple counters and the clock frequency variation can
contribute to the sensing error.
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Texas Tech University, Li Lu, May 2013
1.2.
Oscillator-based temperature sensor
This approach utilizes that fact that the oscillation frequency of an oscillator
(usually ring oscillator) can be strongly dependent on environmental temperature. In [4] ,
the authors implemented a ring oscillator, whose oscillation frequency is a positive
function of temperature. The oscillator output is buffered and square wave is generated.
The clock edges of the oscillator are then counted by a 10 bit digital counter. Fig. 1.3
shows a simplified diagram of the sensor proposed in [4].
Control Bits
DIV 2
DIV 4
MUX
DIV 8
Freq. Div.
External
Clock
Counter
Fig. 1.3. Simplified block diagram of an oscillator-based temperature sensor. From [4].
The major advantage of this approach is that the supply voltage can be very low.
0.3 V supply voltage was achieved in [4]. However, the oscillator-based temperature
sensors are limited by a number of drawbacks which are not easy to overcome. First of
all, the oscillation frequency is strongly dependent on supply voltage as well as process
variation/device mismatch, which result in poor supply sensitivity and accuracy.
Secondly, the clock powering the counter also introduces errors since the clock frequency
can vary from chip to chip. Thirdly, the oscillation frequency may not be linear with
temperature as in [4], which may require further curvature correction techniques.
1.3.
Thermal-diffusivity-based temperature sensor
Since the generated temperature-dependent signals are usually also a function of
process variation and device mismatch, 1-point or even 2-point calibration is usually
needed to improve the sensing accuracy. Therefore, sensor front-ends with small process
spread are always desired. A new method of generating temperature dependent signals is
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Texas Tech University, Li Lu, May 2013
based on the thermal diffusivity of the IC substrate. Researchers in [5] have built
temperature sensors utilizing the fact that the AC thermal characteristics of silicon are
determined by its thermal diffusivity, which can be determined by measuring the phase
response of an electrothermal filter (ETF). Fig. 1.4 (a) shows a schematic layout of an
ETF, which consists of a heater and thermopile. AC heating diffusing from the heater
creates thermal fluctuations at the thermopile, which are low-pass filtered by substrate’s
thermal inertia. The phase shift of the thermopile’s output is converted to digital reading
by a phase-domain sigma-delta modulator.
(a)
(b)
Phase-domain
ƩΔ modulator
VETF
thermopile
Heater
S
n-well
Fig. 1.4. (a) Schematic layout of an ETF (b) Photograph of the ETF (from [5])
The advantage of the thermal diffusivity-based temperature sensor is that the
thermal diffusivity of lightly doped silicon is insensitive to process variation, which could
potentially provide high sensing accuracy without trimming. ± 0.2 0C inaccuracy (3σ)
without trimming over military temperature range (-55 0C- 125 0C) was achieved in[5].
This is better than or comparable with the state-of-the-art sensing accuracy of
temperature sensors in any reported architecture. However, one of the disadvantages of
this approach is that the occupied area of the sensor front-end (the ETF) can be large (160
μm × 140 μm in [6]) as shown in Fig. 1.4 (b). This is OK for the individual on-chip
temperature sensor where the sensor chip is used to monitor the temperature of its
attachment, but may be a problem for temperature sensor system which is used for onchip thermal monitoring, since the location under monitoring may have large thermal
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Texas Tech University, Li Lu, May 2013
gradient and the large sensor front-end may result in large reading errors. Another
disadvantage of this approach is that it may be sensitive to self-heating and thermal noise
[7] The ETF is powered by an AC heating source whose power consumption can be in
the scale of miliwatt in order to achieve enough SNR [5]. This power may heat up the
substrate at the ETF area thus change the real temperature under monitoring.
Furthermore, the thermal diffusivity is measured by detecting a phase shift of AC heat
propagating. The thermal noise in the ETF area can reduce the signal-to-noise ratio and
reduce the sensing accuracy. Given that the location under monitoring can have a noisy
substrate due to digital circuit implementation, the thermal noise in that area can degrade
the temperature sensor performance.
1.4.
Bandgap based temperature sensor
Perhaps the most popular on-chip temperature sensor is the bandgap-based one. In
a bandgap-based temperature sensor, the sensor front-end generates a proportional-toabsolute-temperature (PTAT) voltage/current and a reference voltage/current. The PTAT
signal is then digitized by a following ADC against the reference signal to generate a
digital reading which is proportional to temperature. The theory behind the PTAT and
reference signal generating will be given in detail in the next section. To provide a basic
idea, Fig. 1.5 shows a simplified bandgap-based temperature sensor. Briefly speaking,
two currents in a ratio are driven into two identical BJT diodes, the difference of the two
base-to-emitter voltage, ΔVBE, is a PTAT voltage, which is in high linearity and
insensitive to process spread. Either of the two VBE is complementary-to-absolutetemperature (CTAT), which can be used to combine with the PTAT signal to generate a
reference signal. The reference voltage is referred as “Bandgap reference”, which is about
1.25V, or “Subbandgap reference”, which is scaled version of a “Bandgap reference”.
However, the CTAT voltage and thus the reference voltage are dependent on process
spread, which results in error in the sensed temperature. Therefore, one-point or twopoint calibration is needed to minimize the process spread induced error.
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Texas Tech University, Li Lu, May 2013
M3
1st order ΣΔ modulator
M4
I1
I2
R3
Q1
 A
VREF
_VBE

a
VIN
Q2
 N  A
VX

Vint
bs
clk
Fig. 1.5. A simplified block diagram of a bandgap-based temperature sensor with a 1st
order sigma-delta ADC.
The advantages of the bandgap-based temperature sensor front-end are very
obvious. The generated PTAT signal is highly linear with temperature and is insensitive
to process spread, which potentially can provide high sensing accuracy. Besides, supply
sensitivity can be well below significance with proper design. The state-of-the-art
performance of the bandgap-based temperature sensor achieves ±0.1 0C 3σ error over
military temperature range (-55 0C to 125 0C) with 1-point calibration [8]. The drawback
of the bandgap-based temperature sensor is that the supply voltage may not be able to be
scaled with process technologies. The terminal voltages of the BJT diodes are decided by
the turn-on voltage of PN junctions, which cannot be scaled with process technologies
easily. The supply voltages of popular bandgap-based temperature sensors are usually
higher than 1 V [8, 9].
Table 1.1 summarizes the state-of-the-art performance comparison between the
different temperature sensor architectures. The advantageous performances are
highlighted in green while the disadvantageous ones are highlighted in red. As
summarized previously, each approach has their pros and cons. Since the low-voltage
temperature sensors proposed in this dissertation are mostly based on the bandgap
structure and principle, detailed analysis for the bandgap-based sensor front-end will be
given later.
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Table 1.1. Performance comparison of the state-of-the-art on-chip temperature sensor
solutions. Pros are highlighted in green while cons are highlighted in red.
Parameter
Process
[3]
JSSC2010
Time-todigital
0.35 μm
[10]
ASSCC2007
Oscillatorbased
0.13μm
[5]
ISSCC2010
ThermalDiffusivity
0.18μm
[11]
ISSCC2009
Bandgap+2nd
order ΔΣ ADC
0.7 μm
Accuracy
±0.5 0C (3σ)
±1 0C (3σ)
±0.2 0C (3σ)
±0.1 0C (3σ)
Calibration/trimming Two-point
individual
trimming
Temperature range
0~900C
One-point
individual
trimming
27~470C
No trimming
-55~1250C
One-point
individual
trimming
-55~125 0C
Supply Voltage
1V
1.8V
2.5~5.5V
0.9μW
3mW
25μA
Architecture
3~3.6V
Current/Power Cons. 11.1μA
The data conversion units following the bandgap-based sensor front-end can be
different for different applications. For example, sigma-delta ADC can be used for high
accuracy purpose; pulse-to-digital-based converter can be used for low power purpose.
We review several data converter for bandgap-based temperature sensors here.
1.4.1. Sigma-delta ADC
clk
VIN
VX
a
Z

1
Vint
Out
VREF
Fig. 1.6. A z-domain block diagram of a 1st order sigma-delta modulator.
8
Texas Tech University, Li Lu, May 2013
Perhaps the most popular solution for the temperature dependent signal
conversion is the sigma-delta ADC [12], which consists of a sigma-delta modulator and a
demodulator. Since the temperature of the chip is usually changing slowly, the signals
generated by the sensor front-end have a narrow band at low frequency. Sigma-delta
ADC is usually used in low speed application because the sigma-delta ADC over-samples
the input signal for higher resolution. Therefore, sigma-delta ADCs have been used in
high accuracy temperature sensor applications. Fig. 1.6 shows a block diagram of a 1st
order sigma-delta modulator in z-domain. The modulator over-samples the input signal
against the reference voltage and produces a beat steam, which can be demodulated to an
output close to the input signal divided by the reference signal. The advantage of the
sigma-delta ADC is that the accuracy of the data conversion is decided by the passive
component matching such as the capacitor matching, which can be well-achieved by
careful layout. The high conversion accuracy enables the ADC to sample the input signal
with least loss. Besides, the accuracy of the sigma-delta ADC can be improved by
increasing the oversampling ratio, which trades the conversion speed to conversion
accuracy. Since temperature sensors usually generate very low frequency signals and
don’t require a high speed conversion based on the Nyquist theory, the low speed of
sigma-delta ADCs is acceptable for temperature sensor applications. The principle of a
sigma-delta modulator will be explained in detail later in this dissertation since it’s used
in the proposed low voltage temperature sensors.
1.4.2. Pulse-to-digital converter
Another type of data converter maybe used for temperature sensor is the pulse-todigital converter. Fig. 1.7 shows a simplified schematic of a pulse-to-digital converter
[13]. The operation principle is as follows: When the “sen_vst” is set as low, the supply
voltage VDD_1V will charge the two capacitors C1 and C2 to 1V. The “sen_vst” signal
is then turn to high and shut off the two charging transistors. The PTAT and CTAT
currents start to discharge the two capacitors so that the voltages on the two capacitors
decrease linearly. When the voltages on the capacitors reach the thresholds of the buffers,
the buffer outputs will flip. The two different discharging currents result in two different
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Texas Tech University, Li Lu, May 2013
discharging durations, which causes the two buffers flip at different time points, and the
XOR gate will generate a pulse whose width equals to the discharging duration
difference. Since the discharging currents are temperature dependent, the pulse width is
also temperature dependent. The pulse width will be further counted by a ripple counter
and the output bits can thus present the temperature. The advantage of the pulse-to-digital
converter is that the circuit is simple and mostly digital. The power consumption can be
low due to the digital operation. Therefore, it may be suitable for low power application.
For example, temperature sensors integrated on passive RFIDs for food storage
application supplied by the harvested RF power, which can be very low (about a couple
of microwatt) [14]. A sigma-delta ADC would need tens of microwatt to operate properly
while the pulse-to-digital converter can operate with sub-microwatt power consumption.
The major disadvantage may be the accuracy limit. For example, a factor limiting the
conversion accuracy is the clock frequency variation for the counter. The clock frequency
directly decides the counted bits for the generated pulse. Therefore, the part-to-part
variation can decrease the sensing accuracy.
Fig. 1.7. A schematic of a pulse-to-digital converter. From [13].
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Texas Tech University, Li Lu, May 2013
1.4.3. Thresholding-based converter
Another type of simple converter which can be used to convert the front-end
signals into digital readings is the threshold-based converter. Fig. 1.8 (a) shows a
schematic of the thresholding-based converter. The working principle of the
thresholding-based converter is simply comparing a PTAT voltage to a reference voltage.
The reference current can be tuned by a DAC so that the reference voltage has multiple
values, which serve as multiple thresholds for the comparator. As shown in Fig. 1.8 (b)
the PTAT voltage is compared with a pre-selected bandgap reference voltage, which
corresponds to a specific temperature level. The relationship between the reference
voltage level and the temperature is decided by a pre-calibration process. If the
comparator output becomes positive, it means the PTAT voltage is larger than the current
bandgap reference voltage, and thus the temperature now is higher than the pre-selected
temperature. It is obvious that this approach doesn’t convert the actual detected
temperature into the corresponding digital reading. It only compares the detected
temperature with a pre-selected value to decide if the temperature being monitored
exceeds a threshold. The resolution of the converter is decided by the number of
thresholds, which is usually not many. Even though this approach has the drawback of
low resolution, it can be useful for those applications where no exact temperature
information is needed, but only a thresholding is necessary. For example, some of the
modern computer CUPs (such as Intel Core2TM) have a maximum operation temperature,
which is usually around 90 0C. Damage can be resulted if operating above this
temperature. The thresholding-based temperature sensor can be implemented to avoid
overheating. Compared with other types of converter, the thresholding-based converter is
simple and can be low power consumption. In order to avoid large conversion error, the
comparator should be well-designed to minimize device mismatch and thus input-referred
offset error.
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Texas Tech University, Li Lu, May 2013
(a)
Bandgap bias
M3
M4
I1
I2
I PTAT
DAC Control
VPTAT
VREF
I REF
R3
Q1
 A
Q2
 N  A
Trip
(b)
Voltage
VPTAT
VREF
T/oC
Fig. 1.8. (a) A simple thresholding-based converter. From [15] (b) The comparison
between the PTAT voltage and the pre-selected reference voltages.
The above brief introduction summarizes different types of modern on-chip
temperature sensors for different applications and their advantages and disadvantages.
There are some other types of on-chip temperature sensors which are not listed here since
they are applicable to limited applications. As we can see, there is not a perfect solution.
For example, it’s not easy to realize both high accuracy and low voltage operation in a
design with simple implementation. One has to select an architecture based on the
application specifications, and trade off among different parameters to improve the
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Texas Tech University, Li Lu, May 2013
overall performance. Since the target of my PhD research work is to achieve high
accuracy as well as low operating voltage, and most of the designs are based on bandgap
operation, it worth to review the operation principle of the bandgap-based temperature
sensors.
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Texas Tech University, Li Lu, May 2013
CHAPTER II
BANDGAP-BASED TEMPERATURE SENSOR FRONT-ENDS
As introduced previously, a typical temperature sensor system includes a frontend which generates a proportional-to-absolute-temperature (PTAT) voltage and a
reference voltage, and data converter to convert the front-end signals into digital reading.
Most of the modern on-chip temperature sensor front-ends are based on the bandgap
operation [8, 12], and adopt an analog-to-digital converter (ADC) with high resolution to
accurately convert the front-end signal into digital as shown in Fig. 2.1. The bandgapbased sensor front-end generates PTAT voltage/current with high linearity and the PTAT
signals are insensitivity to process variation. A bandgap circuit is very important for the
sensor front-end since it generates the reference signal as well as the PTAT signal.
PTAT voltage
PTAT voltage
PTAT signal
generator
generator
generator
Temp
ADC
Temp
Reference signal
generator
Temp
Fig. 2.1. Block diagram of a typical bandgap-based temperature sensor.
2.1.
Operation principle of bandgap circuits
Fig. 2.2 shows a conventional bandgap circuit which was used for reference
generator for decades [16]. PNP BJTs are used here for example. The current mirror M1
and M2 are in the same size while the BJTs Q1 and Q2 have a size ratio of N. Or the
current mirror can be in a size ratio N while the BJTs can be identical. This results in a
current density ratio in the two BJTs. When the VBE of the BJT is much larger than tens
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Texas Tech University, Li Lu, May 2013
of micro volts, which is true in temperature sensor applications, the I-V relationship of
the two BJT diodes can be expressed as:
VBE1
nVT
V
 A2 I S exp BE 2
nVT
I C1  A1I S exp
(2.1)
IC 2
(2.2)
where IC1 and IC2 are the currents in the Collector terminal of the two BJT diodes, A1 and
A2 are the size of the BJTs, IS is the saturation current, which is process technology
dependent, n is the non-ideality factor whose value is usually around 1, and VT is the
thermal voltage and can be expressed as kT/q, where k is the Boltzmann constant, T is the
absolute temperature and q is the charge of a single electron.
(a)
(b)
M1
M2
VREF
R2
Voltage
(V)
VREF
1.2
R2
VBE1
I PTAT
R1
Q1
 A
ΔVBE
Q2
 N  A
0
-40
120
T (0C)
Fig. 2.2. (a) A bandgap reference circuit (b) The reference voltage is obtained by
combining the PTAT and CTAT signals.
The operational amplifier in the loop forces equal voltage at A and B. Therefore,
the voltage drop on the resistor R1, which is the difference of the two VBE, can be
calculated as:
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Texas Tech University, Li Lu, May 2013
VBE  nVT ln(
I C1 A2
I A
nkT
nkT
)
ln( C1 2 ) 
ln( N )
I C 2 A1
q
I C 2 A1
q
(2.3)
which is a PTAT voltage and the slope is decided by the current density ratio. The
currents I1 and I2 are thus also PTAT assuming that the resistor R1 has a negligible
temperature coefficient.
On the other hand, either of the two VBE is a CTAT voltage to the first order [16].
The collector current IC can be expressed as Eq. (1). The saturation current IS is
proportional to μkTni2, where μ is the mobility of minority carriers, k again is the
Boltzmann constant, T is the absolute temperature and ni is the intrinsic minority carrier
concentration of silicon. μ and ni2 can be expressed as:
(2.4)
  0T m
ni2  T 3 exp[ Eg
where
, and
 kT ]
(2.5)
is the bandgap energy of silicon. In Eq. (1), let the IS
contain the emitter area A, the saturation current IS can be written as:
 E 
I S  bT 4 m exp  g 
 kT 
where b is a proportionality factor including the emitter area A. Since
(2.6)
,
we now can derive the temperature dependence of the VBE. Take the derivative of VBE
with respect to T, we have:
VBE  VT  I C VT I C VT I S

ln 

T
T
I S I C T I S T
(2.7)
From Eq. (6), we have:
E
 E  E 

I S
 b  4  m  T 3 m exp g  bT 4 m  exp g  g2 
T
kT
kT  kT 

Therefore,
16
(2.8)
Texas Tech University, Li Lu, May 2013
Eg
VT I S
V
  4  m  T  2 VT
I S T
T kT
(2.9)
Since the IC is a PTAT current in the bandgap circuit as just derived, VT/IC becomes
temperature independent and the derivative of IC is also temperature independent.
Therefore, the middle term in Eq. (7) becomes a constant. We can rewrite Eq. (7) as:
Eg
VBE VT I C
V
 ln   4  m  T  2 VT  C
T
T
IS
T kT

VBE   4  m VT  Eg q
T
(2.10)
C
where C is a constant representing the middle term in Eq. (7). Eq. (10) indicates that the
temperature coefficient of VBE is not a constant value and depends on VBE itself.
Numerical calculation shows that the temperature coefficient of VBE is about -1.5 mV/0K
with VBE being around 0.75 V at 300 0K [16]. Simulation and characterization results
show that the VBE is negative with some 2nd order non-linearity. Since the PTAT voltage
ΔVBE has a well-defined temperature coefficient, the curvature in the CTAT voltage VBE
makes the combined bandgap reference voltage not perfectly constant over a large
temperature range, and curvature correction techniques are sometimes necessary for high
precision reference circuits [17].
2.2.
Bandgap-based temperature sensor front-ends
Having understood the bandgap circuit operation for PTAT, CTAT and reference
signal generation, bandgap-based temperature sensor front-end can be developed with
some flexibility. An easy way is to use the same circuit as in Fig. 2.2, where a PTAT
voltage and a reference voltage are already available. An ADC with differential inputs
can sample the PTAT voltage over R1 against the reference voltage and ground.
However, the PTAT voltage ΔVBE is in the scale of tens of micro volts while the reference
voltage here is about 1.25V. It will be shown in the ADC section that the noise level of an
ADC is decided by the reference voltage. A larger reference voltage results in larger
quantization noise. Therefore, the signal-to-noise-ratio (SNR) will be low and limit the
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Texas Tech University, Li Lu, May 2013
sensor resolution if we sample the PTAT voltage directly against this large reference
voltage. The solutions are either amplifying the PTAT signal or reduce the reference
voltage level or applying both of them. A 1.25 V bandgap reference voltage not only too
large for an acceptable SNR, but also too large for low voltage operation since the supply
voltage have to be larger than the reference voltage. Therefore, subbandgap reference
circuits have been studied for a lower reference voltage generation with a lower supply
voltage operation. The subbandgap reference circuits will be discussed in detail in a
following section since they are adopted in the proposed low-voltage temperature sensors
in this dissertation.
M1
M3
M2
M4
VREF
R2
R2
VBE
I PTAT
R1
QB1
 A
QB 2
 N  A
Q1
Q2
Fig. 2.3. A simplified bandgap-based temperature sensor front-end. From [12]
Besides the simple sensor front-end as in Fig. 2.2, another bandgap-based sensor
front-end as shown in Fig. 2.3 is more popular. Two bias currents in a ratio are generated
from a bias circuit (usually a PTAT current generator, which is similar to a bandgap
circuit). The two bias currents in a ratio are used to drive two identical BJT diodes. The
ΔVBE of the two diodes is PTAT and can be sampled by a following ADC. One may ask
what is the advantage of copying the bias current out to driven BJTs over directly use the
PTAT voltage in the bias circuit. Based on the discussion between the author and Dr.
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Texas Tech University, Li Lu, May 2013
Pertjis who invented the structure, the bandgap loop can stay closed when mismatch error
correction techniques such as dynamic element matching (DEM) are applied to the diodes
Q1 and Q2. More detailed explanation on the error correction techniques will be given in
the next section.
Calibration or trimming is usually needed in order to decide the slope as well as
offset of the temperature reading. Due to process variation and device mismatch, there
are part-to-part errors in the PTAT voltage as well as the reference voltage, and this error
can be temperature-dependent and limit the accuracy of the sensor. Table 1.2 shows the
performance of some stat-of-the-art BJT-based temperature sensor. It should be noted
that the BJT-based temperature sensor have less than 1 0C error after 1-point calibration,
which is good enough for most of the applications. However, the supply voltages in these
works are larger than 2.5 V in traditional process technologies, or larger than 1 V in
modern process technologies, which is usually high for low voltage applications.
Table 1.2. State-of-the-art performance of the bandgap-based individual temperature
sensors
Parameters
[18]
ISSCC2003
Accuracy
±0.50C (3σ)
one-point
Calibration/trimming individual
trimming
[8]
JSSC2005
±0.10C/±0.50C
(3σ)
with/without
one-point
individual
trimming
Temperature range
-50~1200C
-55~1250C
Supply Voltage
Process
2.7~5.5V
0.5 μm
2.5~5.5V
0.7 μm
19
[11]
ISSCC2009
±0.10C/±0.250C
(3σ)
One-point
individual/batch
calibration
(-55~125)/(70~130)0C
2.5~5.5V
0.7 μm
[9]
ISSCC2010
±0.20C (3σ)
One-point
Individual
calibration
-70~1250C
1.2V
65nm
Texas Tech University, Li Lu, May 2013
CHAPTER III
THE PROPOSED LOW-VOLTAGE TEMPERATURE SENSORS
Having reviewed different types of on-chip temperature sensor solutions, one can
find that the bandgap structure outperforms the others in terms of sensing accuracy and
supply sensitivity, which makes the bandgap-based temperature sensors the most popular
high precision on-chip temperature sensor solution. However, as mentioned in the
previous sections, the traditional bandgap-based temperature sensors use BJT diodes and
the terminal voltages of BJTs cannot be scaled with process technologies easily.
Therefore, the BJT-based sensors need a high and non-scalable supply voltage. As the
feature sizes of process technologies keep shrinking down and the demand for batteryoperated portable equipment increases, low supply voltage and small chip area become
very important design criteria. Fig. 3.1 shows the 2011 international technology roadmap
for semiconductors where the transistor feature size and the supply voltage scaling down
is anticipated. As an integrated function block in a digital process, the temperature sensor
system desires a low operational voltage and a small occupied area.
(a)
30
HP
LOP
LSTP
III-V/Ge
Gate Length (nm)
25
20
15
10
5
2012 2014 2016 2018 2020 2022 2024 2026
Year
20
Texas Tech University, Li Lu, May 2013
(b)
1
HP
LOP
LSTP
III-V/Ge
Supply Voltage (V)
0.9
0.8
0.7
0.6
0.5
0.4
2012 2014 2016 2018 2020 2022 2024 2026
Year
Fig. 3.1. The 2011 international technology roadmap for semiconductors (a) the scaling
roadmap for transistor gate length (b) the scaling roadmap for the supply voltages of
different types of devices: high performance (HP), low operating power (LOP), low
standby power (LSTP) and III-V family semiconductor/Germanium devices (III-V/Ge)
Due to the superior performance of the bandgap-based temperature sensor in
terms of accuracy and supply sensitivity, most of the sensors proposed in this dissertation
are in the similar structure. However, the supply voltage of the BJT-based sensors is high
and cannot be scaled with process technologies. In order to realize low voltage operation,
both the sensor front-end and the ADC need to be redesigned without harming the other
performances significantly. It should be noted that the ADCs in the bandgap-based
temperature sensor, e. g., a sigma-delta ADC, are mostly MOSFETs-based and the supply
voltage can be scaled with process technologies. Besides, the sensor performances are
dominated by the sensor front-end. Therefore, the main effort has been paid on the sensor
front-end design in this dissertation.
In order to achieve low and process scalable supply voltage for the sensor frontend, MOSFETs working in subthreshold region are used to replace the BJTs in the
bandgap circuit as shown in Fig. 3.2. The theory behind using MOSFETs for temperature
sensing will be given in the next subsection. With the MOSFETs diodes in the bandgap
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Texas Tech University, Li Lu, May 2013
circuit, the diode voltage VBE becomes VGS of the diode-connected MOSFETs. The VGS of
a MOSFET is decided by the threshold voltage of the transistor VTH, which is process
technology scalable. If we don’t consider the error correction amplifier in the bandgap
circuit for the time-being, the supply voltage of the MOSFET-based bandgap will be
decided as Eq. (11), which is process technology scalable.
VDD  VGS1  VDS 3
(3.1)
The error correction amplifier can be also re-designed to operate as low voltage so
that the overall supply voltage of the bandgap circuit can be minimized. The
methodologies for the low voltage error correction amplifier design will be explained in
the following sections. Before that, the theory of using subthreshold MOSFTEs as
temperature sensing devices will be explained.
M3 M4
I1
I2
A
VGS
B
M1
 A
M2
 N  A
R3 VGS
Fig. 3.2. A low voltage bandgap circuit with subthreshold MOSFET diodes.
3.1.
Theory behind using subthreshold MOSFETs as sensing device
A MOSFET is known as working in subthreshold region when its gate-to-source
voltage VGS is close to or less than the threshold voltage VTH, and the channels are weakly
inverted rather than strongly inverted as in active region. As shown in Fig. 3.3, the
transistors M1 and M2 operate in subthreshold region have drain diffusion currents
dominated and decided by:
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Texas Tech University, Li Lu, May 2013
I D  2nCOX VT2 W L  exp VGS  VTH  nVT 
(3.2)
where n is the substrate factor in the EKV MOS model [19], μ is the carrier mobility, COX
is the gate-oxide capacitance per unit area, VT is the thermal voltage, W and L are the
channel width and length respectively, VGS is the gate-source voltage, and VTH is the
threshold voltage.
I
VGS1
N×I
M1 M 2
VGS2
Fig. 3.3. Using MOSFETs as sensing devices.
Assuming that the substrate factor n has small variations with temperature [20],
VGS can be approximated as:
VGS T   VGS T0   KG (T T0  1)
where KG  KT  VGS T0   VTH T0   VOFF
(3.3)
(3.4)
KT is the temperature coefficient of VTH, T0 is the room temperature and VOFF is a
corrective constant term in BSIM3v3 MOS models [19]. KG is a negative constant and
VGS is CTAT to the first order. Similar as the analysis for the BJT diodes, the voltage
difference between the two VGS is given by Eq. (15), where N is the current ratio or the
size ratio of M2 and M1. The CTAT voltage and the PTAT voltage can be combined to
obtain a reference voltage.
VBE 
nkT
ln( N )
q
23
(3.5)
Texas Tech University, Li Lu, May 2013
3.2.
A low voltage temperature sensor front-end based on an error
corrected current mirror structure
As analyzed previously, a modified bandgap circuit with subthreshold MOSFET
diodes can serve as a low voltage temperature sensor front-end. The error correction
amplifier is necessary for supply rejection. As shown in Fig. 3.2, the amplifier forces
equal drain voltage of M3 and M4 regardless to the supply voltage variation. Therefore,
the current ratio can be well-defined by the current mirror size ratio only. The PTAT
current is thus well-defined by the diode size ratio and the value of R3.
With the subthreshold MOSFETs M1 and M2 replacing traditional BJT devices,
the overall supply voltage of the bandgap core can be greatly reduced if the op-amp is not
considered. As mentioned previously, the error correction amplifier can be also designed
in low-voltage operation so that the overall bandgap circuit has a minimized operation
voltage. A traditional op-amp with NMOS differential input pair needs an input common
mode voltage of larger than VGS+VDSAT, which is not available in the subthreshold
MOSFET diodes-based bandgap loop where the input common mode voltage of the
amplifier is only a VGS, and a PMOS counterpart needs a large supply voltage of
VCM+VGS+VDSAT, where VCM is the input common mode voltage and equal to a VGS. Both
of them are undesirable for low-voltage design. Therefore, a bulk-driven technique is
applied when designing a low-voltage error correction amplifier. Fig. 3.4 shows a
subthreshold MOSFET-based bandgap core with a bulk-driven-based error correction
amplifier, where a semi-folded-cascode structure is used for the amplifier as an example
without losing generality [21]. The gates of the input PMOS pair (M6, M7) can be
connected to GND in order to minimize the supply voltage, and the input voltage is
applied to the transistor body. As a result, the amplifier power supply voltage can be as
low as VGS8 + VDSAT10+ VDSAT17 if VGS6 was less than VGS8+VDSAT10. This is valid because
M6 and M7 operate in weak inversion region. Therefore, the overall supply voltage of the
proposed front-end can be reduced and scaled with process technologies.
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Texas Tech University, Li Lu, May 2013
M3 M4
I1
I2
Vb
I3
M5
M 17
M6
M7
CC
Vout
R3
M1
M2
M8
out
M 10
R4
Fig. 3.4. A subthreshold MOSFET-based bandgap core with a bulk-driven semi-foldedcascode error correction amplifier.
3.3.
A low voltage temperature sensor front-end based on an regulated
current mirror structure
Since an on-chip voltage regulator is usually available, a simple regulated current
mirror structure can be used for temperature sensor front-end to save chip area as shown
in Fig. 3.5. M1 and M2 operate in subthreshold region and have a size ratio. As in the
bandgap-based structure, the ratio can be also from the current mirror instead of the
subthreshold MOSFETs. The VGS of M1 and M2 are CTAT to the first order as in the
bandgap-based structure, while the ΔVGS, which is the voltage drop on R1, is PTAT if
ignore the body effect of M2. The PTAT current can thus be copied to drive a resistor R2
to generate a amplified version of PTAT voltage for testing purpose.
Given that the drain voltage of M4 is VGS2 + ΔVGS regardless of the supply voltage
while the drain voltage of M3 can change with supply voltage so that the current ratio of
M3 and M4 becomes supply voltage dependent, a simple single-ended common-source
amplifier is used to make the drain voltage of M3 follow that of the M4 so as to improve
the supply sensitivity. In order to further improve the supply sensitivity, a low-dropout
(LDO) regulator is used to power the sensor front-end. Since the supply voltage of the
front-end is larger than VGS1 + VDSAT3, where VDSAT3 is the minimum VDS of M3 to ensure
active region operation, a NMOS input pair is desired for the amplifier in the regulator so
as to minimize the supply voltage of the regulator.
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Texas Tech University, Li Lu, May 2013
Regulator
To Op-amp Output
M3
M4
M0
IPTAT
VPTAT
M1
Vb
M2
R1
ΔVGS
R2
Fig. 3.5. A simplified schematic of a temperature sensor front-end in a regulated current
mirror structure
3.4.
Error sources and error correction techniques for the low-voltage
temperature sensor front-ends
The subthreshold MOSFETs serving as sensing diodes enables low and process
scalable supply voltage for the sensor front-end. However, compared with traditional
BJTs, the subthreshold MOSFETs suffer from much process spread and mismatch error.
Therefore, in both the error corrected current mirror structure and the regulated current
mirror structure, the output signals have large error due to the process spread and device
mismatch. For the error corrected current mirror structure, the loop gain can be low if a
bulk-driven amplifier is used for low supply voltage purpose, which results in large offset
error. Particularly, the PTAT voltage ΔVBE is insensitive to process variation but sensitive
to device mismatch, while the CTAT voltage VBE and thus the reference voltage is
sensitive to both process variation and device mismatch. As mentioned previously,
sensing diodes are distributed remotely in scattered sensor, while other parts including
the reference signal generator are shared. Therefore, the relative sensing accuracy is only
decided by the PTAT signals from all the remote sensor nodes rather than the reference
signal, which means that the mismatch induced error dominates the relative sensing
26
Texas Tech University, Li Lu, May 2013
accuracy in a scattered sensor. Since the scattered relative temperature sensors are
eventually the focus of this dissertation, mismatch induced error in the sensor front-end
will be analyzed and corresponding error correction techniques will be implemented in
this work.
M3
1
I1
I2
VOS
M1
1
M4
1   2 
R3 VGS
M2
 N  1 
Fig. 3.6. A PTAT signal generator with device mismatches.
The front-end in the error corrected current mirror structure will be analyzed as an
example without losing generality. A simplified PTAT signal generator is redrawn here
in Fig. 3.6 with device mismatches in the diodes, current mirror and the error correction
amplifier. The device size ratio N is in the diodes in this example, but note that the N can
be also in the current mirror or in both the diodes and the current mirror in order to
generate a PTAT signal. Due to the device mismatches, the PTAT voltage ΔVBE is
modified as:
VBE 
nkT
ln( N   )  VOS
q
(3.6)
where δ represents the device mismatches in the diodes as well as the current mirror, and
the VOS is the input referred offset voltage of the amplifier due to the mismatch in the
differential pairs in the amplifier. Since the input referred offset voltage is attenuated by
27
Texas Tech University, Li Lu, May 2013
the amplifier gain, VOS increases as the loop gain decreases and can be significant in the
low-gain bulk-driven-based design.
In order to minimize the mismatches induced errors as in Eq. (16), error
correction techniques have to be implemented. For example, gain boosting can be used
for the low-gain bulk-driven amplifier without harming the low voltage operation so as to
reduce the offset error. Other techniques such as dynamic element matching (DEM) and
dynamic offset cancellation (DOC) can be applied to minimize the various mismatch
induced errors. Introduction to the error correction techniques will be give in this section.
3.4.1. Dynamic element matching and dynamic offset cancellation
Dynamic element matching (DEM) has been used to minimize mismatch errors
for years [22]. The idea is to exchange the position of the devices so that the output flips
and the mismatch error can be averaged out to the first order. As an example, Fig. 3.7
illustrates how a DEM function applies to the current mirror in the bandgap circuit. The
DEM consists of four switches controlled by complementary clocks. At phase 1, the S1
and S2 are enabled and the circuit is configured as the case in the middle of Fig. 3.7 (a).
At phase 2, S1’ and S2’ are enabled and the circuit is configured as the case on the right
of Fig. 3.7 (b). The positions of the two transistors M3 and M4 are thus exchanged. Based
on Eq. (16), one of the outputs of the two cases will be larger than the ideal value and the
other one will be smaller than the ideal value as shown in Fig. 3.7 (b). The averaged
output can thus be close to the ideal value.
(a)
Φ2
Φ1
M4
M3
S1
S1'
S2
S2'
M4
M3
DEM
DEM
To diodes
To diodes
28
Texas Tech University, Li Lu, May 2013
(b)
Φ1
Ideal value
Output
Φ1
Φ2
0
Φ2
Time
Fig. 3.7. (a) The operation principle of dynamic element matching (b) The output of the
design with DEM compared with the ideal output value without any mismatch.
The offset error from the error correction amplifier is also due to device
mismatches inside the amplifier. For example, mismatch in the input pair of the amplifier
results in an input referred offset voltage. The offset error can be minimized by dynamic
offset cancellation (DOC), which swaps the input signals of the amplifier at the same
pace of switching the polarity. A typical DOC also has 4 switches as the same as in a
DEM in Fig. 3.7. The operation principle is illustrated in Fig. 3.8, which is similar to that
of DEM. A simple current mirror-based amplifier is used in this example. The input
referred offset voltage changes to its opposite value from phase 1 to phase 2 and the
averaged output is then close to the value without offset error.
(a)
Φ1
M3
M4
Vb
MA1
MA0
MA2
R3
VO
MA3
M1
M2
29
MA4
Texas Tech University, Li Lu, May 2013
(b)
Φ2
M3
M4
Vb
MA1
R3
MA2
VO
MA3
M1
MA0
MA4
M2
Fig. 3.8. The operation principle of the dynamic offset cancellation
3.4.2. Gain boosting for the bulk-driven error correction amplifier
A bulk-driven amplifier can be used in the bandgap front-end for low voltage
operation. However, the bulk-driven-based amplifier has an input transconductance of
gmb instead of gm, which can result in low gain so that the input referred offset voltage is
large. Besides using DOC to minimize the offset error, which is a well-known
technology, a gain boosting mechanism in a gate-bulk-driven amplifier has been
proposed to reduce the offset error. This method can be applied for reference/PTAT
signal generators, especially when a stable reference signal without switching jumping is
desired. Fig. 3.9 shows a simplified schematic of the reference signal generator along
with the proposed gate-bulk-driven error correction amplifier.
Instead of grounding the gates of the amplifier input pair as in the bulk-driven
amplifier, a portion of the input signals are fed into the gates. The input transconductance
of the amplifier thus becomes gmb + r*gm, where r is the scaling factor representing the
percentage of the fed in signals to the gates, which is decided by the resistor ratio R 1’ /
(R1’ + R1). As a trade-off, the voltage headroom of the amplifier is consumed by r * VGS1,
which can hurt the low voltage operation if r is large. Fortunately, typically gm is much
larger than gmb. Therefore, r can be small to trade off between the boosted gain and the
minimum supply voltage. Detailed analysis and simulation/experimental results on this
gain boosting mechanism will be presented in a following design example.
30
Texas Tech University, Li Lu, May 2013
M4
Vb
b
b
g
g
b
M3
A
Vref
B
R1
R2
b
g g
To Op-amp Output
R3
R4 The Gate-Bulk-Driven
Error Correction
Amplifier
R1' R2 ' M 2
M1
M6 M7
Fig. 3.9. A simplified schematic of the reference signal generator along with the proposed
gate-bulk-driven error correction amplifier
3.4.3. Clock boosting
With the DEM and DOC in the sensor front-end, CMOS switches (usually NMOS
switches or transmission gate) are stacked along the current path. The on-resistance of the
switches should be as small as possible to avoid possible errors. The analog voltages to
be passed by the switches can be around VDD/2, where it is hard to completely turn on the
switches if the supply voltage is lower than VTH-N+VTH-P, which is true in a low voltage
design. As a result, a clock boosting technique is adopted in order to accommodate the
low supply voltage design requirement without additional errors. A popular clock
boosting circuit that can be used in this work is shown in Fig. 3.10 (a). When the clock
feeds in, the NMOS pair charges the two capacitors until the voltage across the capacitors
almost reach VDD. Then the high voltage level of the output clock is lifted by the voltage
across the capacitors and can be about twice of the input clock amplitude. The simulated
boosted clock vs. the input clock in AMI 0.5μm process is plotted in Fig. 3.10 (b). With
an input clock of 1V, the boosted clock is close to 2 V, which becomes larger than VTHN+VTH-P
in this process (VTH-N ~ 0.8 V, VTH-P ~ 0.9 V), which turns on the switches
completely, so that the voltage drop on the switch is negligible.
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Texas Tech University, Li Lu, May 2013
(a)
(b)
CLK
CLK_Boosted
22
Voltage(V)
Voltage
(V)
CLK_Boosted
1.5
11
0.5
00
0
0
CLK
10
10
Time (mS)
20
20
Time(ms)
Fig. 3.10. (a) A simplified clock boosting circuit (b) The simulation results of the clock
boosting in AMI 0.5μm CMOS process
3.5.
Introduction to the sigma-delta modulator
An ADC is used to convert the analog signals generated in the front-end into
digital reading. It has been shown that the class of sigma-delta (ΣΔ) ADC is well suited
for temperature sensor application [12]. In order to accurately convert what the front-end
senses to digital temperature readings, the ADC is supposed to achieve high enough
resolution so that the quantization error is negligible compared with the errors from the
front-end. The performance requirement on the sigma-delta ADC in temperature sensor
application is moderate. Specifically, temperature sensors typically generate signals in
low frequency (<100 Hz) so that the speed requirement is low. For example, with an
oversampling ratio of 256 and a signal band of 200 Hz, the clock frequency of the sigmadelta ADC is about 50 KHz, which is well-below the state-of-the-art performance
(several MHz clock speed). Besides, the resolution requirement on the sigma-delta ADC
in a temperature sensor is also moderate. For example, a sigma-delta ADC with 14
effective number of bits (ENOB) has a quantization error of about 0.02 0C if 1/3 full
range of the ADC is used. Detailed analysis on the resolution requirement for a specific
temperature sensor will be derived later in this section. Since the sigma-delta ADCs have
been well-studied and the performance requirement for the ADC in temperature sensor
32
Texas Tech University, Li Lu, May 2013
application is moderate, only introduction and behavior level analysis will be given in
this dissertation, while detailed circuit level design will not be presented.
The block diagram of a second order sigma-delta modulator is shown in Fig. 3.11.
The corresponding linear z-domain model is also presented. The quantizer is modeled as
an additive noise source. From the block diagram,
V  z  E z 
1  1
1

z V  z  
 z 1V  z   U  z   
1 
1 
1 z 
1 z

1  z  E  z   1  z  z

1  z 
 U  z   1  z  E  z 
1 2
1
1
1 2
 z 1  V  z   U  z 
1 2
(a)

u
(3.7)

v
DAC
(b)
E
U

1
1  z 1

1
1  z 1
V
z 1
Fig. 3.11. (a) Block diagram of a second order sigma-delta modulator (b) Linear zdomain model of the modulator
Hence, the signal transfer function is STF(z)=1, while the noise transfer function
is NTF(z)=(1-z-1)2. After replacing z with ej2πf/fs, where, fs is the sampling rate, the squared
magnitude of the NTF as a function of the normalized frequency is illustrated in Fig. 3.12
[23]. In a typical smart temperature sensor design, the signal band is around 10 Hz. As
shown in Fig. 3.12, the quantization error in the signal band is greatly attenuated, so that
the signal-to-noise-ratio is improved and high resolution is achievable. This resolution
33
Texas Tech University, Li Lu, May 2013
improvement is due to the oversampling behavior of the sigma-delta ADC. It can be
shown that for a second order sigma–delta ADC, doubling the oversampling ratio (OSR)
increases 2.5 bits resolution. Taking advantage of the fact that the frequency of the input
signal in the temperature sensor application is low (below 10Hz), the clock frequency
needed for the second order sigma-delta ADC only needs to be in the range of kHz.
16
14
NFT  e j 2 f

2
12
10
Signal Band
8
6
4
2
0
0
0.1
0.2
0.3
0.4
Normalized
Frequency(f/fs)
Normalized
Frequency
( f fs )
0.5
Fig. 3.12. Noise shaping of the 2nd order sigma-delta modulator
In order to understand how the modulator operates in time domain, one can look
into the charge balance of the modulator. Without losing generality, Fig. 3.13 shows the
charge balance operation of a first order sigma-delta modulator. It’s straightforward that
the integrator’s input voltage VX is:
a  VBE
VX  
VBE
if out  0
if out  1
(3.8)
The feedback in the modulator drives the output of the integrator back to zero.
The charge balance ensures that the average charge accumulated in the integrator is
(approximately) zero. If, in a total number of clock cycles Ntotal, the bitstream is one
during N1 clock cycles, the charge balancing implies
34
Texas Tech University, Li Lu, May 2013
Ntotal VIN  N1 VREF
or
(3.9)
V
N1
 IN
Ntotal VREF
(3.10)
which means that the bit density of the output bitstream can indicate the input amplitude.
For the second order sigma-delta modulator, the same principle applies.
(a)
clk
VBE
a
VIN
VX


VBE
(b)

Vint
Out
VREF
Vint
t
Out
clk
t
Fig. 3.13. (a) Simplified realization of the transfer of a first order sigma-delta modulator
(b) Timing of the modulator
The resolution required at the output of the ADC depends on the requirements of
the application. In order to obtain an inaccuracy of ±0.10C, the resolution of the ADC is
desired to achieve ±0.010C so that the quantization error can be negligible. Define the
‘effective number of bits’ (ENOB) to express the ADC’s total quantization error as a
fraction of its full scale. In order to achieve an inaccuracy of ±0.010C, the maximum
quantization error of the modulator, which corresponds to half of the least significant bit
35
Texas Tech University, Li Lu, May 2013
(LSB), should be equal to ±0.01 0C, i. e., max(Dout-Dout,ideal)=±0.5 LSB=±0.01 0C.
Therefore,
Dout  Dout ,ideal 
D
2
(3.11)
FS
ENOB 1
where DFS is the full-scale value. As a result,

DFS
ENOB  log 2 
 max Dout  Dout ,ideal




 1


(3.12)
The value of DFS depends on the front-end outputs. Assume that the outputs of the frontend are proportional-to-absolute-temperature (PTAT) voltage ΔVBE and decreasing-withtemperature (DWT) voltage VBE. The two voltages can be combined to obtain a ratio µ
that is an accurate function of temperature as expressed by Eq. (6).

a  VBE
VBE  a  VBE
(23)
where the numerator is PTAT and the denominator is temperature-independent. In a
common front-end design, the extremes of the military operation temperature range of 55 0C to 125 0C correspond to roughly µ=1/3 and 2/3. Therefore, about 1/3 of the ADC’s
full scale will be used. The full scale then corresponds to a temperature range of about
DFS=550 0C. Substituting the value of DFS to Eq. (3), the required ENOB can be found as
about 14.8 bits and an OSR of 256 is enough for this application. The efficiency of the
ADC’s full scale usage can be increased so that the required ENOB can be reduced and
the OSR can be even smaller, for example, an OSR of 128 is enough for 80% usage of the
ADC’s full scale [12]. Therefore, the sampling rate or the system clock can be further
reduced.
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Texas Tech University, Li Lu, May 2013
CHAPTER IV
DETAILED PROTOTYPE DESIGNS
4.1.
A subthreshold MOSFET-based subbandgap reference voltage
generator
4.1.1. Operation principles and circuit design
A low voltage reference generator is desirable for the temperature sensor. The
generated reference voltage is required to be supply, temperature and process
independent. Otherwise, the error in the reference voltage will contribute to sensing
inaccuracy. The most common voltage references are bandgap references (BGR) [24, 25],
which generate a nearly temperature-independent reference of about 1.25 V in traditional
processes, and therefore require a higher supply voltage which may not be applicable for
low voltage designs. In order to achieve a sub-1 V supply voltage, several subbandgap
solutions based on BGR principle but with lower reference outputs have been proposed
[17, 26-29]. Bipolar junction transistors (BJTs) are usually used in the bandgap or
subbandgap circuits to generate a proportional-to-absolute-temperature (PTAT) and
complementary-to-absolute-temperature (CTAT) voltage or current. Even though the BJT
based reference voltage generators exhibit low temperature- and process- sensitivities,
they suffer from high supply voltage or large chip area since the terminal voltages of BJT
devices cannot be easily scaled with process technologies [7].
To further achieve lower and process-scalable supply voltages, subthreshold
MOSFETs are used to replace the BJTs in the bandgap or subbandgap circuits for
reference generation [20, 30, 31]. As our first try, we implemented a MOSFET-based
subbandgap reference circuit as shown in Fig. 4.1 [21]. As introduced previously, The
VGS1 is a CTAT voltage to the first order, which results in a CTAT current in R 1 and R2.
Properly combined with the PTAT current in R3, the current in the current mirror I1, I2
and I3 are independent of temperature. Therefore, the voltage on R4 will be a reference
voltage and can be expressed as:
37
Texas Tech University, Li Lu, May 2013
Vref   R4 R3  nVT ln  N    R3 R2 VGS 
(4.1)
When R3/R2 is -VTT0ln(N)/KG, I1, I2 and I3 are temperature independent.
M3 M4
I1
M1
I2
R1 R2
Vb
I3
M 17
M6
M7
CC
Vout
R3
M2
M8
out
M 10
R4
Fig. 4.1. Schematic of the MOSFETs-based subbandgap reference circuit with a semifolded-cascode bulk-driven amplifier.
With the subthreshold MOSFETs M1 and M2 replacing traditional BJT devices,
the supply voltage of the subbandgap core can be reduced with scaled CMOS
technologies if the op-amp is not considered. The supply voltage of the op-amp has to be
reduced to the same scale of the subbandgap core to fully take advantage of the low
voltage devices. A traditional op-amp with NMOS differential input pair needs an input
common mode voltage of larger than VGS+VDSAT, which is not applicable in the
subbandgap circuit based on subthreshold MOSFETs. A PMOS input pair counterpart
needs a large supply voltage of VCM+VGS+VDSAT, where VCM is the amplifier input
common-mode voltage that is slightly smaller than a VTH of an N-MOSFET. Amplifiers
with bulk-driven PMOS input pair can be a candidate for low voltage operation [21].
Specifically, in the semi-folded-cascode amplifier in Fig. 4.1, the gates of the input
PMOS pair can be grounded in order to minimize the supply voltage, and the input
voltages are applied to the bodies of the input PMOS pair. As a result, the minimum
supply voltage of the error correction amplifier can be lowered so that the overall supply
voltage of the subbandgap circuit can be further reduced.
38
Texas Tech University, Li Lu, May 2013
4.1.2. Experimental results
The proposed subbandgap reference circuit was fabricated in AMI 0.5 µm CMOS
as well as UMC 130nm CMOS technology. Fig. 4.2 shows the micrograph of the
proposed voltage reference generator circuit. The total chip area excluding pads is
490×660 um2. As shown in Fig. 4.3 and Fig. 4.4, the measured minimum supply voltages
at room temperature at room temperature are below 1 V and 0.4 V for the two processes
respectively. The temperature sensitivity of the design in AMI 0.5 µm process from 0 0C
to 100 0C was measured as 9.9 ppm/0C. The temperature sensitivity was calculated by the
following equation
Temprature Sensitivity=
Outmax  Outmin
106
Outave  Tmax  Tmin 
Active Circuit
490 X 660 µm2
Fig. 4.2. Photomicrograph of the subbandgap reference circuit.
39
(4.2)
Texas Tech University, Li Lu, May 2013
Vout [mV]
400
300
200
100
0
0.8
1
1.2
1.4
1.6
1.8
Power supply voltage [V]
2
Fig. 4.3. Measured minimum supply voltage and line sensitivity at room temperature in
AMI 0.5 μm CMOS process
0.2
Vout [mV]
0.15
Subbandgap
Reference Circuit
340 X 140 µm2
0.1
0.05
0
0.2
0.4
0.6
0.8
1
Power supply voltage [V]
Fig. 4.4. Measured minimum supply voltage and line sensitivity at room temperature in
UMC 130nm CMOS process
4.1.3. Conclusion
Compared with tradition BJT-based reference generator, the subthreshold
MOSFETs-based alternative provides lower supply voltage. More importantly, the supply
voltage is scalable with process technologies. The line sensitivity is acceptable for a low
voltage design, and the temperature sensitivity is reasonable for the MOSFETs-based
design. However, device mismatches can cause large part-to-part error in the generated
40
Texas Tech University, Li Lu, May 2013
reference voltage. Particularly, the amplifier input-referred offset can be a dominant error
source since the amplifier gain is usually not high enough without full cascode in low
voltage designs. Moreover, the amplifier gain could be lower as the process technologies
scale. In the bulk-driven based amplifier adopted in the proposed subbandgap circuit, the
input transconductance is the body-effective transconductance gmb rather than the gatesource transconductance gm. Since gmb is typically 1 order of magnitude smaller than gm,
the amplifier gain is further lower. In order to accommodate the requirements of low
voltage as well as small output error, we then proposed a subthreshold MOSFETs-based
subbandgap reference generator with a gain boosting mechanism in the error correction
amplifier.
4.2.
A subthreshold MOSFETs-based subbandgap reference generator
with a gain boosted error correction amplifier
4.2.1. Operation principles and design details
Device mismatches in the subthreshold MOSFETs, resistors, current mirrors and
op-amp can cause significant error in the generated reference voltage. The offset error
resulted from the mismatches in the op-amp can be dominant when the op-amp has a
lower gain as process technologies scale down. Since the input transconductance of a
bulk-driven amplifier is the body-effective transconductance gmb rather than the gatedrain transconductance gm, the overall gain of the bulk-driven op-amp is smaller than that
of a gate-driven counterpart, so that the bulk-driven op-amp can have a higher inputreferred offset. Therefore, the error at the subbandgap circuit output could be larger in the
bulk-driven design. Besides, a high gain amplifier improve the supply sensitivity of the
bandgap loop since the supply rejection of the amplifier is improved. In order to
minimize the op-amp offset error by increasing the op-amp gain, a gate-bulk-driven error
correction amplifier with 4 input ports is proposed in this paper to boost the gain while
maintaining the low supply voltage operation [32]. Fig. 4.5 shows the schematic of the
subbandgap reference circuit with the proposed gate-bulk-driven amplifier.
41
Texas Tech University, Li Lu, May 2013
M3
M4
Vb
I2
b
g
g
b
I1
A
B
R1 R 2
M1
M6 M7
b
VREF
b
g g
To Op-amp Output
R3
R4
The proposed Gate-BulkDriven Error Correction
Amplifier
R 1 R 2 M 2
Fig. 4.5. Schematic of the reference voltage generator with the proposed gate-bulk-driven
gain-boosted error correction amplifier.
Instead of grounding the gates of the input PMOS pair, a fraction of VGS1, i. e.,
VGS1
R1’/(R1+R1’), is fed to the gates of the PMOS input pair M6 and M7 [33]. As a
result, the effective input transconductance of the op-amp becomes:
GM  gmb  r  gm  g mb  g m  R1
R  R
1
1
(4.3)
where gmb and gm are the body-effective transconductance and the gate-drain
transconductance of the input PMOS transistors, respectively, and r = R1’/(R1+R1’) is a
scaling factor. Since gm is typically much larger than gmb, the scaling factor r can be small
such that the sacrificed voltage headroom (r VGS) is still acceptable for low voltage
applications. The resistors R1, R1′, R2 and R2′ are implemented off-chip in this demo
design in order to make r easily configurable. In the on-chip solution, the resistors need
to be laid out carefully for the best matching. Simulation results in AMI 0.5 µm process
show that a 4 dB higher loop gain is obtained with r being 12% at 60 °C and 1.1 V
supply, as shown in Fig. 4.6. To fully demonstrate the advantage of the gain boosting,
42
Texas Tech University, Li Lu, May 2013
simulation has been performed in IBM 180nm CMOS process, where the Monte-Carlo
process variation and mismatch models are available. The scaling factor r was swept
from 0 to 0.5 and the loop gain and minimum supply voltage of the subbandgap reference
circuit were plotted as shown in Fig. 4.7. The loop gain increases with the scaling factor
with a trade-off of the minimum supply voltage. The reference output spread due to the
global process spreads and local device mismatches was also simulated. The standard
deviation (STD) of the output spread divided by the mean value (relative STD) decreases
due to the gain boosting. Besides, the supply sensitivity of the subbandgap circuit
improves as the loop gain increases.
LoopGain(dB)
Loop
Gain (dB)
80
60 4dB
40
The bulk-driven amplifier
The gate-bulk-driven amplifier
20
0 0
10
2
10
Frequency
(Hz)
Frequency(Hz)
10
4
Supply
Sensitivity
(ppm/V)
Relative
STD
Minimum
supply
voltage (V)
Loop gain (dB)
Fig. 4.6. Simulated loop gains of a semi-folded-cascode bulk-driven amplifier and the
proposed gate-bulk-driven realization.
0.68
4000
70
0.04
0.64
2000
-0.1
65
0.03
-0.1
-0.1
-0.1
Minimum supply voltage (V)
Relative STD
Supply sensitivity (ppm/V)
5600
0.67
75
4.9%
73
Loop gain (dB)
6000
75
0.66
0.05
Loop gain (dB)
0.64
70
2300
65650
0.1
00
00
0.1
0.1
0.1
0.1
0.2
0.3
Gain0.2
boosting factor
0.3
0.2
0.3
Scaling
factor
r
Gain
boosting
factor
0.2
0.3
0.2
Gain
boosting0.3
factor
0.4
0.53%
0.6
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.6
0.6
0.6
Fig. 4.7. Simulated loop gain, minimum
supply voltage,
Gain boosting
boosting
factor relative STD of the output spread
Gain
factor
and the supply sensitivity of the subbandgap reference as a function of the scaling factor
r.
43
Texas Tech University, Li Lu, May 2013
I(μA)
15
B
A
M3
(I)
0
V (V)
0
B
(II)
MS4 MS5
A
0.8
I(μA)
40
MS2 MS3
I1
B
A
RS
A
Startup
0
V (V)
0
MS1
0.8
M1
Fig. 4.8 The simulated I-V curves of the two diode branches in the reference core (I) w/o
the parallel resistors R1, R1′ R2 and R2′, and (II) w/ the parallel resistors R1, R1′ R2 and
R2′. The adopted startup circuit is presented on the right hand side.
In the subbandgap reference core, the resistors R1 (R1′) and R2 (R2′) make the I-V
relationships of the two diode-branches more linear and the operating points less-defined
compared with the traditional bandgap structure without these parallel resistors [17]. Fig.
4.8 includes the simulated I-V curves of the two diode-branches without (I) and with (II)
the parallel resistors. At low voltage, the linear devices R1 (R1′) and R2 (R2′) dominate the
currents and the I-V curves of the two diode branches become near-linear and can be very
close to each other. A large amount of start-up current is desired to pull the circuit out of
the “near-linear” region to avoid a metastable operating point due to process variation
and mismatch. Therefore, a start-up circuit as shown in Fig. 4.8 has been implemented to
inject large amount of current during start-up to both the diode branches and kick off the
circuit. After reaching a proper operating point, the gates of MS4 and MS5 are pulled to
VDD and the start-up circuit is turned off. Observing that mismatch of the MS4 and MS5
pair can cause offset between the injected currents and thus could lead the circuit to a
metastable operating point, large gate length and common-centroid layout were utilized
on MS4 and MS5.
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Texas Tech University, Li Lu, May 2013
4.2.2. Experimental results
The reference generator was fabricated in AMI 0.5 µm CMOS process with a
typical N-/P-type threshold voltage of around 0.8 V and 0.9 V at room temperature,
respectively. The fabricated chip and the test setup are shown in Fig. 4.9. The packaged
chip was mounted on a printed circuit board and placed in an aluminum box, which
serves as a thermal mass to stabilize the temperature. The box was placed in an
environment chamber (ESPEC ECT-2) that controled the temperature during
measurement. The reference voltage was recorded by a Keithley 2001 digital multimeter.
A 100 ohm platinum resistance temperature detector (RTD 100) with a ±0.5 0C accuracy
was used to provide the reference temperature during testing.
150μm X 530μm
Environment
Chamber ESPEC
ECT-2
Thermal Testing
mass Board
793.43mV
Keithley
2001
Fig. 4.9.Chip microphotograph and test setup.
The chamber was first set at room temperature and the spread of the reference
output with different scaling factors r were measured from 18 samples as shown in Fig.
4.10. The spread of the reference output decreases as the scaling factor r increases. The
output spread (1 σ) reduced from 34 mV to 16 mV with r increaseing from 0% to 12%
while the mean values are in the same scale. An r of 18% further reduces the output
spread to 13.7 mV. The output error reduction indicates the effectiveness of the amplifier
gain boosting mechanism. Another benefit of the gain boosting design is the line
sensitivity improvement as shown in Fig. 4.11, which is reasonable since the supply
rejection ratio can be improved by increasing the gain of the amplifier. The minimum
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Texas Tech University, Li Lu, May 2013
supply voltages at room temperature with different scaling factor r are also reported in
Fig. 4.11, which suggests that the sacrificed voltage headroom for the gain boosting
Number of SamplesNumber
Number of
of Samples
SamplesNumber of Samples
mechanism is small and acceptable for low voltage applications.
r = 0%
Mean = 0.743V
Sd = 34.3mV
4
2
0
0.68
0.7
0.72
0.74
0.76
0.78
0.8
0.82
Reference Voltage (V)
r = 12%
Mean = 0.723V
Sd = 16mV
0.68
0.7
0.72
0.74
0.76
0.78
0.8
0.82
Reference Voltage (V)
r = 18%
Mean = 0.717V
Sd = 13.7mV
0.68
0.7
0.72
0.74
0.76
0.78
Reference
Voltage
(V)
Reference Voltage (V)
4
2
0
4
2
0
0.8
0.82
Output
(V) (V)
Reference
Voltage
Fig. 4.10. Measured reference output spreads at room temperature from 18 samples.
0.8
0.75
0.7
r=0%; Vdd_min=0.97V; LineSens=3040ppm/V
r=12%; Vdd_min=1.01V; LineSens=1820ppm/V
r=18%; Vdd_min=1.03V; LineSens=880ppm/V
0.65
0.6
1
1.5
2
2.5
Supply Voltage
(V)
Vdd (V)
Fig. 4.11. Measured line sensitivities at room temperature.
46
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Texas Tech University, Li Lu, May 2013
Reference
Voltage(V)
(V)
Reference Voltage
(a)
Vref Voltage
(mV)
Reference
(V)
(b)
1
-55 oC, r=12%, 490ppm/V
25 oC, r=12%, 1820ppm/V
125 oC, r=12%, 4050ppm/V
0.5
0
1
r = 0%, 35ppm/oC
0.75
1.5
2
SupplyVDD
Voltage
(V) (V)
r = 12%, 34ppm/oC
2.5
3
r = 18%, 34ppm/C
0.74
0.73
0.72
0.71
-50
0
50
100
Temperature
(oC)
Temperature
(C)
Fig. 4.12. Measured line sensitivities with r = 12% (a) and temperature sensitivities with
1.15 V supply voltage (b).
The chamber measurements show that the minimum supply voltages of the
reference generator from -55 °C to 125 °C are 1V, 1.1 V and 1.14 V for r being 0%, 12%
and 18% respectively. It should be noted that the supply voltage can be further scaled
with process technologies. For example, simulation shows that the same design has a
minimum supply voltage of around 0.45 V in UMC 130 nm process. Fig. 4.12 (a)
presents the line sensitivities from a random sample at -55°C , 25°C and 125°C with r =
12 %. The measured line sensitivities at the three temperatures were 490 ppm/V, 1820
ppm/V and 4050 ppm/V respectively over 1.1~3 V supply. Fig. 4.12 (b) shows the
outputs from this random sample as a function of tempearture with a 1.15V supply
voltage, and the temperature sensitivities were measured as 35 ppm/°C (r = 0%) and 34
ppm/°C (r = 12% and r = 18%). The 1σ output spreads for r being 0%, 12% and 18% are
36.7 mV, 18.3 mV and 15 mV respectively at -55 °C; 34.3 mV, 16 mV and 13.7 mV
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Texas Tech University, Li Lu, May 2013
respectively at 25 °C ; 37 mV, 16.7 mV and 14 mV respectively at 125 °C. The
effectiveness of gain boosting has thus been demonstrated over the millitary temperature
range. The current consumption of the reference generator was less than 68 uA for 1.1~3
V supply over the military temperature range. Most of the current was consumed by R1
(R1’) and R2 (R2’).
4.2.3. Conclusion
Experimental results demonstrated the effectiveness of the proposed gain-boosted
error correction amplifier. Compared with the previous subbandgap reference voltage
generator, this design realized an improved part-to-part accuracy and supply sensitivity
while maintaining the low voltage operation.
4.3.
A subthreshold MOSFETs-based PTAT voltage generator with
mismatch error correction techniques
4.3.1. Theory and design details
As introduced in Chapter 2 as well as the subbandgap reference designs,
subthreshold MOSFETs can be used for low voltage PTAT voltage generators. Bulkdriven amplifier can be adopted to further reduce the supply voltage. However, as in the
subbandgap reference voltage generator, device mismatches induce significant error.
Specifically, device mismatches exist in the MOSFET diodes, the current mirror and the
op-amp and can modify the PTAT voltage ΔVGS as:
VGS   n
kT
ln  N     VOS
q
(4.4)
where Δ is introduced by the local mismatch in the diodes and the current mirror
and VOS is the input referred offset voltage of the op-amp. In order to minimize the
mismatch errors, dynamic element matching (DEM) and dynamic offset cancellation
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Texas Tech University, Li Lu, May 2013
(DOC) can be implemented. Fig. 4.13 shows the schematic of the PTAT voltage
generator. Specifically, the positions of the devices such as the subthreshold MOSFETs
and the current mirror are exchanged periodically so that the mismatch error can be
averaged out. The DOC swaps the polarity of the op-amp so that the offset error can be
averaged out.
M4
M3
Vb
DEM2

DOC
M6 M7

VPTAT
R1
DEM1
M
M
M
M
To Op-amp Output
R2
The Bulk-Driven Error
Correction Amplifier
Robust
DEM&DOC
Start-up Clock Control
Fig. 4.13. Block diagram of the individual PTAT generator.
Since the switches in the DEM are stacked in the PTAT voltage generator, the onresistance of the CMOS switches should be as small as possible. The analog voltages to
be passed by the switches can be around VDD/2, where it is hard to completely turn on the
switches if the supply voltage is lower than VTH-N+VTH-P. As a result, a clock boosting
technique is adopted in order to accommodate the low supply voltage design requirement.
The clock boosting circuit used in this design is shown in Fig. 4.14. When the clock feeds
in, the NMOS pair charges the two capacitors until the voltage across the capacitors
almost reach VDD. Then the high voltage level of the output clock is lifted by the voltage
across the capacitors and can be about twice of the input clock amplitude. The simulated
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Texas Tech University, Li Lu, May 2013
boosted clock vs. the input clock is also plotted in Fig. 4.14. With the boosted clock and a
supply voltage of 1 V, the gate voltage of the switches is about 2 V and the VGS reaches
larger than 1.2 V in this design, which turns on the switches completely, so that the
voltage drop on the switch is negligible.
CLK
CLK_Boosted
22
Voltage(V)
Voltage
(V)
CLK_Boosted
1.5
11
0.5
CLK
00
0
10
20
10
20
CLK Boosting
Time
(mS)
Time(ms)
Fig. 4.14. The clock boosting circuit used in this design and simulation result.
4.3.2. Simulation and experimental results
10% Diode MS, Av=644mV
10% Curr. Mirr. MS, Av=624mV
10% Op-amp Input MS, Av=643mV
10% All the Three MS, Av=626mV
Output
(V)
Output (V)
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
CLK_SG115
20
25
30
35
30
35
Time (mS)
CLK_SG2
CLK_SG3
15
20
25
Time (mS)
Fig. 4.15. Simulated PTAT voltage when various mismatches (MS) exist. The
corresponding average output (Av) level is marked in the legend.
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Texas Tech University, Li Lu, May 2013
Simulation has been performed in order to verify the efficiency of the error
correction techniques DEM and DOC. Fig. 4.15 plots the simulated PTAT voltage with
various mismatches in the circuits at 600C and 1.1V VDD in 0.5 µm process. It is shown
that, without DEM and DOC, the errors in the PTAT voltage due to 10% mismatches can
be as large as hundreds of millivolts, while the averaged PTAT voltage with DEM and
DOC techniques has an error of only around 20 mV (marked in the legend of Fig. 4.15).
Therefore, the error in the averaged PTAT voltage can be significantly reduced. The
clock control block was carefully designed so that the clock frequency of SG1 is twice of
SG2 (SG2’) and 4 times of SG3, as shown in Fig. 4.15.
Clock Control and
Clock Boosting
470μm X 370μm
PTAT Core
380μm X 230μm
Angilent
oscilloscope
MOS9254A
Environment
Chamber ESPEC
ECT-2
VPTAT
Thermal Testing
mass Board
Vref
BNC
Cables
793.43mV
Keithley 2001
Fig. 4.16. Chip microphotograph and test setup.
The design was fabricated in AMI 0.5 µm process with a typical N-/P-type
threshold voltage of around 0.7 V and 0.9 V at room temperature, respectively. The
fabricated chip and the test setup are shown in Fig. 4.16. The packaged chip was mounted
on a printed circuit board and plcaed in an aluminum box, which serves as a thermal mass
to stabilize the temperature. The box was placed in an environment chamber (ESPEC
ECT-2) that controled the temperature. The generated PTAT voltage was recorded by a
mixed signal oscilloscope (Angilent MOS9254A).
The measured minimum supply voltage of the PTAT voltage generator over -55
0
C to 125 0C was 1 V, which also suggests that the clock boosting mechanism functions
as expected. Fig. 4.17 (a) shows the recorded transient signal of the PTAT voltage at
different temperatures with a supply voltage of 1.05 V. Each state in the transient PTAT
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Texas Tech University, Li Lu, May 2013
waveform represents a particular mismatch status. Mismatch and offset can cause a large
error in the PTAT voltage and the measurement results show that this error can be as
large as 100mV. However, the DEM and DOC minimized the errors in the averaged
output (the averaging was realized by a simple low pass filter). Fig. 4.17 (b) shows the
PTAT characteristic of the averaged output along with the outputs of different mismatch
status. The averaged current consumption of the PTAT voltage generator including both
the analog and the digital parts is measured as 17 uA over the 1~3 V supply range at
room temperature.
(a)
PTATVoltage
Voltage (V)
(V)
PTAT
0.8
0.8
1050C
0.6
0.6
650C
250C
0.4
0.4
-150C
0.2
0.2
0
0
0.1
0.1
0.2
0.3
0.2
0.3
Time (S)
-550C
0.5
0.5
0.4
0.4
Time (s)
(b)
PTAT Voltage
Voltage (V)
PTAT
(V)
0.8
0.8
Averaged PTAT voltage
0.6
0.6
0.4
0.4
0.2
0.2
-50
-50
Others: Some of the outputs
of the mismatch status
00
50
50
Temperature
(C)
Temperature (C)
100
100
Fig. 4.17. (a) Measured PTAT voltage generator output at different temperatures. (b) The
averaged PTAT voltage along with outputs of different mismatch status as a function of
temperature.
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Texas Tech University, Li Lu, May 2013
4.3.3. Conclusion
Subthreshold-MOSFETs based PTAT voltage generator has been developed. Low
voltage operation is achieved. Experimental results also demonstrated the effectiveness of
the implemented error correction techniques.
4.4.
An all-CMOS low voltage scattered thermal monitoring front-end
4.4.1. Circuit design details
As multi-core era arrives, multi-location hot-spots temperature monitoring is
becoming more and more important. Low voltage operation is always desirable.
Continued with the previous PTAT voltage generator, a scattered thermal monitor with
four sensor nodes distributed remotely is developed in this work. Instead of implementing
multiple individual PTAT voltage generators on the chip, only the sensing diodes are
distributed while the other parts are shared so as to save chip area as well as power
consumption.
A
M3 M4
SG1
SG1
SG1
SG1
M
SG3
SG2
Switches in the DEM
SG1
B
EN
A
A
A
M
M
M
SG2'
A
Scattered Sensor Nodes
B
EnableB
EnableB
Enable
R3
R3
R3
R3
M
M
M
M
M
M
M
M
M
M
M
M
SG2/3
B
EN
CLK_SG1
PTAT Core Driver
EN
Switches
in SG1
Fig. 4.18. Schematic of the scattered thermal monitor.
Fig. .18 shows the simplified schematic of the scattered thermal monitoring frontend. Compared with the individual PTAT voltage generator, where only two diodes are
driven by two currents, four sensing nodes are connected to the same PTAT core driver.
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Texas Tech University, Li Lu, May 2013
Each of the sensor nodes consists of a resistor R3, a DEM block and 4 identical diodeconnected N-MOSFETs, which can be synchronized in 1:3 ratio. As in the individual
PTAT voltage generator, DEM is applied to the current mirror and the diodes, and DOC
is implemented for the amplifier so that the mismatch induced error can be minimized.
The detailed implementation of the DEMs and DOC are included in Fig. 4.18. The sensor
nodes can be enabled/disabled by “EN” signals. In sleep mode, all the sensor nodes can
be disabled to save power.
Heating Resistor
Sens. Node #2
Centralized
PTAT Core
Clock
Generator
Angilent
oscilloscope
MOS9254A
Environment
Chamber
ESPEC ECT-2
Thermal
mass
Sens. Node #1
90μm X 70μm
VPTAT
PCB
BNC Cables
Vref
652.43mV
Sens. Node #3
Sens. Node #4
800μm
Keithley 2001
Fig. 4.19. Chip microphotograph and test setup.
4.4.2. Experimental results
The temperature sensor was fabricated in AMI 0.5 µm process with a typical N/P- type threshold voltage of around 0.8/0.9 V at room temperature, respectively. The
chip photograph and test setup are shown in Fig. 4.19. Four sensor nodes are distributed
at the chip corners and each of them occupies 90×70 µm2 area, which can be smaller in
advanced process technologies by reducing the switch sizes. A small resistor is
implemented beside node #1 for heating purpose. The chip was mounted on a testing
PCB and plcaed in a thermal mass aluminum box in an environment chamber that
controls the temperature. The generated PTAT and reference voltages were recorded by a
mixed signal oscilloscope and a digital multimeter, respectively.
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Texas Tech University, Li Lu, May 2013
(a)
PTAT
PTAT Output
Output (mV)
Sens. Node
#1 Enabled
Sens. Node
#2 Enabled
Sens. Node
#3 Enabled
Sens. Node
#4 Enabled
800
125oC
85oC
600
45oC
5oC
-35oC
400
200
CLK_SG10
0.1
0.2
0.3
0.4
0.5
0.3
Time (S)
0.4
0.5
Time (S)
CLK_SG2
CLK_SG3
(b)
Averaged
Averaged Output
Output (mV)
(mV)
0
0.1
0.2
800
SensNode#1
SensNode#2
SensNode#3
SensNode#4
700
600
500
400
300
-50
0
50
o
Temperature
C)
Temperature((C)
100
Fig. 4.20. (a) Measured PTAT voltage generator output at different temperatures. (b) The
averaged PTAT voltages vs. temperature.
The minimum supply voltage for the PTAT voltage generator was measured as 1
V over the military temperature range. The digital supply was 2.5 V. Clock boosting can
be further used to reduce the digital supply voltage as used in the individual PTAT
voltage generator. Fig. 4.20 (a) shows the recorded transient PTAT output voltages at
different temperatures with a 1 V supply voltage. The clock signals for DEM and DOC
are also shown. The four sensor nodes were enabled periodically. Fig. 4.20 (b) shows the
averaged output voltages vs. temperature, which exhibits acceptable PTAT linearity and
small spread across corners. The measured PTAT temperature coefficient is included in
Table 4.1. The current consumption was around 18 µA at room temperature when the
sensor nodes were enabled. The line sensitivity of the PTAT voltage generator was also
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Texas Tech University, Li Lu, May 2013
measured for 1~3 V supply voltage and listed in Table 4.1. Table 4.1 summarizes the
performance of the circuit.
Table 4.1. Performance summary of the front-end.
Process feature size
0.5 µm
Occupied die area
0.202 mm2
Sensor node size
6300 µm2
Minimum supply voltage
1V
Current at 25 °C
18 µA
Temperature range
-55 °C to 125 °C
PTAT line sensitivity #1/2/3/4 <0.8/0.7/0.8/0.7 °C/V
PTAT temperature coefficient 2.42±0.15 mV/°C
After the chamber measurements, the temperature was set as 20 °C and the
heating resistor was powered on to simulate the thermal behavior of VLSI chips. The
heating current was increased from 110 to 380 mA with a step size of 30 mA. The PTAT
outputs
were recorded and converted to temperature readings. Fig. 4.21 shows the
temperatures measured by the four sensor nodes. The temperature reading from sensor
node #1 increases more than those from the other sensor nodes as expected. The on-chip
temperature gradients were measured as around 1.2 °C /mm and 26 °C /mm with 110 mA
and 380 mA heatinging current respectively. In applications such as CPU thermal
management, once the system detects an overheat, clock throttling or power down will be
Temperature Reading
Temperature
Reading(C)(oC)
applied to the logic blocks in that area.
120
SensNode#1
SensNode#2
SensNode#3
SensNode#4
100
80
60
Heating
resistor
power off
110mA
heating
current
380mA
heating
current
40
20
2
4
6
8
Time
Index
Time Index
10
12
Fig. 4.21. Thermal monitoring behavior with uneven temperature changes.
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Texas Tech University, Li Lu, May 2013
4.4.3. Conclusion:
MOSFETs diodes are used in the temperature sensor front-end to achieve low
supply voltage. Error correction techniques including gain boosting, DEM and DOC have
been implemented to reduce offset and mismatch errors. The sensor nodes are distributed
across the chip to perform multi-location thermal monitoring.
4.5.
A Subthreshold-MOSFETs-Based Scattered Relative Temperature
Sensor Front-End with a Non-Calibrated ±2.5 0C 3σ Relative
Inaccuracy from -40 0C to 100 0C
4.5.1. Theory and design details
In relative temperature sensor for multi-location thermal monitoring, the sensing
devices are distributed at various hot spots while sharing the same bias current. The
relative accuracy (intra-chip) is more important than the absolute accuracy (inter-chip) to
optimize the load balancing among different cores in multi-core processers [1]. It should
be noted that, rather than global process spreads, the local mismatches between the
sensing devices dominate the relative accuracy in scattered temperature sensors.
Therefore, with proper mismatch-error correction techniques such as dynamic element
matching (DEM), reasonable relative accuracy becomes possible for scattered
temperature sensors based on subthreshold MOSFETs even though MOSFETs suffer
from larger local mismatch and process variation than BJTs [7]. In the previous multilocation thermal monitoring front-end, only four sensor nodes were implemented for
function verification. In this design, 25 remote sensor nodes are distributed so that
statistically significant data can be obtained and the relative inaccuracy can be evaluated.
Fig. 4.22 shows the block diagram of the proposed scattered relative temperature
sensor front-end. 25 sensor nodes are distributed remotely at different locations on the
chip, while the other parts including the error correction amplifier and the current mirror
are shared. The occupied area of the sensor nodes should be as small as possible because
the area close to hot spots is usually expensive. Besides, a smaller sensor node can be
deployed closer to the hot spot so that the measured temperatures are more reliable
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Texas Tech University, Li Lu, May 2013
provided that the temperature gradient can be large at the hot spots [1]. In order to
minimize the occupied area of the sensor nodes, the two subthreshold MOSFETs M 1 and
M2 have the same size, while the current mirror transistors M3 and M4 have a size ratio N
(N=3 in this work; M3 and M4 are the four unit transistor M in Fig. 4.22). The sensor
nodes contain only the two subthreshold MOSFETs and some switches for the DEM. For
each sensor node, three analog signals (two for the MOSFETs and one for the analog
ground) and five digital signals (two for CLK_DEM1, one for the digital supply, one for
the digital ground and one for the enable/disable) are routed to the control center.
M
M
A
M
K
K
K
M
B
C
O
O
O
D
M1
M1
M1
DEM2
E
F
G
I
K
H
DOC
K
L
R1
J
L
O
S2
S1' S2'
DEM1
S3
P
I
S4
S3' S4'
S5 S6 S7 S8
E
S5' S6' S7' S8'
F
DEM2
P
P
P
M2
M2
M2
DEM&DOC
Clock Control
I2C
Output Stage
DEM2 and DOC
Switches
EN
CLK_DEM1
A
B
C
D
L
Robust
Start-up
J
DOC
L
L
CLK_DEM2
CLK_DOC
G
H
S1
EN
EN
EN DEM1
DEM1
DEM1
Sensor
Node
Sensor
Node
Sensor
Node
PTAT Center
M5
M6
M8
M7
EN
DEM1 Switches
Fig. 4.22. Block diagram of the proposed relative temperature sensor front-end.
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Texas Tech University, Li Lu, May 2013
S1
S2
CLK_DEM1
S3
S4
CLK_DOC
S5
S6
S7
S8
CLK_DEM2
Fig. 4.23. Clock signals for DEM1, DOC and DEM2.
4.5.2. Error sources analysis
In the proposed scattered relative temperature sensor front-end, the relative
accuracy of the PTAT voltage ΔVGS among the sensor nodes is mainly decided by the
mismatches between the subthreshold MOSFETs. In order to minimize the relative
inaccuracy, similar to the test chip, DEM is applied to M1 and M2 so that the error due to
the mismatch can be averaged out. The remote sensor nodes are enabled/disabled by “EN”
signals, which are controlled by an I2C data interface. Detailed implementation of the
enable/disable is shown in Fig. 4.22. Specifically, during the enable phase, the
transmission gate (M5 and M6) is turned on and transistor M7 is turned off so that the
CLK_DEM1 signal controls M8 to perform the DEM function. During disable phase, the
transmission gate is turned off to isolate M8 from the CLK_DEM1 signal, while M7 pulls
the gate of M8 to ground to turn off the switch. Besides, DEM2 is implemented for the
current mirror and DOC is implemented for the error correction amplifier. Fig. 4.22
includes the detailed implementations of the DEMs and DOC. Fig. 4.23 shows the clock
timings for the DEMs and DOC. Similar to that in the test chip, DEM1 is clocked at half
the speed of the DOC and a quarter of the speed of DEM2 speed, so that all the mismatch
status can be exhausted and averaged.
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Texas Tech University, Li Lu, May 2013
Another error source of the sensor relative inaccuracy in this work comes from
the on-resistance of the switches in DEM1 as well as the parasitic resistance on the
routing traces connecting the PTAT center and the remote sensor nodes. These
“resistances” can vary among sensor nodes at different locations due to mismatches and
routing differences. Since the PTAT current is small due to the subthreshold operation of
the sensing diodes, the error due to the voltage drop on the routing traces can be
negligible in this work. The switches in DEM1 were carefully sized to avoid significant
on-resistance. Besides, the leakage current of the switches in DEM1 during the disable
phase may be significant enough at high temperature and thus harm the PTAT
characteristic of the output voltage. Therefore, the transistor size for these switches
cannot be too large. It should be noted that, if ΔVGS from M1 and M2 is measured by an
on-chip ADC with Kelvin sensing [7], the switch on-resistance and the routing trace
parasitic resistance do not contribute to the relative inaccuracy. Therefore, the tested
relative inaccuracy in this work should be considered conservative compared with a
complete system with on-chip ADC. Furthermore, the ground of the centralized parts and
the remote ground of the sensor nodes have been carefully routed to avoid error due to
the ground offset [34].
4.5.3. Experimental results
proposed scattered relative temperature sensor front-end was fabricated in AMI
0.5µm CMOS process. Fig. 4.24 shows the chip photograph and the chamber test setup.
The 5×5 sensor nodes are distributed at different locations and each node occupies an
area of 59×49 µm 2. It should be noted that the size of the sensor node is scalable with
process technology. The sensor nodes are located 200 µm apart from each other. The I2C
data interface is located to the left of the sensor node array, and all the other building
blocks including the PTAT center are at the upper left corner of the chip and occupy an
area of 0.11 mm2. Common-centroid layout was applied to the sensor nodes, the error
correction amplifier and current mirror in the PTAT center to reduce mismatch error. As
highlighted in red in the chip photo, some small resistors are deployed at different
locations on the chip to serve as heating sources for testing purpose.
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Texas Tech University, Li Lu, May 2013
Hot spots
5 X 5 Sensor node array
PTAT center, etc
560μm X 200μm
I2 C
220μm X 725μm
Environment
Chamber ESPEC
ECT-2
Thermal Testing
mass Board
59μm X 49μm
Angilent oscilloscope
MOS9254A
BNC
Cables
VPTAT
110.289 Ω
RTD 100
Keithley 2001
Fig. 4.24. Chip photograph and test setup. The red dots represent the hot spots realized by
heating resistors for testing purpose.
The chip was packaged in a 52-pin thin quad flat package (TQFP). The packaged
chip was mounted on printed circuit boards and plcaed in an aluminum box, which serves
as a thermal mass to stabilize the temperature. The box was placed in an environmental
chamber (ESPEC ECT-2) that controlled the testing temperature. A 100 ohm platinum
resistance temperature detector (RTD 100) with a ±0.5 0C accuracy was used to provide
the reference temperature during testing. The platinum resistance of the RTD 100 was
monitored by a digital multimeter (Keithley 2001). The output voltages were recorded by
a mixed signal oscilloscope (Agilent MOS9254A).
The minimum supply voltage for the scattered sensor front-end was measured as 1
V over -40-100 0C. The voltage at one input of the error correction amplifier, which is a
VGS of the subthreshold MOSFET, was measured at 1-3 V supply voltage to evaluate the
line sensitivity. Fig. 4.25 shows that the measured line sensitivities at -40 0C, 20 0C and
100 0C were 2.8 0C/V, 1.4 0C/V and 3.5 0C/V respectively.
61
1
1
1
0.8
0.4
0.4
0.2
0.2
0.8
VGS (V)
0
0.5
1
Texas Tech University, Li Lu, May 2013
0.6
0.6
0.6
1
1.5
0.75
0.4
0
-40 C
C
-40
0.2
data2
0
data3
0.5
1
1.5
2
2.5
0.65
-40 C
data2
100 0C
data3
-40 C
25 0C
data2
data3
1.5
2
3
0.7
2
-40 0C: 2.8 0C/V
2.5
3
2.5
3
25 0C: 1.4 0C/V
100 0C: 3.5 0C/V
1
1.5
2
Supply voltage (V)
2.5
3
Fig. 4.25. Measured line sensitivities at different temperatures.
0.65
PTAT outputs (V)
0
0.5
0.8
0.8
0.6
0.55
0.5
0.45
-40
-20
0
20
40
Temperature (0C)
60
80
100
Fig. 4.26. Measured PTAT outputs vs. chamber temperature for the twenty-five sensor
nodes. The PTAT outputs have been low-pass filtered.
The PTAT outputs for all the twenty-five sensor nodes over -40 0C to 100 0C were
recorded and went through a low pass filter so as to average out the mismatch errors as
shown in Fig. 4.26. The averaged PTAT outputs have a temperature sensitivity of about
1.6 mV/0C. and the spread of the PTAT outputs among the twenty-five sensor nodes was
used to evaluate the relative sensing accuracy. As shown in Fig. 4.27, the relative
inaccuracy (3σ) was less than ±2.5 0C over -40-100 0C. To the best of the authors’
knowledge, this is the first reported relative accuracy for on-chip temperature sensor
without any calibration. It should be noted that the tested inaccuracy is conservative due
to the on-resistance of the DEM1 switches and the routing trace parasitic resistance as
discussed in Section III. When on-chip ADC with Kelvin sensing is used, better relative
accuracy could be obtained. Table 4.2 summarizes the performance of the scattered
temperature sensor front-end.
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Texas Tech University, Li Lu, May 2013
3σ
Relative inaccuracy (0C)
2
1
0
-1
-2
-40
-20
0
20
40
Temperature (0C)
60
80
100
Fig. 4.27. Measured relative inaccuracy among the 25 sensor nodes.
Table 4.2. Performance summary of the proposed scattered relative temperature sensor
front-end in AMI 0.5 µm process
Process technology
Occupied size of a sensor
node
Number of sensor nodes
Minimum supply (analog)
Consumed current (at 20 0C)
Non-calibrated relative
inaccuracy
Temperature range
Supply voltage range
AMI 0.5 µm
59 × 49 µm2
25
1V
21 µA
±2.5 0C
-40-100 0C
1-3 V
2.8 0C/V @ -40 0C
1.4 0C/V @ 20 0C
3.5 0C/V @ 120 0C
1.6 mV/0C
Line sensitivities
Temperature sensitivity
After the chamber measurement, the testing board of the scattered temperature
sensor front-end was set up at room temperature and one of the heating resistors was
powered on. This creats an on-chip temperature gradient and simulates the thermal
behavior of multi-core digital processors when one of the cores is overloaded. The output
with each sensor node enabled was then recorded and mapped to temperature in celsus
degree in order to demonstrate the multi-location thermal monitoring capability. First, the
recorded output voltages were compensated with the relative error measured at an
arbitrary temperature. Then, the compensated output voltages were converted into
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Texas Tech University, Li Lu, May 2013
tempeartures based on the PTAT slope. This relative error compensation process deembeds the relative inaccuracy from the thermal map and thus provides more reliable onchip relative temperature information.
(a)
1
2
3
4
5
°C
(b)
°C
1
2
3
4
5
84
84
6
7
8
9
10
6
7
8
9
10
82
(c)
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
11
12
13
14
15
78
16
17
18
19
20
76
21
22
23
24
25
80
1
2
3
4
5
°C
84
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
22
23
24
(d)
82
80
78
76
°C
1
2
3
4
5
82
6
7
8
9
10
80
11
12
13
14
15
20
78
16
17
18
19
20
25
76
21
22
23
24
25
29
28
27
Fig. 4.28. Thermal maps of the chip during the heating experiments. (a)~ (c): The center
heating resistor was powered on. Relative error information at -40 0C, 20 0C and 100 0C
were used to compensate the thermal map in (a), (b) and (c) respectively. (d): The upper
right heating resistor was powered on.
Fig. 4.28 shows the generated thermal maps. Fig. 4.28 (a)~(c) show the thermal
maps when the heating resistor in the center was driven by a 300mA current. The relative
errors measured at -40 0C, 20 0C and 100 0C were used to compensate the measurement
results, and resulted in the thermal maps in Fig. 4.28 (a), (b) and (c) respectively. All the
three relative error compensations generated reasonable thermal maps showing the hot
spot is located at the center of the chip. The similarity of the three compensated thermal
maps indicates that a one-time error correction can be made at any temperature right after
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Texas Tech University, Li Lu, May 2013
a processor is power up, which significantly reduced the calibration cost.
The
temperatures on the right side of the chip are slightly higher than those on the left side.
This is due to the fact that there is extra die area dedicated to other building blocks on the
left side of the sensor array, while the right side of the sensor array is immediately
bounded by air, which has less thermal conductivity.
Fig. 4.28 (d) shows the measured thermal map when the heating resistor on the
upper right corner was powered on. The heating current was set to be small (110mA) to
explore the minimum temperature gradient that the relative temperature sensor can detect.
The relative error at room temperature was used to compensate the thermal map. A
temperature difference of 2.8 0C was measured from the upper right corner to the lower
left corner of the array, with a distance of 1.4 µm. This indicates that the on-chip relative
temperature sensor can detect a gradient as small as 2 0C/mm.
4.5.4. Conclusion
A subthreshold MOSFETs-based scattered relative temperature sensor front-end
with has been designed and characterized for low voltage multi-location thermal
monitoring. The use of subthreshold MOSFETs makes the supply voltage scalable with
CMOS process technology, which is beneficial to performance optimization of modern
digital processors. Bulk-driven error correction amplifier is adopted for low voltage
operation. Dynamic error correction techniques are used to minimize the error due to
device mismatches. The scattered relative temperature sensor was implemented in AMI
0.5µm CMOS process and the minimum supply voltage was measured as 1 V over -40100 0C. Error sources contributing to the relative inaccuracy have been analyzed and
minimized carefully. The sensor node occupies a small area and the measured 3σ relative
inaccuracy is less than ±2.5
0
C without calibration. The multi-location thermal
monitoring function has been demonstrated experimentally and a 2 0C/mm temperature
gradient was detected.
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Texas Tech University, Li Lu, May 2013
4.6.
A 0.45 V MOSFETs-based temperature sensor front-end in 90nm
CMOS with a non-calibrated ±3.5 0C 3σ relative inaccuracy from -55
0
C to 105 0C
4.6.1. Theory
Different from previous sensor front-ends, which are based on the error corrected
current mirror structure, this sensor front-end adopts a simple regulated current mirror
structure since a LDO regulator is usually available on chip. Fig. 4.29 shows the adopted
structure for the PTAT voltage/current generation in this work.
Regulator
M3
M4
I PTAT
M1
M2
R1
VGS
VPTAT
R2
Fig. 4.29. Simplified schematics of a PTAT voltage/current generator based on a
regulated current mirror structure.
MOSFETs M1 and M2 work in subthreshold region and have a size ratio of 1:N
(N=3 in this work), while M3 and M4 have the same size in this design. In subthreshold
region, the currents of M1 and M2 are decided by:
I D  2nCOXVT2 W L  exp VGS  VTH  nVT 
(28)
where n is the substrate factor in the EKV MOSFET model, μ is the carrier mobility, COX
is the gate-oxide capacitance per unit area, VT is the thermal voltage, W and L are the
channel width and length respectively, VGS is the gate-source voltage, and VTH is the
threshold voltage.
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Texas Tech University, Li Lu, May 2013
A simple single-ended amplifier and a regulator are used to reduce the channel
length modulation of M1 and optimize the line sensitivity. Ignore the body effect of M2,
the voltage ΔVGS over resistor R1 is given by:
VGS  n
kT
ln N
q
(29)
which is a PTAT voltage assuming n has negligible temperature coefficient [20]. The
currents are also PTAT and can be copied to the output for testing purpose.
As indicated in Eq. (2), the ΔVGS is insensitive to the device global process
spreads if n is insensitive to process variation. However, the local device mismatches can
introduce significant error and modify Eq. (2) as ΔVGS = nkT/qln(N+Δ), where Δ is
introduced by the local mismatches of the subthreshold MOSFETs and the current mirror.
Compared to a bandgap structure with an error-corrected amplifier as in the previous
design [35], the error due to the op-amp offset is avoided in the adopted structure.
Dynamic element matching (DEM) can be used to minimize the mismatch error Δ.
Specifically, the positions of the devices such as the subthreshold MOSFETs and the
current mirror are exchanged periodically so that the mismatch error can be averaged out.
4.6.2. Circuit design details
Fig. 4.30 shows the detailed block diagram of the proposed scattered relative
temperature sensor front-end with the sensing MOSFETs remotely distributed. In order to
reduce the channel length modulation on M1 (in Fig. 4.30, M1 is one of the unit transistor
M in the sensor node) and relax the PSRR requirement on the regulator, a simple
amplifier is added so that the drain voltage of M1 (VB) follows the VGS of M5 regardless of
the supply voltage to the first order [36]. The amplifier was implemented using NMOS
M5 as a common source amplifier driving a diode-connected PMOS load M6. A capacitor
C1 is added in parallel with the simple amplifier to avoid possible oscillation. Compared
with the bandgap-based structure in [35], a complicated error correction amplifier and the
corresponding offset error are avoided in this design. The start-up circuit functions as
follows: When the sensor front-end is off, the potential at node A (VA) is close to Vreg and
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Texas Tech University, Li Lu, May 2013
no current is in MS1, MS2 and RS. MS3 is thus turned on and pulls down VA so as to kick
off the sensor. Once the circuit is started up, the PTAT current will be copied to the large
resistor RS and make the VGS of MS3 close to zero so as to turn off MS3.
Start-up
PTAT Center
RS
MS3
MS4
M4
A
MS2
M
MM
M
MM
DEM2
C1
DEM1_B
DEM1
DEM1
R1
EN
Enable
Enable
B
G
DEM1_A
M5
S1 S2 S3 S4
S1' S2' S3' S4'
+
DEM1
Vreg
DEM
Control
Output
Stage
Switches in
DEM1_A
and DEM2
S5 S6 S5' S6'
DEM2
CLK_DEM1
-
CLK_DEM
2
Regulator
Vref
M
MM
GM
G
A
B
MS1
MM
M6
G
Sensor
Nodes
M3
EN
M5
M8
M6
M7
EN
Switches in DEM1_B
Fig. 4.30. Block diagram of the proposed relative temperature sensor front-end.
The regulator is a simple NMOS input differential pair structure with a second
stage PMOS current driver. With an input reference voltage of 0.35 V, the simulation
results in IBM 90nm process show that the loaded regulator has a loop gain of 50 dB,
phase margin of 63 degree and PSRR of 60 dB at the worst PVT corner (VDD = 0.45 V,
Temp. = -55 0C). Fig. 4.31 presents the simulated line sensitivity comparison between
three different versions of designs: the one without the simple amplifier and the regulator,
the one with the simple amplifier but without the regulator and the one with both the
amplifier and the regulator. The simple amplifier and the regulator improve the line
sensitivity significantly. A trade-off has been made between the line sensitivity
improvement and the increase of the minimum supply voltage due to the regulator dropout.
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Texas Tech University, Li Lu, May 2013
V
PTAT (V)
Output
(V)
0.8
0.8
w/o regulator, w/o simple amplifier
w/o regulator, w/ simple amplifier
w/ regulator, w/ simple amplifier
0.6
0.6
0.4
0.4
0.2
0.2
00
0
0.5
0.5
1.5
1
1.5
VDD
(V)
VDD (V)
Fig. 4.31. Simulated line sensitivities of three different versions of designs.
The sensor node contains only the subthreshold MOSFETs, R1 and some switches
for the DEM1_B and the enabling/disabling (EN). For each sensor node, six analog
signals (four for the MOSFETs, one for node G and one for the analog ground) and
eleven digital signals (eight for CLK_DEM1, one for the digital supply, one for the
digital ground and one for the enabling/disabling) are routed to the control center. The
occupied area of the sensor nodes should be as small as possible because the area close to
hot spots is usually expensive. Besides, a smaller sensor node can be deployed closer to
the hot spot so that the measured temperatures are more reliable provided that the
temperature gradient can be large at the hot spots [1].
S1
S2
S3
S4
CLK_DEM1
S5
S6
CLK_DEM2
Fig. 4.32. Clock signals for DEM1 and DEM2. The usage of clock signal for the error
correction chopping as in [35] has been avoided in this design.
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Texas Tech University, Li Lu, May 2013
4.6.3. Error sources analysis
As discussed previously, the relative accuracy of the PTAT voltage ΔVGS among
the sensor nodes is mainly decided by the mismatches between the subthreshold
MOSFETs. In order to minimize the relative inaccuracy, DEM (DEM1_A and DEM1_B
in Fig. 4.30) is applied to M1 and M2 in the sensor nodes so that the error due to device
mismatches can be averaged out. Specifically, M1 and M2 with a size ratio of 1:3 are
divided into 4 unit diodes (M is the sensor nodes) with identical size. DEM1 is controlled
by clocks with specific timing as shown in Fig. 4.32. The arrangement of the 4 unit
transistors is changed in a round robin fashion so that each unit transistor is connected to
the left branch exactly once per every 4 clock phases. DEM2 is implemented for the
current mirror in the PTAT center. Fig. 4.32 includes the clock timing for DEM2. DEM1
is clocked at half the speed of DEM2 speed, so that all the mismatch status can be
exhausted and averaged. Since the use of differential error correction amplifier has been
avoided, the dynamic offset cancellation (DOC) or chopping for the offset error
correction is not needed in this design, resulting in simpler clock control logic.
The sensor nodes can be disabled by controlling the “EN” signal and turning off
all the eight switches in DEM1_B [35]. Detailed implementation of the enable/disable is
shown in Fig. 430. The transmission gate (M5 and M6) either pass the DEM clock to
control the switch M8 or isolate the clock signal from M8, and M7 pulls the gate of M8 to
ground to turn it off during disabling.
It should be noted that, if ΔVGS is directly sampled by on-chip ADC with Kelvin
sensing, the local mismatch on R1 among the sensor nodes does not contribute to the
relative inaccuracy of ΔVGS. Therefore, this resistor local mismatch does not contribute to
the relative inaccuracy of the final temperature reading assuming that ΔVGS are sampled
directly over R1. However, the PTAT current does suffer from the local mismatch of R1,
which introduces additional inaccuracy to the tested PTAT voltage in this work.
Therefore, the tested relative inaccuracy in this work should be considered conservative
compared with a complete system with on-chip ADC. R1 could be centralized and shared
by all the sensor nodes in this design so as to eliminate the testing error due to resistor
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Texas Tech University, Li Lu, May 2013
local mismatch. However, the traces connecting the sensor nodes and the centralized
resistor can have different parasitic resistances and contribute to the relative inaccuracy.
Furthermore, the traces and contacts connecting the PTAT center and the sensor
nodes introduce parasitic resistances. These parasitic resistances together with the DEM
switches on-resistance can be another error source. In this work, these resistances are in
series with the large output impedances of the MOSFETs drain terminals and can be
neglected. Besides, the leakage current of the switches in DEM1_B during disabling may
be significant enough at high temperature so as to harm the PTAT characteristic of the
output voltage. Therefore, the switches in DEM1_B have been carefully sized to avoid
the significant on-resistance as well as large leakage current during disabling at high
temperature. Finally, the ground of the centralized parts and the remote ground of the
sensor nodes have been routed carefully to avoid error due to the ground offset [34].
4.6.4. Experimental results
SN #2
SN #1
46μm X 23μm
SN #3
SN #4
SN #6
SN #5 & PTAT
Center + Regulator
180μm X 150μm
SN #7
SN #8
Environment
Chamber ESPEC
ECT-2
Thermal Testing
mass
Board
RTD 100
SN #9
Fig. 4.33. Chip photograph and the chamber testing setup.
The proposed scattered relative temperature sensor front-end was fabricated in
IBM 90 nm CMOS process with a typical N-/P-type threshold voltage of around 0.26V
and 0.16 V at room temperature, respectively. Low threshold PMOS devices have been
used. Fig. 4.33 shows the chip potograph and the chamber test setup. The 3×3 sensor
nodes are distributed across the chip and each occupies an area of 46×23 µm2. The
packaged chips were mounted on printed circuit boards and plcaed in an aluminum box,
which serves as a thermal mass to stabilize the temperature. The box was placed in an
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Texas Tech University, Li Lu, May 2013
environment chamber (ESPEC ECT-2) that controled the testing temperature. A
calibrated 100 ohm platinum resistance temperature detector (RTD 100) was used to
provide the reference temperature during testing. The platinum resistance was monitored
by a digital multimeter (Keithley 2001). The generated PTAT voltages were recorded by
a mixed signal oscilloscope (Agilent MOS9254A).
The minimum analog supply voltage for the sensor front-end was measured as
0.45 V over -55-105 0C. The measured line sensitivities of the front-end with sensor node
#6 enabled were 0.28 0C/V (3100 ppm/V), 0.48 0C/V (2700 ppm/V) and 0.48 0C/V (1800
ppm/V) at -55, 25 and 105 0C respectively as shown in Fig. 4.34, which are well below
significance.
0.08
0.08
Output
PTAT Output
(V)
PTAT Output (V)Averaged
(V)
0.06
0.06
T=-55 0C
3100ppm/V or 0.28 0C/V
0.04
0.04
0.160.2
0.4
0.6
0.8
1
1.2
1.4
Supply Voltage (V)
0.14
0.14
T=25 0C
2700ppm/V or 0.48 0C/V
0.12
0.12
0.1
0.24
0.2
0.4
0.8
1
1.2
1.4
Supply Voltage (V)
0.22
0.22
T=105 0C
1800ppm/V or 0.48 0C/V
0.2
0.2
0.18
0.2
0.2
0.6
0.4
0.6
0.8
11
Supply Voltage (V)
Supply voltage (V)
1.2
1.4
1.4
Fig. 4.34. Measured line sensitivities at different temperatures with sensor node #6
enabled.
The recorded PTAT outputs for all the nine sensor nodes over -55 0C to 105 0C
were recorded and averaged (the averaging was realized by an off-chip low pass filter),
and the spread was used to evaluate the relative sensing accuracy. In order to increase
the sample size and obtain more reliable 3σ values of the relative errors, 3 chips have
been characterized and their relative inaccuracies without trimming are ploted in the same
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Texas Tech University, Li Lu, May 2013
figure as shown in Fig. 4.35 (a). The relative inaccuracy (3σ) was less than ±3.5 0C over 55-105 0C. It should be noted that the tested inaccuracy is conservative due to the local
mismatch of the resistor R1 in the sensor nodes as discussed in Section III. Fig. 4.35 (b)
shows the relative inaccuracy after one-point trimming at 25 0C and the 3σ relative
inaccuracy decreases to ±2 0C. In real application, this one-point trimming can be easily
realized in digital during an initialization phase of the measurement at arbitary
temperature. Table 4.3 summarizes the performance of the scattered temperature sensor
front-end.
(a)
Relative
(0C)
Relativeinaccuracy
Inaccuracy
(C)
44
3σ
22
00
-2
-2
(b)
Relative
(0C)
Relativeinaccuracy
Inaccuracy (C)
-4
-4
Average
-50
00
50
0
Temperature
C)
Temperature( (C)
100
100
-50
-50
0
50
0
50
0
Temperature
C)
Temperature ((C)
100
100
22
11
00
-1
-1
-2
-2
Fig. 4.35. (a) Measured relative inaccuracy among 27 sensor nodes from 3 chips. (b)
Relative inaccuracy after one-point digital trimming at 25 0C.
Table 4.3. Performance summary of the proposed scattered relative temperature sensor
front-end in IBM 90nm process
Process technology
Minimum supply
(analog)
IBM 90nm
0.45 V
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Texas Tech University, Li Lu, May 2013
Number of sensor
nodes
Non-trimmed relative
inaccuracy
Occupied size of a
sensor node
9
±3.5 0C
46 X 23 µm2
0.28 0C/V (3100 ppm/V) @-55 0C
0.48 0C/V (2700 ppm/V) @25 0C
0.48 0C/V (1800 ppm/V) @105 0C
Line sensitivity
Consumed current (at
25 0C)
Supply voltage range
Temperature range
32 µA
0.45-1.5V
-55-105 0C
After the chamber measurement, the testing board of the scattered temperature
sensor front-end was set up at room temperature and a soldering iron was placed on the
board close to the chip corner where sensor node #3 is located. This creats a temperature
gradient on the chip and simulate the thermal behavior of multi-core digital processors
when one of the core is overloaded. The soldering iron was heated to 300, 350 and 400 0F
respectively, and the output of each sensor node was recorded. The recorded outputs were
mapped to temperature in celsus degree and the relative error information at room
temperature were used to calibrate the map. Fig. 4.36 shows the thermal maps. The
values of the temperature readings are presented in Table 4.4. The measured on-chip
temperature gradients were around 2.2, 2.6 and 3.5 0C/mm for the three heating
temperatures, respectively.
(a)
0
C
3
6
2
5
1
9
8
4
7
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Texas Tech University, Li Lu, May 2013
(b)
0
C
3
6
2
9
5
1
8
4
7
(c)
0
C
3
6
2
9
5
1
8
4
7
Fig. 4.36. Thermal maps of the chip during the heating experiments when the soldering
iron is (a) 300 0F, (b) 350 0F and (c) 400 0F.
Table 4.4. Temperature reading of each sensor node
Sold. iron temp. (0F)
SN #1 temp.(0C)
SN #2 temp.(0C)
SN #3 temp.(0C)
SN #4 temp.(0C)
SN #5 temp.(0C)
SN #6 temp.(0C)
SN #7 temp.(0C)
SN #8 temp.(0C)
SN #9 temp.(0C)
75
300
68
70
72
68
70
71
67
69
69
350
74
76
78
73
75
77
72
74
76
400
87
89
93
85
89
91
85
87
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Texas Tech University, Li Lu, May 2013
4.6.5. Conclusion
A subthreshold MOSFETs-based scattered relative temperature sensor front-end
with low supply voltage operation has been designed and characterized for low voltage
multi-location thermal monitoring. Dynamic error correction techniques such as DEM are
used to minimize the error due to device mismatches. The error sources contributing to
the relative inaccuracy have been analysis and minimized carefully. The minimum supply
voltage in IBM 90 nm implementation was measured as 0.45 V over -55-105 0C. The line
sensitivity of the scattered sensor has been improved by adding a simple amplifier
consisting of two MOSFETs and powering by a simple 2-stage regulator. The sensor
node occupies a small area and the measured 3σ relative inaccuracy is less than ±3.5 0C
without any calibration. The multi-location thermal monitoring function has been
demonstrated experimentally and a 2.2 0C/mm temperature gradient was detected.
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CHPATER V
CONCLUSION AND FUTURE WORK
Low supply voltage temperature sensors with multi-location thermal monitoring
function are desired for the thermal/power management of modern multi-core digital
processers. Popular solutions of on-chip temperature sensors are reviewed and compared
in Chapter I. Novel low-voltage temperature sensor front-ends are proposed in this
dissertation. Specifically, MOSFETs working in subthreshold region, which need low
and process scalable supply voltage, are used to replace the BJTs in the bandgap structure
for temperature dependent signal and reference signal generation. Low voltage error
correction amplifiers are proposed to further reduce the supply voltage. Various error
correction techniques are implemented in the sensor front-ends to minimize the
mismatch-incudced errors. Six prototype designs are presented in Chapter IV, including
two reference signal generators, a PTAT signal generator, and three scattered relative
temperature sensors. The relative inaccuracy of the scattered temperature sensors were
evaluated and optimized and the multi-location thermal monitoring function was
demonstrated by experiments.
Further research works can be performed continued with this dissertation. The key
performances which are desired for the VLSI thermal management can be further
improved in the future works: low supply voltage, high accuracy, low power
consumption, etc. Several directions may be considered. First of all, Schottky barrier
diodes (SBDs) may be used as sensing device in order to achieve low operating voltage.
In [37], temperature characteristics of SBDs have been evaluated to investigate the
possibility of SBD serving in low voltage temperature sensing applications. The process
variation and device mismatch of SBDs need to be further characterized in order to
evaluate the accuracy performance of SBDs in temperature sensor applications. A second
direction is to further increase the relative accuracy of the scattered temperature sensors.
DEM has been used to minimized the diode mismatch, which is the major error source of
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the relative inaccuracy in a scattered temperature sensor. However, DEM cannot remove
the mismatch error completely due to the residue 2nd order mismatch error. A potential
solution to completely eliminate the diode mismatch is to adopte the current switching
mechanism [38], where only a single diode is used as sensing device while the driving
currents are switched. The PTAT voltage is therefore generated in time domain. Since the
PTAT voltage comes from the diode voltage difference of the same diode, no diode
mismatch error shall exist. This approach can improve the relative accuracy theoretically,
but more study should be performed on practical issues such as the time-domain PTAT
signal sampling. Another future direction is to reduce the power consumption of the
temperature sensor. The driving current for the sensing diodes is in the scale of a couple
of micro-Amp. Sub-micro-Amp driving current can be investigated in future. The other
power hungry blocks such as the error correction amplifiers and sigma-delta ADCs
should be re-designed in low power or replaced by other low power solutions. However,
the mismatch errors can increase due to the small current operation and the accuracy
performance of the sensor may degrade. Optimized balance between power consumption
and sensing accuracy may exist and can be explored in future.
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