Download Dynamic avalanche behavior of power MOSFETs and IGBTs under

Vol. 34, No. 3
Journal of Semiconductors
March 2013
Dynamic avalanche behavior of power MOSFETs and IGBTs under unclamped
inductive switching conditions
Lu Jiang(陆江), Tian Xiaoli(田晓丽), Lu Shuojin(卢烁今), Zhou Hongyu(周宏宇),
Zhu Yangjun(朱阳军), and Han Zhengsheng(韩郑生)Ž
Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
Abstract: The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped
inductive switching (UIS) conditions is measured. This measurement is to investigate and compare the dynamic
avalanche failure behavior of the power MOSFETs and the IGBT, which occur at different current conditions. The
UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs
is related to the parasitic bipolar transistor, which leads to the deterioration of the avalanche reliability of power
MOSFETs. However, the results of the IGBT show two different failure behaviors. At high current mode, the failure
behavior is similar to the power MOSFETs situation. But at low current mode, the main failure mechanism is related
to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement
with the experiment result.
Key words: UIS test; parasitic bipolar transistor; power MOSFETs; IGBT; parasitic thyristor
DOI: 10.1088/1674-4926/34/3/034002
EEACC: 2560P
to investigate the avalanche behavior of power MOSFETs and
an IGBT at different current conditions in detail.
1. Introduction
In recent years, saving energy and increasing energy efficiency have become important goals in power electronics systems. It has led to higher demands on the performances of
power semiconductor devices. Power MOSFETs and the insulated gate bipolar transistors (IGBTs) are the two most important power devices, which have been widely used in locomotive traction, industrial control, automotive electronics,
and consumer electronics. Generally, most of these devices are
applied as switch power supplies, and are used to drive unclamped inductive loads. It is required that the device is able
to dissipate all of the energy stored in the inductor loads during the switching process. Because most power devices are
the key component in such power supply systems, they must
have high avalanche ruggedness and a larger safe operating
area to withstand all possible extreme conditions that may occur during their lifetime. Thus, it is important to investigate
the avalanche failure mechanism of power MOSFETs and IGBTs, and find how avalanche behavior affects the device reliability over a wide current range. The unclamped inductive
switching (UIS) test is a routine method used to determine
the reliability of power devices. Lots of efforts have investigated the avalanche behavior of power MOSFETs or IGBTs
under UIS stress. Some researchers attempted to explain the
avalanche events of the power MOSFETs by experiment and
numerical simulationŒ1 3 . Others specifically focused on better understanding the ruggedness of the IGBT under avalanche
stressŒ4 6 . In real applications, a device may encounter various current conditions and it requires the device to have enough
ruggedness. However, very little experimental data is available
to compare the avalanche ability of power MOSFETs and IGBTs at different current conditions. The purpose of this study is
2. Device structure and experimental setup
2.1. Device structure
In order to compare the dynamic avalanche phenomenon
of different power devices under UIS conditions, two typical
commercial power devices are selected. The tested devices are
planar power MOSFETs with rated values (200 V, 18 A) and
planar IGBTs with rated values (1200 V, 25 A), which are manufactured by International Rectifier (IR) and Infineon, respectively. Figure 1 shows the cross-section view of one cell of the
device structure and its equivalent circuit for the power MOSFET and the IGBT, respectively.
The diffused structure of the power MOSFET in Fig. 1(a)
shows that the parasitic bipolar transistor is inherent in it. Here
the NC source acts as the emitter, the P-body as the base and the
N drift region as the collector. However, the IGBT structure
consists of four alternating semiconductor layers that contain
the coupled PNP and NPN transistors in Fig. 1(b). It introduces
a parasitic thyristor by using this sandwich structure. Generally,
when these parasitic components are activated under certain
circumstances, it leads to a detrimental effect.
2.2. Experimental setup
In previous work, the test circuit, which is called a single pulse UIS, was used to evaluate the avalanche behavior of
power MOSFETsŒ7 . However, it requires that the power supply voltage (VDD / in the test circuit is not over the device’s
maximum breakdown voltage and it may introduce error in the
special test condition. To optimize the single pulse UIS test cir-
† Corresponding author. Email: [email protected]
Received 21 August 2012, revised manuscript received 7 October 2012
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J. Semicond. 2013, 34(3)
Lu Jiang et al.
Fig. 1. Cross-sectional view and equivalent circuit of the different power devices. (a) The power MOSFET structure. (b) The IGBT structure.
Fig. 2. (a) UIS test circuit and (b) typical current and voltage waveforms of the DUT under UIS test.
cuit, an improved test method, which is called the decoupled
VDD voltage source method by international rectifier, is used to
analysis the UIS characteristic of the deviceŒ8 . In this study,
an ITC 55100 UIS load tester which satisfies the improved
method is used to measure the avalanche voltage and current
during the dynamic avalanche period. Figure 2(a) shows the
structure of the decoupled VDD voltage source test circuit used
for the experiment. It consists of a power supply voltage VDD ,
a pulse voltage generator, an inductance load L, a high speed
switch and the DUT. During the UIS test, the high speed switch
is switched on by the control circuit and the current continues to
flow through the inductance load to achieve the required drain
(collector) current. Once the desired current in the inductance
load is reached, the DUT is switched off immediately. The energy stored in the inductance is dissipated on the DUT during
the time period ta. The device will enter the dynamic avalanche
breakdown mode. The avalanche energy during the avalanche
mode can be obtained by:
1 2
LI ;
(1)
2 AS
where IAS is the peak avalanche current after the gate is turned
off, L is the value of the inductance load. The detailed derivation of this equation is given in Ref. [7]. It should be noted
V.BR/DSS
is omitted in Eq. (1)
that the adjustment coefficient V.BR/DSS
VDD
due to the fact that we use the decoupled VDD voltage source
method. Figure 2(b) gives the typical current and voltage waveforms for most power devices.
In order to identify the dynamic avalanche behavior of
the power MOSFET and the IGBT, the UIS test conditions
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Lu Jiang et al.
Fig. 3. Failed waveform of the power MOSFETs (a) at rated maximum current condition and (b) at low current condition.
were defined by VDD D 100 V and VGS D 12 V. According to
Eq. (1), we fixed the drain (collector) current and then the tester
increased the load inductance value automatically by every
0.1 mH per step until the DUT was destroyed. The drain (collector) current was set at two different current values to compare the device’s dynamic avalanche behavior. One of the currents was the device’s rated maximum current by its datasheet,
the other was set at 5 A, which is much lower than the device’s rated current. The measurement results were detected by
an ITC 55100 UIS load tester and the tester displayed the DUT
in “PASS” or “FAIL” status. In addition, the final destruction
current and voltage waveforms of the DUT were captured by
the tester.
3. Results and discussion
Figure 3 shows the captured failed waveform results of
power MOSFETs at different current conditions. As can be
seen from Fig. 3(a), the current curve reaches the device’s rated
maximum current (18 A) at the time 800 s and then the DUT
enters in the avalanche breakdown mode. The drain voltage of
DUT rises up for several microseconds due to the energy in the
inductance dissipating on the DUT. However, it can be seen
from the current waveform that the current continues to flow
in the DUT after the avalanche breakdown voltage disappears.
This implies that the DUT is still in the on state without the
gate voltage control. Figure 3(b) shows that the DUT enters
into avalanche breakdown mode at the low current condition
(5 A). As can be seen, the current waveform of Fig. 3(b) is
similar to the typical avalanche current waveform in Fig. 2(b).
But the tester detected that the DUT failed. By comparing the
failure waveform of power MOSFETs at different current, it
indicates that the failed behavior of the device always occurs
at the off state regardless of the current conditions. That means
the failure mechanism is similar for the power MOSFETs at different current conditions. In a previous workŒ7 , we have found
that the inner parasitic bipolar transistor of power MOSFETs
cause the destruction during the dynamic avalanche behavior.
The relationship of the local temperature and current density
was discussed in detail. It can be known that the positive feedback mechanism of the parasitic bipolar transistor leads to the
concentration of the total current as the inner temperature rises
on a few areas and causes the catastrophic device failure. The
parasitic bipolar transistor is the main influence on a power
MOSFET’s avalanche reliability.
Figure 4 shows the failed current and voltage waveform
of the tested IGBT, measured at rated maximum current condition (25 A) and low current condition (5 A). As can be
seen, the failed waveform at rated maximum current conditions (Fig. 4(a)) is similar with the power MOSFETs results
in Fig. 3(a). The current within the DUT continues to flow after the avalanche breakdown voltage disappears. This implies
that the parasitic bipolar transistor of the IGBT is activated by a
positive feedback mechanism and the current continues to flow
without the control of the gate. It is a similar failure mechanism
to the power MOSFETs we mentioned before.
However, an obviously different phenomenon is observed
when the IGBT is tested at low current conditions. As can be
seen from Fig. 4(b), collector–emitter voltage appears during
the current rising process and the appearance of the current
and voltage within the DUT simultaneously at nearly 10 ms.
Thus, huge power consumption is generated during this period. Moreover, it can be known from the device’s datasheet
that the single pulse transient resistance Z th is proportional
to pulse time. It implies that the device inner junction temperature increases quickly due to the influence of the enormous
power consumption and long pulse time without an effective
heat sink. McDonald et al.Œ8 explained in detail that the increase of the device’s inner junction temperature at the low current mode is apparently higher than the temperature at the high
current mode.
Furthermore, by comparing the device structure of the
power MOSFET and the IGBT, it can be known from the cross
section view in Fig. 2(a) that the IGBT contains the parasitic
thyristor, which is composed of NPN and PNP transistors. During the current increasing process, holes are injected from the
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Lu Jiang et al.
Fig. 4. Failed waveform of the IGBT (a) at rated maximum current condition and (b) at low current condition.
collector (PC / into the N-drift region. Some of the holes recombine with electrons coming from the gate channel. Other
holes flow along the P-body region laterally and are collected
by the emitter. This laterally flowing hole current develops a
voltage drop in the resistance region of the P-body. It tends to
forward bias the self-built potential of the NC P junction and, if
it large enough, the electrons will inject from the emitter into
the body region. It triggers the parasitic NPN transistor in activation mode and then both the NPN and the PNP parasitic
transistor are turned on. That causes the thyristor, which composed of these two parasitic transistors, to be in the on state.
It is the destruction effect in the IGBT that we call the latch
upŒ9 . Once in latch up, the gate cannot control the collector
current and the IGBT is destroyed by the excessive power dissipation. The maximum latch up current can be expressed by
the following equationŒ10 :
J D
Vbi
;
˛PNP;ON SP LNC p
(2)
where Vbi is the built-in potential of the NC P junction, and it
decreases with the temperature increasingŒ10 . ˛PNP;ON is the
current gain, which is proportional to the temperature due to
an increase in the lifetime. SP is the sheet resistance and is
the positive temperature coefficient. LNC is the P-body length
located below the NC emitter region. According to Eq. (2), the
latch up current density is reduced severely as the temperature
rises.
During the low current mode, the inner temperature of the
IGBT structure increases severely. This positive feedback effect leads to the parasitic thyristor in the on state and causes
catastrophic device failure. It indicates that the ability of the
IGBT to sustain avalanche energy at low current mode is
mainly influenced by the parasitic thyristor, which is in good
agreement with the experiment result in Fig. 4(b). Suppressing
it becomes a major concern in the device structural design and
application requirements. Some design considerations are used
to optimize the device structure, such as increasing the P-body
doping concentration with a high doping PC region, optimizing
the P-body cell layout, reducing the gate oxide thickness, and
so on. However, there is a dilemma in the design consideration.
When optimizing the device’s reliability, we need to be careful
not to sacrifice the device’s electrical performance. For example, the increase of the P-body doping concentration will affect the device threshold voltage. Achieving the best avalanche
performance and suitable electrical performance requires better device structural optimization, proper manufacture process
selection, and appropriate application design.
4. Conclusion
In this paper, the UIS experiment is used to investigate the
avalanche behavior of power MOSFETs and IGBTs at different current conditions. The goal of this research is to analyze
how the current variations affect the avalanche behavior of the
power MOSFETs and IGBTs. The UIS test results of the power
MOSFETs indicate that the main reason for device failure is related to the action of the parasitic NPN bipolar transistor. And
the IGBT also shows the similar reason at high current condition. However, the IGBT at low current conditions demonstrates a different failure behavior. It can be concluded that this
failure is affected by the parasitic thyristor as the inner temperature increases. The positive feedback effect will lead to the
parasitic thyristor being in the on state and causes catastrophic
device failure. Thus, according to the failure mechanism, some
optimized ways to suppress the parasitic component of the device is necessary. It can help to enhance the device’s sustained
avalanche capability through adjusting the device’s structural
design and manufacturing process.
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