Download APV25S0 - Calibration Circuit

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APV25S0 - Calibration Circuit
Author: Andrea Neviani
E-mail: [email protected], [email protected]
Version: 1.1 - July 19, 1999
Notes: This document contains the description of the calibration circuit integrated in the
APV25S0 chip.
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1. Scope
The calibration circuit is intended to be a system for on-chip testing and measurement of the
APV25S0 analog front-end impulse response. Basically, the circuit generates and injects current
pulses of programmable total charge into selected channel inputs. The time interval between the
stimulation and the point where the front-end response in sampled is programmable, both on a
coarse (25 ns) and a fine (25/8 = 3.125 ns) time scale. The sampled data are read out by the APSP
filter in peak detection mode, with a gain nominal value of 1. This allows the reconstruction of the
front-end impulse response shape.
The calibration procedure is triggered externally, and can be summarized in the following steps:
1. a calibration request is generated externally and placed on the TRIG line of the chip
2. the request is decoded and an internal signal is issued to the calibration circuit
3. after a time interval tc (fixed offset plus an additional delay, programmable in steps of 3.125
ns) the calibration circuit injects a programmable amount of charge into selected channels
4. the front-end generates a response which is sampled every 25 ns and stored in the pipeline
cells
5. trigger signals are generated externally and issued in sequence to mark all cells for APSP processing
6. step 3 to 6 are repeated for a total of 8 iterations, increasing the programmable delay from 0 to
21.875 ns in steps of 3.125 ns.
The amount of charge injected is programmable, nominally in the range between 0 and 25.5 fC (0
- 6.4 mips) in steps of 0.1 fC (0.025 mips), though large deviations from these figures should be
expected due to the poor accuracy of the M1-M2 parasitic capacitors used in the circuit (see section 2).
The 128 analog channels are grouped into 8, selectable, 16-channel sets. The stimulation is actually injected only in the selected sets. The channels belonging to a given set are separated by 7
channels belonging to different sets, to help minimize channel to channel interference effects.
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2. Circuit overview
The architecture of the APV25S0 calibration circuit is basically the same as that for the APV6
chip. A block diagram of the system is shown below.
edge
generators
clock
delay regulator
delay control bias voltage
mask register
variable
delay
line
delayed edge
trigger for edge
generation
calibration request
processor
delay line input
calibrate request signal
The system is made up of four functional blocks:
• variable delay line
• delay regulator
• calibration request processor
• calibration edge generators
The signal flow starts with the calibration request processor sending a falling edge to the variable
delay line in response to a calibration request signal. The delayed edge is picked up somewhere
between the 5th and the 12th stage of the variable delay line, and sent back to the calibration
request processor, which sends a trigger to the calibration edge generators. Finally, the calibration
edge generators convert the trigger into a voltage step of given amplitude, which, in turn, is converted to charge by the capacitor coupling the analog channels input to the edge generators. The
delay regulator generates a bias voltage which regulates the delay of the stages of the variable
delay line.
Here follows a descritpion of the functionality and circuit implementation of each block.
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2.1 Variable delay line
The function of this block is to delay a (digital) input signal by a programmable amount of time.
The delay can take 8 values in increments of 3.125 ns. The functionality is achieved by tapping a
16-stage delay line at anyone of the 8 central stages using selector switches. Each stage of the
delay line consists of a current-starved inverter in series with a Schmitt trigger. The current level
in the inverter is set by an nMOSFET and a pMOSFET acting as current sources, whose gate voltage is controlled by the delay regulator so as to keep the total delay through the line constant at
the desired value. The Schmitt trigger transforms the slow transition of the starved inverter output
into a sharp edge. Having the 8 stages actually used to selectively delay the signal in the middle
of a 16-stage line helps increase the uniformity and the accuracy of the delay increments. A block
diagram of the variable delay line and a schematic of the current-starved inverter and of the
Schmitt trigger is shown below.
delay control bias voltage
variable
delay
line
delayed edge
current-starved inverter
+
Schmitt trigger
VP
output to next
delay stage
in
Vdd
VN
delay
select
delayed edge
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2.2 Delay regulator
The function of the delay regulator is to generate the control voltages used to set the current in the
current-starved inverters, so as to keep the total delay across the 16-stage delay line constant at a
nominal value of 50 ns. This is achieved by a Delay-Locked-Loop (DLL) in which an exact copy
of the variable delay line is used to delay a periodic square wave (pulse), which is then compared
to a reference signal (strobe). A phase detector compares the falling edge of the reference and of
the delayed signal (delout), activating a charge pump for a period equal to the delay between the
two signals. The charge pump actually injects current into a storage capacitor if the delayed signal
is late with respect to the reference, while it sinks current if the signal is fast. A low-pass, RC loop
filter gets rid of unwanted high frequency components in the storage capacitor voltage, which is
then mirrored and used to control the current-starved inverters. At calibration start-up, or after a
reset, the voltage on the storage capacitor is initialized to VDD, in order to guarantee that initially
the delayed signal delout is faster than the reference. A block diagram of the delay regulator is
shown below.
40 MHz clock
strobe
up
sequencer
phase detector
pulse
delout
variable delay line
VP
VN
down
VP
mirrors
VN
loop filter
charge pump
clock
pulse
strobe
50 ns
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2.3 Calibration request processor
The function of this block is to process incoming calibration request signals, in response to which
a falling edge is sent to the variable delay line. Upon reception of the delayed edge, the processor
issues a trigger to the calibration edge generation. Alternating positive and negative triggers are
generated upon successive calibration requests, so that the front-end can be tested with inputs of
both polarities. The first trigger after a reset (or start-up) of the calibration circuit generates a negative charge input. Since the preamplifier is programmed to expect an input of given polarity, and
half of the calibration requests end up with an opposite polarity input, the corresponding front-end
response is meaningless and should be disregarded, or, as an alternative, the level 1 trigger signals
should not be issued in this phase.
A schematic diagram of the calibration request processor is shown below
B to the delay line
D
D
A
calibration
request
C
from the
delay line
A
B
C
D
Q
D
Q
Q
Q
reset
reset
calibration
trigger
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2.4 Calibration edge generators
The function of the calibration edge generators is to transform the trigger issued by the calibration
processor into a voltage step of programmable amplitude. Since the output of the each edge generator is AC coupled to the input of the analog channels, the voltage step ∆V causes a charge injection equal to Q=∆V CC in each channel, CC being the value of the coupling capacitance.
The calibration subsystem includes 8 edge generators, each driving 16 channels. In order to minimize interference, channels driven by different edge generators are interleaved, (edge generator 1
drives channel 0, 8, 16, ..., 120, edge generator 2 drives channel 1, 9, 17, ..., 121, and so on), so
that, when a single edge generator is active, the driven channels are separated by 7 undriven ones.
The conversion of the trigger into a voltage step is performed by a nMOSFET differential pair
with resistive loads RL, whose schematic diagram is shown below. The trigger signal (and its
complement) coming from the calibration processor, switch on one transitor and turn off the other
one in the differential pair, causing the bias current to switch from one branch to the other. When
the current is switched to the output branch, the output voltage commutes from VDD to VDDICALRL, stepping back to VDD when the current is switched to the other branch. The current
source transitor is biased by a programmable voltage, corresponding to a bias current ICAL ranging between 0 and 255 µA. This, combined with the nominal value of the load resistors (2.5 KΩ)
and of the coupling capacitors (40 fF), gives a voltage step ranging between 0 and 637.5 mV, in
steps of 2.5 mV, and an injected charge between 0 and 25.5 fC, in steps of 0.1 fC. Given the tolerances on the load resitors and coupling capacitors values, large deviations from these figures is to
be expected. Each generator can be turned off by switching off the current source transistor with
VDD
RL
RL
to channel
input
CC
calibration
trigger
(complement)
calibration
trigger
generator on
current source
transistor
programmable
bias
generator off
VSS
the corresponding switches.
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3. Operational procedures
Under normal operating conditions the calibration subsystem should be inhibited in order to prevent unnecessary noise generation by the delay regulator logic. The mode register (see section 4.5
of the APV25S0 user guide) bit 2 is used to inhibit (value = 0) or activate (value = 1) the calibration subsystem. When inhibited, the calibration internal reset is active and clock distribution to the
delay regulator logic is prevented. When active, the delay regulator is driven by the 40 MHz system clock and runs continuously, while the rest of the calibration subsystem is idle until a calibration request is issued. The APV25S0 general reset acts also on the calibration subsystem,
activating the internal reset which is distributed to all the flip-flops in the subsystem.
A double pulse, 11, on the TRIG line (see section 6.0 of the APV25S0 user guide for a full explanation of the TRIG line) starts a calibration cycle, whose features are controlled by four different
programmable parameters: the content of three registers sets the magnitude (charge) of the calibration pulse (calibrate edge generator current bias register), the fine grain delay (calibrate delay
select register), and which channels actually receive the test pulse (calibrate output mask register);
informations on how to program these registers can be found in section 4.9 of the APV25S0 user
guide. Finally, a proper combination of the trigger latency value (latency register - see section 4.6
of the APV25S0 user guide) and trigger pulse sequence should be selected in order to make sure
that the front-end response to the test pulse is sampled in a significant time interval. The diagram
shown below might help in making this concept clear.
clock
TRIG+
x
x
0
1
x
1
cal_req
req_in
td
req_back
cal_switch
shaper
output
x
x
x
x
x
x
When a 11 sequence is detected on the TRIG line, an internal calibration request (cal_req) is
generated, which is then inverted (req_in) and sent to the variable delay line. The returning
delayed signal (req_back) causes the calibration request processor to issue a trigger (cal_switch)
to the edge generators, which finally generate the test pulse. The polarity of a test pulse is negative
(the test charge is sucked out of the channel input node) in response to the first calibration request
after start-up or after a reset, and then alternates between positive and negative on the subsequent
calibration requests.
The delay td introduced by the variable delay line ranges nominally between 15.625 ns and 37.5
ns, depending on the value stored in the calibrate delay select register. This register can take 8 different values, shifting the shaper output pulse in steps of 3.125 ns with respect to the clock signal
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(and thus, to the sampling edges). In order to make sure that all samples in the desired time window are marked for output, the APV25S0 mode of operation (as defined in section 4.5 of the
APV25S0 user guide) should be multi-mode, and consecutive (i.e., 3 clock cycles apart - see section 6.2 of the APV25S0 user guide) trigger pulses should be issued on the TRIG line.