Download Excalibur Chip Set Controller

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D0
D1
D2
D3
D4
D5
D6
D7
V DD
GND
N/C
SHLDENA
PW M LR
PWM L L
PW M UR
PW M UL
N /C
N /C
N /C
A0
A1
A2
A3
A4
A5
A6
A7
V DD
V DD
G ND
G ND
A 14
A 15
R DN OT
W R N OT
573C L K
C L O CK
N /C
N /C
X CS B A R
SH L D-D RV
IS ET
LL
N/ C
LLSJ
O PA M PL L
LR
N/ C
L RS J
O PA M P L R
AV D D
AV D D
VSJ
A GN D
A GN D
UR
N/ C
U RS J
OPA M PU R
UL
N/ C
U LSJ
O PA M P UL
I DR I V E
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Excalibur Chip Set Controller
Developer’s Guide
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INT DONE
LEDCAT HODE
A SI CRST
uRESET
SY SRST
M ODCL K
CHARGE
N/C
V DD
GND
N/C
LLT P
LRT P
ULTP
URT P
PENOUT
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Features
Description
x Support for Capacitive and/or
The Excalibur chip set consists of an optimized
controller circuit that can be used with MicroTouch
capacitive or 5-wire resistive touchscreens. The
chip set is designed for maximum flexibility and ease
of implementation.
5-wire Resistive Touchscreens
x Lower System Cost
x Small Form Factor
x MicroTouch Proprietary Excalibur
ASIC (80 pin PQFP)
x Simple System Power Requirements
(5V @ 35 mA typical)
x Serial UART or PS/2 Interface
At the core of the chip set is the MicroTouch
Excalibur proprietary custom ASIC and the
microcontroller firmware. The ASIC contains the
latest technology used in MicroTouch touchscreen
controllers. The ASIC, together with an 80C32
microcontroller, a 64K OTP EPROM, a 2K-bit serial
EEPROM, and a few discrete components, form a
powerful and versatile touchscreen controller.
Multi-mode is an implementation method that lets
you switch the controller’s behavior from capacitive
to resistive simply by changing a few shorting-plugs.
You can also select serial or PS/2 communication
protocol via shorting-plugs.
With multi-mode, you can switch touchscreen
technologies and communication modes at will
without having to design multiple circuits and
manage the different SKUs.
This document includes full technical detail for the
Excalibur ASIC. It also provides implementation
schematics and a complete bill of materials for
capacitive, resistive, and multi-mode touchscreen
controllers.
Excalibur Chip Set Controller Developer’s Guide
Part Number: 19-221, Version 2.0
© 1997 MicroTouch Systems, Inc. All rights reserved.
Excalibur ASIC Chip Specifications
Table 1, Table 2, and Table 3 list the specifications for the Excalibur ASIC.
Table 1. Excalibur Absolute Maximum Ratings
Parameter
Rating
Storage temperature range
-65 to 150 qC
Operating free-air temperature
0 to 65 qC
Supply voltage, VDD, AVDD*
6.5V
Input voltage range*
-0.5 to +6.5V
Output current, IO
5 mA
Input current, II
5 mA
Continuous total power dissipation
TA ‰ 25qC Power Rating: 1 W
De-Rating Factor Above TA=25qC: 12 mW/qC
TA=65qC Power Rating: 520 mW
Case temperature for 40 seconds
225 qC
* All voltages are with respect to GND and AGND.
Table 2. Excalibur Recommended Operating Conditions (TA = 0 to 65qC)
Parameter
Rating
Supply voltage, VDD, AVDD
4.5 to 5.5V
Input rise or fall times (logic inputs)
500 ns maximum
Clock frequency
11.0592 MHz (MicroTouch recommends using
this frequency such that nominal baud-rate
frequencies are generated by the microcontroller.)
Excalibur Chip Set Controller • Developer’s Guide
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Table 3. Excalibur Electrical Characteristics (TA=25qC)
Parameter
Rating
Minimum high level input voltage, VIH (logic inputs)
VDD & AVDD = 4.5V to 5.5V
3.5V
Maximum low level input voltage, VIL (logic inputs)
VDD & AVDD = 4.5V to 5.5V
0.8V
Maximum input Leakage high, IINH
VDD & AVDD = 5.5V
r1 PA
Maximum input Leakage low, IINL
VDD & AVDD = 5.5V
r1 PA
Maximum input Leakage low, IINL (logic inputs w/ pull-ups)
VDD & AVDD = 5.5V
5 to 35 PA
Typical total supply current, ICC
VDD & AVDD = 5.5V
5 mA
Maximum total supply current, ICC
VDD & AVDD = 5.5V
8 mA
System Power Requirements for Complete Chip Set
Table 4. System Power Requirements for Complete Chip Set
Parameter
Rating
Vcc
5V r 10%, ripple and noise < 50 mVpp (peak-to-peak)
Icc
35 mA typical, 60 mA maximum
Excalibur Chip Set Controller • Developer’s Guide
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Excalibur Pin Definitions
D0
D1
D2
D3
D4
D5
D6
D7
V DD
GND
N/C
SHL DENA
PW M L R
PWM L L
PWM UR
PWM UL
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79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
Figure 1 shows the layout of the pins on the Excalibur ASIC. Table 5 lists the name, type, and
description of each pin.
N /C
N /C
N /C
A0
A1
A2
A3
A4
A5
A6
A7
V DD
V DD
GN D
GN D
A 14
A 15
R D N OT
W R N OT
573C L K
C L OC K
N /C
N /C
X C SB A R
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41
I NTDONE
L EDCATHODE
A SI CRST
uRESET
SY SRST
M ODCL K
CHARGE
N/C
V DD
GND
N/C
L LTP
L RTP
ULTP
URTP
PENOUT
SH L D -D RV
ISET
LL
N /C
L L SJ
OPA M PL L
LR
N /C
L R SJ
OPA M PL R
AV D D
AV D D
V SJ
A GN D
A GN D
UR
N /C
U R SJ
OPA M PU R
UL
N /C
U L SJ
OPA M PU L
ID R IV E
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Figure 1. Excalibur Pinout
Excalibur Chip Set Controller • Developer’s Guide
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Table 5. Excalibur Pin Definitions
Pin
Name
Type
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
N/C
N/C
N/C
A0
A1
A2
A3
A4
A5
A6
A7
VDD
VDD
GND
GND
A14
A15
RDNOT
WRNOT
573CLK
CLOCK
N/C
N/C
XCSBAR
INTDONE
LEDCATHODE
ASICRST
uRESET
N/C
N/C
N/C
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Gnd
Gnd
Input
Input
Input
Input
Input
Input
N/C
N/C
Output
Output
Output
Input
Output
29
30
31
32
33
34
35
36
37
38
39
40
SYSRST
MODCLK
CHARGE
N/C
VDD
GND
N/C
LLTP
LRTP
ULTP
URTP
PENOUT
Input (Schmitt)
Output
Output
N/C
Power
Gnd
N/C
Output
Output
Output
Output
Output
No connection
No connection
No connection
EPROM lower order address bit A0
EPROM lower order address bit A1
EPROM lower order address bit A2
EPROM lower order address bit A3
EPROM lower order address bit A4
EPROM lower order address bit A5
EPROM lower order address bit A6
EPROM lower order address bit A7
Digital power
Digital power
Digital ground
Digital ground
Address bit A14
Address bit A15
Registers Read control (active low)
Registers Write control (active low)
Lower order address-byte latch control
Master clock (11.0592 MHz)
No connection
No connection
No connection
A/D integration status (active low)
LED drive output
Resets ASIC registers and FFs (active high)
Output of the ASIC’s internal Power on Reset
(POR) circuit OR’d with SYSRST (active high)
Chip set Master Reset (active low)
No connection
Sensor operating frequency
No connection
Digital power
Digital ground
No connection
No connection
No connection
No connection
No connection
No connection
Excalibur Chip Set Controller • Developer’s Guide
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Pin
Name
Type
Description
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80
IDRIVE
OPAMPUL
ULSJ
N/C
UL
OPAMPUR
URSJ
N/C
UR
AGND
AGND
VSJ
AVDD
AVDD
OPAMPLR
LRSJ
N/C
LR
OPAMPLL
LLSJ
N/C
LL
ISET
SHLD-DRV
PWMUL
PWMUR
PWMLL
PWMLR
SHLDENA
N/C
GND
VDD
D7
D6
D5
D4
D3
D2
D1
D0
Output
Output
Input
N/C
Output
Output
Input
N/C
Output
Agnd
Agnd
Output
Power
Power
Output
Input
N/C
Output
Output
Input
N/C
Output
Input
Output
Output
Output
Output
Output
Input
N/C
Gnd
Power
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Resistive screen drive output
Upper-left amplifier output
Upper-left amplifier input
No connection
Upper-left sensor drive
Upper-right amplifier output
Upper-right amplifier input
No connection
Upper-right sensor drive
Analog ground
Analog ground
Voltage reference output
Analog power
Analog power
Lower-right amplifier output
Lower-right amplifier input
No connection
Lower-right sensor drive
Lower-left amplifier output
Lower-left amplifier input
No connection
Lower-left sensor drive
Bias reference input, sets transfer f(x) gain
Shield amplifier output
No connection
No connection
No connection
No connection
No connection
No connection
Digital ground
Digital power
Data bus signal D7
Data bus signal D6
Data bus signal D5
Data bus signal D4
Data bus signal D3
Data bus signal D2
Data bus signal D1
Data bus signal D0
Excalibur Chip Set Controller • Developer’s Guide
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Mechanical Specifications for Excalibur 80 Pin PQFP
The package style for the Excalibur ASIC is an 80 pin PQFP (plastic quad flat pack).
Table 6. Dimensions of the Excalibur 80 Pin PQFP
Symbol
Tolerance (mm)
Dimension (mm)
A
3.40 maximum
A1
0.25 minimum
A2
r0.10
2.70
D
r 0.25
23.20
D1
r 0.10
20.00
E
r 0.25
17.20
E1
r 0.10
14.00
L
+.15/-0.10
0.88 (L is measured at gage plane at 0.25 above the
seating plane.)
B
r 0.05
0.35
c
0.17 maximum
G
0.20 radius minimum
e
0.80 nominal
J
0.30 radius minimum
Eq
0q – 7q
Excalibur Chip Set Controller • Developer’s Guide
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Resistive Versus Capacitive Sensor Operation
The Excalibur ASIC is designed to operate analog capacitive or 5-wire resistive touchscreens with
a minimum of difference in the overall chip set design. The main difference is the firmware used
to program U4, the program ROM. From a circuit implementation point of view, the only
remaining difference is how the fifth wire of the sensor is driven.
MicroTouch determines touch position by measuring currents in the four corners of the
touchscreen, regardless of sensor technology.
x For capacitive operation, a fifth connection is made to the back of the sensor (backshield),
typically connected to ground to provide noise immunity from the display device.
x For resistive operation, a fifth connection is made to the conductive top sheet connecting
it to a current source.
For sensors with cable NovRAM, the electrical difference of the capacitive/resistive fifth wire is
incorporated within the sensor harness. Therefore, you only need to select the firmware to
implement either resistive or capacitive mode of operation.
For sensors without cable NovRAM, you can easily implement the fifth wire electrical difference
into the chip set circuit if multi-mode operation is desired.
Firmware Programming
MicroTouch provides the firmware as binary hexadecimal files contained on the Excalibur ASIC
Controller Firmware diskette (Part Number: 9310000). This diskette provides four versions of
firmware that vary based on the touchscreen technology (capacitive or resistive) and the
communication mode. Refer to “Serial Versus PS/2 Communication Modes” later in this
document for more details.
x You must program the appropriate file(s) into individual 64K x 8 pages of a ROM device.
Table 7 lists the available firmware files. For multi-mode applications, shorting-plugs on
the upper address lines of the ROM can select the appropriate firmware.
x The file is in Intel hexadecimal format.
x All unused ROM bytes must be filled with FFH.
Excalibur Chip Set Controller • Developer’s Guide
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Serial Versus PS/2 Communication Modes
The Excalibur chip set design supports either serial communication or PS/2 communication. You
can enable the communication mode (as well as capacitive versus resistive operation ) by selecting
the appropriate firmware. Table 7 shows the four firmware files included on the Excalibur ASIC
Controller Firmware diskette (Part Number: 9310000).
Table 7. Firmware Available for the Excalibur Chip Set
Touchscreen Technology
Communication Mode
Firmware Part Number
Capacitive
Serial communication
9208900
Capacitive
PS/2 communication
9208710
Resistive
Serial communication
9208940
Resistive
PS/2 communication
9209100
You must be sure to use the appropriate set of I/O communication pins for the communication
mode selected.
x For serial communication, use DATA-IN and DATA-OUT.
x For PS/2 communication, use PS2-CLK and PS2-DATA.
For multi-mode applications, shorting-plugs could also be used to select the I/O communication
pins.
Touchscreen Interface
x For sensors with cable NovRAM, the J1 connector, the ferrite beads (L1 – L4), the ESD
protection diodes (D1 – D5, D7, D8), and the resistors (R4 – R6) provide the touchscreen
interface to the Excalibur ASIC. Refer to Figure 3.
x For sensors without cable NovRAM, the J1 connector, the ferrite beads (L1 – L4), and the
ESD protection diodes (D1 – D5) provide the touchscreen interface to the Excalibur
ASIC. SP3, R2, and R3 provide CRT turn-on HV discharge for resistive mode and shield
termination for capacitive mode. Refer to Figure 5.
The four ferrites attenuate any RF pickup from the touchscreen. The ESD diodes clamp
excessive voltage generated by an ESD disturbance and direct the currents to low impedance
nodes. Be sure the EVDD and EGND connection to these diodes is short and direct using good
PCB layout techniques. (Refer to “PCB Layout Considerations” later in this document for more
information).
Excalibur Chip Set Controller • Developer’s Guide
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Microcontroller and Program Memory
U2 and U4 are the 80C32 microcontroller and program ROM respectively.
The 80C32 microcontroller is a member of the standard Intel 8051 style 8-bit CMOS
microcontroller family. The 80C32 contains 256 bytes of RAM and includes a full serial UART
interface. (The address/data bus of the 80C32 is multiplexed and applications using this
microcontroller typically require an address demultiplexer circuit that latches the lower 8 bits of
the address bus during a program fetch. The function of the demultiplexer circuit is built into the
Excalibur ASIC.)
The 80C32 requires an external ROM or OTP (one time programmable) EPROM. MicroTouch
supplies the firmware for the ROM as part of the Excalibur chip set package. It is available as a
binary hexadecimal file, which is compatible with most PROM programmers.
The MicroTouch firmware controls all aspects of the hardware operation and provides for
stand-alone touchscreen functionality. Touch position is automatically detected, calculated, and
output serially at user selected baud rates. The firmware command set is extensive. Refer to the
MicroTouch Touch Controllers Reference Guide for information on each command.
Non-Volatile Storage
A number of controller parameters, such as baud rate and other settings, are stored in the chip
set’s non-volatile EEPROM U3 (NovRAM). This allows all operating defaults to be maintained
even after power has been removed. This 93C46 device features a 3-wire serial interface to the
microcontroller.
A similar NovRAM resides in MicroTouch sensor cables with NovRAM, which contains
manufacturing information, calibration data, and identification of sensor type. The ESD
protection diodes (D1 – D3) and the resistors (R4 – R6) provide the communications interface
with the sensor cable NovRAM. Refer to Figure 3.
Chip Set System Reset
From the host system point of view, the touchscreen controller can be hardware reset using the
active low signal denoted in the schematics as SYSTEMRESET.
When SYSTEMRESET is asserted active low, the touch controller is in hard reset. A hard reset
means that the entire chip set (Excalibur and 80C32 microcontroller) is brought to an idle state
with no clock, logic, or processor activity.
When SYSTEMRESET is de-asserted, Excalibur pin 28, uRESET, switches low which enables
the 80C32 microcontroller to boot up (the 80C32 requires an active high RESET). During the
boot-up sequence, the 80C32 performs several self diagnostics. If the self diagnostics pass, the
80C32 will set its pin 16 low, ASICRESET, in order to enable full Excalibur operation.
NOTE: Do not confuse this process with the action of the software “Reset”
command. A software reset does not alter the hardware operation. Instead, a
soft reset performs a logical update on the controller’s local information about
the touchscreen environment. (Refer to the Touch Controllers Reference Guide
for a description of the Reset command.)
Excalibur Chip Set Controller • Developer’s Guide
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Excalibur ASIC Function
The Excalibur ASIC contains the touchscreen sensor interface logic, A/D converter, LED drive,
and microcontroller interface. Its main function is to digitize the four unknown currents from the
touchscreen corner nodes. The microcontroller establishes ASIC operating behavior at boot-up
by writing internal registers used to control analog function and digital timing. It also establishes
the operating frequencies and interactively nulls analog errors.
Under command from the microcontroller, the ASIC will start to integrate the four currents and
proceed to do so for a preset length of time. When finished, the ASIC will set INTDONE low,
interrupting the microcontroller. The microcontroller will then read the four digitized corner
currents from the ASIC and issue another integration start. This process continues indefinitely.
For capacitive operation, the ASIC actively operates the sensor in order to detect touch
capacitance, which is digitized as a proportional current. For resistive, it passively waits for a
touch to provide D.C. current to its digitizers.
Design Considerations
Although the chip set only requires one physical +5V supply, it is advantageous to use the three
separate connections, VDD, AVDD, and EVDD, as shown on the schematics and Sample PCB
Layout. This helps minimize digital noise from being coupled into the A/D converter within
Excalibur, as well as any ESD currents.
Likewise, there are three separate ground connections: GND, AGND, and EGND. You should
connect these three grounds directly to split ground planes.
The only external components necessary for proper operation of the Excalibur ASIC are as
follows:
x Capacitors C7, C8, and C9 are decoupling capacitors for the digital supply voltage VDD.
x C3 and C17 are decouplers for the analog AVDD supply.
x C16 is a decoupling capacitor for the reference voltage VSJ. This capacitor is connected
between the VSJ pin and AVDD.
x R1 sets the internal gain of the ASIC.
x Capacitors C12 – C15 are used for the internal A/D converter. These ceramic capacitors
require a quality dielectric. MicroTouch recommends X7R.
x The optional LED provides a number of diagnostic functions such as power-on self-test
results, touch indication, and any error conditions that occur. The LED is controlled by an
internal current source providing 4 to 5 mA for LED drive.
Excalibur Chip Set Controller • Developer’s Guide
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PCB Layout Considerations
The layout of the Excalibur chip set is straightforward. The general layout suggestions listed
below should insure maximum performance from the Excalibur chip set implementation. Refer to
Figure 2 for a sample PCB layout.
1. Maintain separate power planes, VDD, AVDD, and EVDD, connecting them together at
the source of the +5V (ideally at the power supply or connector where the voltage
originates.) Maintain separate ground planes, GND, AGND, and EGND, connecting them
together at the source of circuit ground (ideally at the power supply or connector where
ground originates).
2. Place touchscreen connector J1 and all ESD components in zone E, over the EVDD and
EGND planes.
3. Place the four ferrite beads, L1 – L4, such that they bridge zones E and A.
4. Place op-amps, U5 and U6, and associated capacitors, C10 – C15, in zone A. Maintain
PCB trace separation of each op-amp’s two unique nets from the others. For example,
do not route U5A pins 1 and 2 nets near U5B pins 6 and 7 nets. Place C12 – C15 as close
as possible to their respective op-amps minimizing PCB trace length. Place U5 and U6 as
close as possible to U1, minimizing PCB trace length.
5. Place U1 (Excalibur ASIC) such that it bridges zones A and D as shown in Figure 2. This
places the analog portion of Excalibur over the AGND and AVDD planes, and the digital
portion over the GND and VDD planes.
6. Place digital circuits, U2, U3, U4, and their support discrete components in zone D.
7. Route touchscreen connections UL, UR, LL, and LR with a minimum spacing of 25 mil
between these four nets and any other net on the board, as well as keeping etch lengths to
a minimum. Route them from J1 to the ESD components, then to the ASIC. These steps
will help insure that ESD pulses are clamped by the protection diodes and not coupled into
other circuitry.
8. Locate all decoupling capacitors as close as possible to their respective power pins.
Layer A
EVDD
Layer B
EGND
Layer A
AVDD
L1
L2
Layer B
AGND
L3
L4
E
A
41
ASIC
64
Layer A
VDD
Layer B
GND
D
Connections to System
+5V and ground
Figure 2. Sample PCB Layout
Excalibur Chip Set Controller • Developer’s Guide
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Testing Considerations
In most cases, the Excalibur chip set circuit is implemented as part of an overall embedded system
or PCB assembly. Together with the fact that most applications are using custom software to
communicate with the controller, testing the controller operation at either the manufacturing level
or operational level is an issue that you should address before the controller PCB design is
complete.
You should incorporate the following suggested list of test points into the PCB layout to provide
easy access. Table 8 represents a set of test points that should be sufficient to validate correct
operation of the Excalibur ASIC and firmware in general. These test points let you monitor
internal signals that you can use for indicating normal operation during ATE or for debugging
purposes. For many cases of in-circuit testing it will be advantageous for you to provide
additional circuitry, where appropriate, for isolation of the different integrated circuits. The best
manufacturing strategy is usually determined by the overall testing strategy used by the overall
system PCB.
Table 8 does not include obvious signals such as supply voltages, crystal clocks, or
communication signals as these are left up to you to incorporate if appropriate.
Table 8. Test Points
Pin Name
and Number
Description
Normal Resistive
Operation
Normal Capacitive
Operation
UL
Pin 45
Upper-left sensor drive
2.5V, r0.2V
Square wave, 2.5 to 5V
~40kHz
UR
Pin 49
Upper-right sensor drive
2.5V, r0.2V
Square wave, 2.5 to 5V
~40kHz
LL
Pin 62
Lower-left sensor drive
2.5V, r0.2V
Square wave, 2.5 to 5V
~40kHz
LR
Pin 58
Lower-right sensor drive
2.5V, r0.2V
Square wave, 2.5 to 5V
~40kHz
CHARGE
Pin 31
Sensor operating frequency
CMOS square wave
~40kHz
CMOS square wave
~40kHz
VSJ
Pin 52
Voltage reference output
2.5V, r0.2V
2.5V, r0.2V
INTDONE
Pin 25
A/D integration status
CMOS square wave
CMOS square wave
~200Hz, 80% duty cycle ~200Hz, ~80% duty cycle
NOTE: You can use the test point labeled TP1 “PWRUP DEFAULTS” to
restore factory defaults. An active low applied during the reset sequence will
restore all factory defaults including communication parameters. Using the test
point is useful if you cannot send the “Restore Defaults” (<CTRL>A RD)
firmware command.
Excalibur Chip Set Controller • Developer’s Guide
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Testing Considerations for Software
If the embedded system is not compatible with MicroTouch utility programs, such as Microcal
(MS-DOS based), you must provide some generic ability to talk/listen to the chip set using a
terminal program, via an external serial port.
For example, you can provide an external RS-232 interface at the DATA-IN and DATA-OUT
signals of the chip set. If you do, you must also provide a way to disable your system’s transmit
pin in order to prevent signal contention on DATA-IN. This RS-232 interface will allow you to
send diagnostic commands and observe the resulting reception of diagnostic feedback from the
controller using a dumb terminal. Some diagnostic capabilities include touch calibration and
verification functions.
Excalibur Chip Set Controller • Developer’s Guide
14
Bill of Materials (BOMs) and Schematics
The schematics (refer to Figure 3 – Figure 6) show typical implementations of the chip set
controller for capacitive and resistive touchscreen applications. You can modify the basic
schematic to include RS-232 level translation for serial communication, or voltage pre-regulation
as required by the available voltages in the host system.
Table 9 lists the bill of materials for the schematics shown in Figure 3 and Figure 4.
Table 9. Bill of Materials for Capacitive and Resistive Touchscreens with Cable NovRAM
Item
Quantity
Part Description
Reference Designators
1
2
22pF 10% COG 25V
C1 C2
2
1
6.8uF 10V Tantalum
C3
3
6
0.01uF X7R 25V
C12 C13 C14 C15 C16 C17
4
6
0.1uF X7R 25V
C4 C5 C6 C7 C8 C9 C10 C11
5
7
MMBD7000 dual diodes
D1 D2 D3 D4 D5 D7 D8
6
1
LED @5 mA (optional)
D6
7
1
Molex 10-88-1121 (2x6, .1C)
J1
8
4
Murata BLM21A102SPT
Fair-Rite 2508051027
L1 L2 L3 L4
9
1
82.5K 1% 1/10W
R1 (R2 and R3 are not used.)
10
3
100 5% 1/10W
R4 R5 R6
11
2
Shorting-plugs (optional)
SP1 SP2 (Shorting-plugs, SP1 SP2, are
required to implement multi-mode
applications.)
12
1
93C46 EEPROM
U4
13
1
80C32 ROMLESS uP
U2
14
1
Excalibur*
(MicroTouch P/N 19-550)
U1*
15
1
27C020 150 ns
U4 (MicroTouch supplies the firmware.
For single and dual-mode applications,
a 27C512 and 27C010 may be used,
respectively.)
16
2
Motorola MC33072/MC34072
U5, U6
17
1
11.0592 MHz
Y1
* All components except the Excalibur ASIC are non-proprietary.
Excalibur Chip Set Controller • Developer’s Guide
15
1
2
3
4
5
6
Revision History
NOVCE
NOVDATA
NOVCLK
RD
WR
ROMCLK
ASICRESET
CLOCK
A15
A14
SYSTEMRESET
Signals from Page 2
D
BiDirectional Signals
to/from Page 2
Description
D
C7
C15
.1uF
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
C
A0
A1
A2
A3
A4
A5
A6
A7
VDD
Sensor Connector
Molex 10-88-1121
C8
2
1
MMBD7000
NOVCLK
3
1
2
MMBD7000
NOVCE
3
2
1
MMBD7000
NOVDATA
3
D3
3
TP5
TP6
100
2
1
MMBD7000
3
D4
AVDD
8
.01uF
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
R1
LL
LRSJ
2
VSJ
3
U6A
1
82.5K 1%
LLSJ
OPAMPLL
LR
C16
LRSJ
OPAMPLR
.01uF
OPAMPLR
C10
.1uF
MC33072
C
C13
C3
6.8uF
10V
C17
.01uF
URSJ
6
VSJ
5
.01uF
U5B
7
UR
URSJ
OPAMPUR
UL
OPAMPUR
MC33072
C12
ULSJ
OPAMPUL
SENSE
.01uF
AVDD
ULSJ
2
VSJ
3
U5A
1
OPAMPUL
C11
.1uF
MC33072
4
2
R6
C14
VSJ
SHLD-DRV
ISET
LL
N/C
LLSJ
OPAMPLL
LR
N/C
LRSJ
OPAMPLR
AVDD
AVDD
VSJ
AGND
AGND
UR
N/C
URSJ
OPAMPUR
UL
N/C
ULSJ
OPAMPUL
IDRIVE
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
100
B
N/C
N/C
N/C
A0
A1
A2
A3
A4
A5
A6
A7
VDD
VDD
GND
GND
A14
A15
RDNOT
WRNOT
573CLK
CLOCK
N/C
N/C
XCSBAR
1
D2
R5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
L3
Ferrite
L4
Ferrite
10
12
INTDONE
100
TP3
INTDONE
LEDCATHODE
ASICRST
uRESET
SYSRST
MODCLK
CHARGE
N/C
VDD
GND
N/C
LLTP
LRTP
ULTP
URTP
PENOUT
D1
.1uF
A14
A15
RD
WR
ROMCLK
CLOCK
EVDD
R4
OPAMPLL
MC33072
4
ADDRESS[7:0]
Standard MicroTouch NovRAM sensor pin-out shown.
7
U6B
AVDD
Earth ground symbol represents a unique
low impedance path from the ESD
protection circuits to the ground entry
point of the PCB, ideally earth referenced.
4
5
U1
Power and Analog ground are connected
together only at the power-entry point of
the TouchScreen Controller circuit area
on the PCB.
J1
6
VSJ
8
AVDD
+5VDC
GND
LLSJ
.01uF
7
VDD, AVDD, and EVDD are connected
together only at the power-entry point
of the TouchScreen Controller circuit
area on the PCB.
D0
D1
D2
D3
D4
D5
D6
D7
VDD
GND
N/C
SHLDENA
PWMLR
PWMLL
PWMUR
PWMUL
VDD
Approved
VDD
DATA[7:0]
LR
B
EXCALIBUR
19-550
C9
ASICRESET
uRESET
SYSTEMRESET
EVDD
Power Connections
Date
with cable NovRAM
DATA[7:0]
DATA[7:0]
Rev. ECO
Excalibur Connections
D0
D1
D2
D3
D4
D5
D6
D7
NOVCE
NOVDATA
NOVCLK
RD
WR
ROMCLK
ASICRESET
CLOCK
A15
A14
SYSTEMRESET
uRESET
INTDONE
ADDRESS[7:0]
.1uF
TP2
uRESET
INTDONE
ADDRESS[7:0]
Signals to Page 2
VDD
LL
3
D6
TP4
2
TP8
D5
MMBD7000
1
D7
MMBD7000
2
3
TP7
PC110
L1
Ferrite
L2
Ferrite
11
9
2
This document and the data
disclosed herein or within is
not to be reproduced, used
or disclosed in whole or part
to anyone without the written
permission of MicroTouch.
1
D8
8
Date
Approved
Date
Excalibur Chip Set Schematic
Approved
Date
Capacitive and Resistive with cable NovRAM
Approved
Date
Approved
Date
MMBD7000
Printed
1
Date
Checked
UR
6
5
Drawn
UL
3
A
MicroTouch Systems, Inc.
300 Griffin Park
Methuen, MA 01844
1
2
3
29-Oct-1997
4
at
11:05:51
Title
Size
A
Doc. Number
B
Rev.
19-221
Template bsht1.dot
FileName C:\AAA\PROTEL\CHIPSETX\MULTIS3.SCH
5
2.0
Sheet
1
of
2
6
Figure 3. Excalibur Chip Set Schematic for Capacitive and Resistive Touchscreens with Cable NovRAM (Sheet 1 of 2)
Excalibur Chip Set Controller • Developer’s Guide
16
1
2
3
D
NOVCE
NOVDATA
NOVCLK
SYSTEMRESET
RD
WR
ROMCLK
ASIC RESET
CLOCK
A15
A14
PS2 communications are enabled via specific firmware
PS2-CLK
PS2-DATA
To Host
DATA-OUT
DATA-OUT
DATA[7:0]
Signals to Page 1
DATA[7:0]
BiDirectional Signals
to/from Page 1
VDD
C
C8
MultiMode Implementation
SP2
SP1
1
1
2
2
PSEN
22
24
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CE
OE
Vpp
U2
VCC
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
D0
D1
D2
D3
D4
D5
D6
D7
PGM
NC
13
14
15
17
18
19
20
21
26
16
27C020PLCC32
3
D0
D1
D2
D3
D4
D5
D6
D7
43
42
41
40
39
38
37
36
A8
A9
A10
A11
A12
A13
A14
A15
24
25
26
27
28
29
30
31
RD
WR
PSEN
ROMCLK
DATA-OUT
DATA-IN
19
18
32
33
13
11
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
X1
X2
RSVD
RSVD
RESET
RSVD
RSVD
INT0
INT1
T0
T1
A8
A9
A10
A11
A12
A13
A14
A15
RD
WR
PSEN
ALE/P
TXD
RXD
EA/VP
P1.0/T2
P1.1/T2X
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Y1
11.0592 MHz
35
21
CLOCKIN
20
12
34
10
23
1
14
15
16
17
uRESET
PS2-DATA
INT DONE
ASIC RESET
C2
C1
22pF
22pF
TP1
PWRUP DEFAULTS
2
3
4
5
6
7
8
9
VDD
B
U3
PS2-CLK
4
3
2
1
DO
DI
CLK
CE
NOVDATA
NOVCLK
NOVCE
22
80C32PLCC
VDD
Shorting Plug
D0
D1
D2
D3
D4
D5
D6
D7
31
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
.1uF
44
1
.1uF
U4
B
C
C6
32
Signals from Page 1
VDD
uRESET
INTDONE
ADDRESS[7:0]
uRESET
INTDONE
ADDRESS[7:0]
VCC
PS2-CLK
PS2-DATA
D
NOVCE
NOVDATA
NOVCLK
SYSTEMRESET
RD
WR
ROMCLK
ASICRESET
CLOCK
A15
A14
GND
BiDirectionals
6
with cable NovRAM
SYSTEMRESET
DATA-IN
SYSTEMRESET
DATA-IN
5
Microprocessor Connections
Host CPU Connections
From Host
4
VCC
NC
NC
GND
8
7
6
5
C9
.1uF
93C46
Shorting Plug
3
Stake Pins (6)
LSB
MSB
MultiMode implementation: Page EPROM U4
via MSB address lines A16 and A17, in this
or similar fashion, choosing one of four
operating modes: Serial Resistive or
Capacitive; PS2 Resistive or Capacitive.
A
Title
Excalibur Chip Set Schematic
This document and the data
disclosed herein or within is
not to be reproduced, used
or disclosed in whole or part
to anyone without the written
permission of MicroTouch.
Size
Doc. Number
B
2
3
4
Rev.
19-221
Template bshtx.dot
FileName C:\AAA\PROTEL\CHIPSETX\MULTIS4.SCH
1
A
Capacitive and Resistive with cable NovRAM
5
2.0
Sheet
2
of
2
6
Figure 4. Excalibur Chip Set Schematic for Capacitive and Resistive Touchscreens with Cable NovRAM (Sheet 2 of 2)
Excalibur Chip Set Controller • Developer’s Guide
17
Table 10 lists the bill of materials for the schematics shown in Figure 5 and Figure 6.
Table 10. Bill of Materials for Capacitive and Resistive Touchscreens without Cable NovRAM
Item
Quantity
Part Description
Reference Designators
1
2
22pF 10% COG 25V
C1 C2
2
1
6.8uF 10V Tantalum
C3
3
6
0.01uF X7R 25V
C12 C13 C14 C15 C16 C17
4
8
0.1uF X7R 25V
C4 C5 C6 C7 C8 C9 C10 C11
5
5
MMBD7000 dual diodes
D1 D2 D3 D4 D5
6
1
LED @5 mA (optional)
D6
7
1
5 pin connector (consult
MicroTouch for specification)
J1
8
4
Murata BLM21A102SPT
Fair-Rite 2508051027
L1 L2 L3 L4
9
1
82.5K 1% 1/10W
R1
10
2
1Meg 5% 1/10W
R2, R3 (R2 and R3 are required for
resistive and multi-mode applications;
not required for capacitive-only
designs.)
11
3
Shorting-plugs (optional)
SP1 SP2 SP3 (Shorting-plugs, SP1 SP2
SP3, are required to implement
multi-mode applications.)
12
1
93C46 EEPROM
U4
13
1
80C32 ROMLESS uP
U2
14
1
Excalibur*
(MicroTouch P/N 19-550)
U1*
15
1
27C020 150 ns
U4 (MicroTouch supplies the firmware.
For single and dual-mode applications,
a 27C512 and 27C010 may be used,
respectively.)
16
2
Motorola MC33072/MC34072
U5, U6
17
1
11.0592 MHz
Y1
* All components except the Excalibur ASIC are non-proprietary.
Excalibur Chip Set Controller • Developer’s Guide
18
1
2
3
4
5
6
Revision History
Signals from Page 2
RD
WR
ROMCLK
ASICRESET
CLOCK
A15
A14
SYSTEMRESET
BiDirectional Signals
to/from Page 2
DATA[7:0]
Rev. ECO
Excalibur Connections
Description
Date
Approved
w/o cable NovRAM
D
VDD
DATA[7:0]
DATA[7:0]
C7
D0
D1
D2
D3
D4
D5
D6
D7
D
RD
WR
ROMCLK
ASICRESET
CLOCK
A15
A14
SYSTEMRESET
C15
.1uF
LLSJ
6
VSJ
5
.01uF
U6B
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
7
OPAMPLL
MC33072
U1
ADDRESS[7:0]
Power and Analog ground are connected
together only at the power-entry point of
the TouchScreen Controller circuit area
on the PCB.
A0
A1
A2
A3
A4
A5
A6
A7
C
Earth ground symbol represents a unique
low impedance path from the ESD
protection circuits to the ground entry
point of the PCB, ideally earth referenced.
VDD
C8
Standard "three o'clock" resistive
sensor pin-out shown. Contact
MicroTouch for available connectors
and pinouts.
.1uF
A14
A15
RD
WR
ROMCLK
CLOCK
EVDD
2
N/C
N/C
N/C
A0
A1
A2
A3
A4
A5
A6
A7
VDD
VDD
GND
GND
A14
A15
RDNOT
WRNOT
573CLK
CLOCK
N/C
N/C
XCSBAR
1
MMBD7000
L3
Ferrite
L4
Ferrite
5
LR
3
1
INTDONE
MMBD7000
SENSE
3
3
2
1
D3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
8
R1
LL
LRSJ
2
VSJ
3
U6A
1
82.5K 1%
LLSJ
OPAMPLL
LR
C16
LRSJ
OPAMPLR
.01uF
OPAMPLR
C10
.1uF
MC33072
C
C13
C3
6.8uF
10V
C17
.01uF
URSJ
6
VSJ
5
.01uF
U5B
UR
7
URSJ
OPAMPUR
UL
OPAMPUR
MC33072
ULSJ
OPAMPUL
SENSE
C12
.01uF
AVDD
ULSJ
2
VSJ
3
U5A
1
OPAMPUL
C11
.1uF
MC33072
LL
TP6
D2
SHLD-DRV
ISET
LL
N/C
LLSJ
OPAMPLL
LR
N/C
LRSJ
OPAMPLR
AVDD
AVDD
VSJ
AGND
AGND
UR
N/C
URSJ
OPAMPUR
UL
N/C
ULSJ
OPAMPUL
IDRIVE
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
4
2
AVDD
4
3
D1
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
INTDONE
LEDCATHODE
ASICRST
uRESET
SYSRST
MODCLK
CHARGE
N/C
VDD
GND
N/C
LLTP
LRTP
ULTP
URTP
PENOUT
Sensor Connector
J1
TP5
.01uF
AVDD
+5VDC
GND
C14
VSJ
4
Power Connections
TP3
8
AVDD
D0
D1
D2
D3
D4
D5
D6
D7
VDD
GND
N/C
SHLDENA
PWMLR
PWMLL
PWMUR
PWMUL
VDD
SP3
Shorting Plug
B
EXCALIBUR
19-550
C9
ASICRESET
uRESET
SYSTEMRESET
EVDD
VDD, AVDD, and EVDD are connected
together only at the power-entry point
of the TouchScreen Controller circuit
area on the PCB.
uRESET
INTDONE
ADDRESS[7:0]
.1uF
TP2
uRESET
INTDONE
ADDRESS[7:0]
Signals to Page 2
VDD
D6
MMBD7000
TP4
2
Stake Pins (3)
1
L2
Ferrite
UL
UR
R3
R2
1M
1M
3
1
1
Ferrite
2
L1
2
2
A
1
TP8
D5
MMBD7000
Touch Screen Configuration Table
Capacitive:
SP3 pins 1&2
Resistive:
SP3 pins 2&3
This document and the data
disclosed herein or within is
not to be reproduced, used
or disclosed in whole or part
to anyone without the written
permission of MicroTouch.
Printed
1
MicroTouch Systems, Inc.
300 Griffin Park
Methuen, MA 01844
PC110
MMBD7000
3
D4
3
TP7
2
3
29-Oct-1997
4
at
Drawn
Date
Checked
Date
Approved
Date
Excalibur Chip Set Schematic
Approved
Date
Capacitive and Resistive w/o cable NovRAM
Approved
Date
Approved
Date
10:56:09
Title
Size
A
Doc. Number
B
Rev.
19-221
Template bsht1.dot
FileName C:\AAA\PROTEL\CHIPSETX\MULTIS1.SCH
5
2.0
Sheet
1
of
2
6
Figure 5. Excalibur Chip Set Schematic for Capacitive and Resistive Touchscreens without Cable NovRAM (Sheet 1 of 2)
Excalibur Chip Set Controller • Developer’s Guide
19
1
2
3
6
w/o cable NovRAM
SYSTEMRESET
DATA-IN
SYSTEMRESET
DATA-IN
5
Microprocessor Connections
Host CPU Connections
From Host
4
D
D
SYSTEMRESET
RD
WR
ROMCLK
ASIC RESET
CLOCK
A15
A14
PS2 communications are enabled via specific firmware
PS2-CLK
PS2-DATA
DATA-OUT
DATA-OUT
SYSTEMRESET
RD
WR
ROMCLK
ASICRESET
CLOCK
A15
A14
DATA[7:0]
C4
MultiMode Implementation
SP2
SP1
1
1
2
2
PSEN
22
24
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CE
OE
Vpp
U2
VCC
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
D0
D1
D2
D3
D4
D5
D6
D7
PGM
NC
13
14
15
17
18
19
20
21
26
16
27C020PLCC32
3
D0
D1
D2
D3
D4
D5
D6
D7
43
42
41
40
39
38
37
36
A8
A9
A10
A11
A12
A13
A14
A15
24
25
26
27
28
29
30
31
RD
WR
PSEN
ROMCLK
DATA-OUT
DATA-IN
19
18
32
33
13
11
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
X1
X2
RSVD
RSVD
RESET
RSVD
RSVD
INT0
INT1
T0
T1
A8
A9
A10
A11
A12
A13
A14
A15
RD
WR
PSEN
ALE/P
TXD
RXD
EA/VP
P1.0/T2
P1.1/T2X
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Y1
11.0592 MHz
35
21
CLOCK
20
12
34
10
23
1
14
15
16
17
uRESET
PS2-DATA
INTDONE
ASICRESET
C2
C1
22pF
22pF
TP1
PWRUP DEFAULTS
2
3
4
5
6
7
8
9
VDD
B
U3
PS2-CLK
4
3
2
1
DO
DI
CLK
CE
VCC
NC
NC
GND
8
7
6
5
C6
.1uF
93C46
22
80C32PLCC
VDD
Shorting Plug
D0
D1
D2
D3
D4
D5
D6
D7
31
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
.1uF
44
1
.1uF
U4
B
C
C5
32
Signals from Page 1
VDD
uRESET
INTDONE
ADDRESS[7:0]
uRESET
INTDONE
ADDRESS[7:0]
BiDirectional Signals
to/from Page 1
DATA[7:0]
VDD
C
Signals to Page 1
VCC
To Host
PS2-CLK
PS2-DATA
GND
BiDirectionals
Shorting Plug
3
Stake Pins (6)
LSB
MSB
MultiMode implementation: Page EPROM U4
via MSB address lines A16 and A17, in this
or similar fashion, choosing one of four
operating modes: Serial Resistive or
Capacitive; PS2 Resistive or Capacitive.
A
Title
Excalibur Chip Set Schematic
This document and the data
disclosed herein or within is
not to be reproduced, used
or disclosed in whole or part
to anyone without the written
permission of MicroTouch.
Size
Doc. Number
B
2
3
4
Rev.
19-221
Template bshtx.dot
FileName C:\AAA\PROTEL\CHIPSETX\MULTIS2.SCH
1
A
Capacitive and Resistive w/o cable NovRAM
5
2.0
Sheet
2
of
2
6
Figure 6. Excalibur Chip Set Schematic for Capacitive and Resistive Touchscreens without Cable NovRAM (Sheet 2 of 2)
Excalibur Chip Set Controller • Developer’s Guide
20