Download Power Electronics Project 4

ISTANBUL TECHNICAL
UNIVERSITY
DEPARTMENT OF ELECTRICAL
ENGINEERING
POWER ELECTRONIC CIRCUITS
FALL 2008, CRN: 11473
ASST. PROF. DENİZ YILDIRIM
PROJECT REPORT
MINIPROJECT IV
DC/AC INVERTER
GROUP MEMBERS
040060450
040050442
040050437
BİROL ÇAPA
ELİF KÖKSAL
BURAK BEŞER
SUBMISSION DATE: JANUARY 21, 2009
2
1. PURPOSE
The purpose of the project is to design and construct an inverter that produces
220V, 50Hz sinusoidal AC voltage from a DC power supply.
The project contains three main steps, design an inverter, simulating the
circuit, and construct the circuit. After construction, the circuit will be tested to
see if it obeys simulation results.
In conclusion, 220V 50Hz sinusoidal output should be obtain.
2. DESIGN
Figure 2.1 - AC inverter circuit
A typical circuit to receive a sinusoidal signal at the output is shown in Figure
2.1. To achieve this purpose the most important part is to design a PWM inverter.
This PWM signal will be applied to the MOSFET H bridge through the gate drive
IC. MOSFETs will be triggered according to the following equation:
3
For obtaining necessary PWM signal, sinusoidal and triangular signal must be
produced and compared. Triangular wave in the carrier wave and the sinusoidal
wave is the main wave. There are many different methods for obtaining those
signals, but XR2206 IC is chosen.
Figure 2.2 - XR2206 waveform generator
Figure 2.3 - Timing resistor vs. frequency
4
It is possible getting desired signals at desired frequencies by choosing
resistors and capacitors. R resistor and C capacitor, in Figure 2.2, are chosen for
frequency range. Figure 2.3 shows the resistor values for particular frequency
range. Equation 1 is the formula of frequency.
f= 1/ R*C
(1)
To obtain the PWM signal, frequencies of the sinus and triangle waves are
chosen carefully. The frequency of triangular wave must be larger than the
sinusoidal. Therefore frequency of sinusoidal wave is 50 Hz, triangular one is
20KHz. With help of the Figure 2.3, resistors for 50Hz as 100K and for 20KHz as
10 K are suitable. From the equation (1) capacitors are calculated 200nF for sinus,
5nF for triangular.
For sinusoidal wave, S1 switch must be off.
For obtaining a modulated wave as PWM, a comparator in used. In Figure 2.4
LM311 can be seen basically. When the input 3 larger than the input 2 the output
is +Vcc, on the other condition the output is –Vcc. the modulated signal is as
Figure 2.5.
Figure 2.4 - LM311
HC7804 “NOT gate” is placed at the output of the LM311, in order to obtain
necessary signals for HIP4082. LM805 regulator is used to get the supply voltage
for HC7804 IC.
5
Figure 2.5 - Modulated signal
Modulated signal which is the output of the comparator and the inverse of it is
applied the HIP4082 IC. The purpose of this IC is to trigger MOSFETs properly.
Typical application schema for HIP4082 is shown in Figure 2.6.
Figure 2.6 - HIP4082 application
6
Diodes between 12 and 9 pins and 12 and 1 pins and capacitors are for
bootstrap, which are needed for full bridge drive.
For trigger MOSFETs correctly 10Ω resistors are placed.
3. SIMULATION
The simulations are done with PSIM. As the sine and triangle waves are
generated from function generator XR2206 IC, these signals are simulated as sine
and triangle wave sources. In Figure 3.1 the simulation circuit is seen with voltage
and current probes attached to it.
Figure 3.1 – The simulation circuit
LM311 comparator is simulated as an ideal op-amp with ±5V supply voltage.
The transformer has a ratio 24:220. Rload is identified as a 484Ω resistance as it is
a 100W 220V incandescent lamp in real construction. Simulation results are given
below due to full load and no load respectively.
7
Figure 3.2 – Waveforms of Vsine, Vtri and Vcontrol at full load
8
Figure 3.3 – Waveforms of Vac, Iac and Vpwm at full load
When no load is attached to circuit the simulation results are acquired as
below. However simulations cannot be run with zero load, Rload is selected
0,00001Ω which can be considered as zero.
Figure 3.4 – Waveforms of Vsine, Vtri and Vcontrol at no load
9
Figure 3.5 – Waveforms of Vac, Iac and Vpwm at no load
As it can be seen from Figure 3.2 through Figure 3.5, only the value of Iac is
related with the value of Rload. Besides that the PWM signal’s waveform is
consistent with theoretical expectations.
4. CONSTRUCTION AND TESTING
Tests of the circuit are executed in parts. Firstly, the sine and triangular waves
are tested which can be seen in Figure 4.1 and Figure 4.2.
10
Figure 4.1 – The sinusoidal waveform
Figure 4.2 – The triangular waveform
After that the comparator’s output signal waveform is observed in
oscilloscope. This waveform can be seen in Figure 4.3 and it is also well-matched
with theoretical calculations.
11
Figure 4.3 – The waveform at the output of LM311
The PWM signal that is produced from voltage comparator LM311 and the
inverted PWM signal that is produced from hex inverter 74HC04 are applied to
the inputs of HIP4082. These waveforms can be seen in Figure 4.4
simultaneously.
Figure 4.4 – Inverted and non-inverted PWM waveform
12
In Figure 4.5 the waveforms of the outputs of HIP4082, PWM signal and
inverted PWM signal that change between 0-12V are given. However, as no load
is attached to the circuit, a 12V DC voltage is seen at the other 2 outputs as it is
given in Figure 4.6.
Figure 4.5 – Waveform at the low-side MOSFET
Figure 4.5 – Waveform at the high-side MOSFET
13
At the testing part a 100W 220V incandescent lamp is connected as a load to
the secondary side of a 22:220 transformer. In figure 4.6 the waveform of the
Vload that is not filtered can be seen.
Figure 4.6 – Waveform of Vload with no capacitor
After connecting a 3.33nF filter capacitor, the waveform of Vload is changed
and approximated to a sinusoidal wave that can be seen in Figure 4.7.
Figure 4.6 – Waveform of Vload with 3.33nF capacitor
14
In Figure 4.7 the waveform of Vload is seen when higher capacitor is used for
filtering. A 150nF capacitor is used for this purpose.
Figure 4.7 – Waveform of Vload with 150nF capacitor
At the secondary side of the transformer the rms value of the voltage is
127.8V and the current that flows through the load is 0.12A as it can be seen in
Figure 4.8.
Figure 4.8 – RMS value of Vlaod and value of Iload
15
Figure 4.9 shows all the testing setup.
Figure 4.9 – The complete testing setup
5. CONCLUSION
In conclusion, the sinusoidal wave is produced from a DC voltage by using a
DC/AC inverter circuit. Adding a capacitance filter the output voltage of the load
approximate to a sinusoidal waveform. In addition designing a L-C low pass filter
aid to obtain a smooth sinusoidal waveform.
6. EQUIPMENT
2*XR2206 Function Generator
LM311 Voltage Comparator
74HC04 Hex Inverter
HIP4082 MOSFET Driver
LM7805 Voltage Regulator
4*IRF540 N-Type MOSFET
2*UF4002 Ultrafast Diode
4*1N5245 Ultrafast Zener Diode
16
2*0.01uF, 2*2.2uF, 3*1uF, 1.5uF, 200nF, 5nF, 0.33uF 2*10uF (electrolyte
type), 2*1uF (electrolyte type) Capacitors
6*1KΩ, 4*5.1KΩ, 4*15Ω, 2*10KΩ, 2*100KΩ, 220Ω Resistors
100KΩ Potentiometer, 10KΩ Potentiometer
7. REFERENCES
1. Exar Corp. (1997). XR-2206 Monolithic Function Generator. Retrieved
January 20, 2009, from http://www.datasheetcatalog.com/
2. Fairchild Semiconductor Corporation (2001). MC78XX/LM78XX/MC78XXA
3-Terminal 1A positive voltage regulator. Retrieved January 20, 2009,
from http://www.datasheetcatalog.com/
3. General Semiconductor (1998). UF4001 THRU UF4007 Ultrafast effıcıent
plastıc rectifier. Retrieved January 20, 2009, from
http://www.datasheetcatalog.com/
4. Intersil (2004). HIP4082. Retrieved January 20, 2009, from
http://www.datasheetcatalog.com/
5. Philips Semiconductors (1999). IRF540, IRF540S. Retrieved January 20,
2009, from http://www.datasheetcatalog.com/
6. Semelab Plc. (1999). 1N5221B-LCC3 TO 1N5281B-LCC3. Retrieved
January 20, 2009, from http://www.datasheetcatalog.com/
7. ST Microelectronics (2002). LM111 - LM211 - LM311 Voltage comparators.
Retrieved January 20, 2009, from http://www.datasheetcatalog.com/
17
8. Texas Instruments Incorporated (2004). CD54HC04, CD74HC04,
CD54HCT04, CD74HCT04 High-speed CMOS logic hex inverter.
Retrieved January 20, 2009, from http://www.datasheetcatalog.com/
8. APPENDIX

Appendix 1 – XR-2206 datasheet

Appendix 2 – UF4007 datasheet

Appendix 3 – HIP4082 datasheet

Appendix 4 – IRF540 datasheet

Appendix 5 – 1N5245 datasheet

Appendix 6 – LM311 datasheet

Appendix 7 – CD74HC05 datasheet

Appendix 8 – LM7805 datasheet
XR-2206
...the analog plus
Monolithic
Function Generator
company TM
June 1997-3
FEATURES
APPLICATIONS
Waveform Generation
Low-Sine Wave Distortion, 0.5%, Typical
Excellent Temperature Stability, 20ppm/°C, Typ.
Sweep Generation
Wide Sweep Range, 2000:1, Typical
AM/FM Generation
Low-Supply Sensitivity, 0.01%V, Typ.
V/F Conversion
Linear Amplitude Modulation
FSK Generation
TTL Compatible FSK Controls
Phase-Locked Loops (VCO)
Wide Supply Range, 10V to 26V
Adjustable Duty Cycle, 1% TO 99%
GENERAL DESCRIPTION
The XR-2206 is a monolithic function generator
integrated circuit capable of producing high quality sine,
square, triangle, ramp, and pulse waveforms of
high-stability and accuracy. The output waveforms can be
both amplitude and frequency modulated by an external
voltage. Frequency of operation can be selected
externally over a range of 0.01Hz to more than 1MHz.
The circuit is ideally suited for communications,
instrumentation, and function generator applications
requiring sinusoidal tone, AM, FM, or FSK generation. It
has a typical drift specification of 20ppm/°C. The oscillator
frequency can be linearly swept over a 2000:1 frequency
range with an external control voltage, while maintaining
low distortion.
ORDERING INFORMATION
Part No.
Package
Operating
Temperature Range
XR-2206M
16 Lead 300 Mil CDIP
-55°C to +125°C
XR-2206P
16 Lead 300 Mil PDIP
–40°C to +85°C
XR-2206CP
16 Lead 300 Mil PDIP
0°C to +70°C
XR-2206D
16 Lead 300 Mil JEDEC SOIC
0°C to +70°C
Rev. 1.03
1972
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 (510) 668-7017
1
XR-2206
TC1
5
TC2
6
TR1
7
TR2
8
FSKI
9
AMSI
1
Timing
Capacitor
Timing
Resistors
VCC
GND
BIAS
4
12
10
11 SYNCO
VCO
Current
Switches
Multiplier
And Sine
Shaper
WAVEA1 13
WAVEA2 14
SYMA1 15
SYMA2 16
Figure 1. XR-2206 Block Diagram
Rev. 1.03
2
+1
2
STO
3
MO
XR-2206
AMSI
STO
MO
VCC
TC1
TC2
TR1
TR2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
SYMA2
SYMA1
WAVEA2
WAVEA1
GND
SYNCO
BIAS
FSKI
AMSI
STO
MO
VCC
TC1
TC2
TR1
TR2
16 Lead PDIP, CDIP (0.300”)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
SYMA2
SYMA1
WAVEA2
WAVEA1
GND
SYNCO
BIAS
FSKI
16 Lead SOIC (Jedec, 0.300”)
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
AMSI
I
Amplitude Modulating Signal Input.
2
STO
O
Sine or Triangle Wave Output.
3
MO
O
Multiplier Output.
4
VCC
5
TC1
I
Timing Capacitor Input.
6
TC2
I
Timing Capacitor Input.
7
TR1
O
Timing Resistor 1 Output.
8
TR2
O
Timing Resistor 2 Output.
9
FSKI
I
Frequency Shift Keying Input.
10
BIAS
O
Internal Voltage Reference.
O
Sync Output. This output is a open collector and needs a pull up resistor to VCC.
Positive Power Supply.
11
SYNCO
12
GND
13
WAVEA1
I
Wave Form Adjust Input 1.
14
WAVEA2
I
Wave Form Adjust Input 2.
15
SYMA1
I
Wave Symetry Adjust 1.
16
SYMA2
I
Wave Symetry Adjust 2.
Ground pin.
Rev. 1.03
3
XR-2206
DC ELECTRICAL CHARACTERISTICS
Test Conditions: Test Circuit of Figure 2 Vcc = 12V, TA = 25°C, C = 0.01F, R1 = 100k, R2 = 10k, R3 = 25k
Unless Otherwise Specified. S1 open for triangle, closed for sine wave.
XR-2206M/P
Parameters
Min.
Typ.
XR-2206CP/D
Max.
Min.
Typ.
Max.
Units
Conditions
General Characteristics
Single Supply Voltage
10
26
10
26
V
Split-Supply Voltage
+5
+13
+5
+13
V
20
mA
Supply Current
12
17
14
R1 10k
Oscillator Section
Max. Operating Frequency
0.5
Lowest Practical Frequency
1
0.5
0.01
1
MHz
0.01
Hz
C = 1000pF, R1 = 1k
C = 50F, R1 = 2M
Frequency Accuracy
+1
+4
+2
% of fo
Temperature Stability
Frequency
+10
+50
+20
ppm/°C 0°C TA 70°C
R1 = R2 = 20k
Sine Wave Amplitude Stability2
4800
4800
ppm/°C
Supply Sensitivity
0.01
0.01
%/V
2000:1
fH = fL
2
%
fL = 1kHz, fH = 10kHz
Sweep Range
0.1
1000:1 2000:1
fo = 1/R1C
VLOW = 10V, VHIGH = 20V,
R1 = R2 = 20k
fH @ R1 = 1k
fL @ R1 = 2M
Sweep Linearity
10:1 Sweep
2
1000:1 Sweep
8
8
%
fL = 100Hz, fH = 100kHz
FM Distortion
0.1
0.1
%
+10% Deviation
Figure 5
Recommended Timing Components
Timing Capacitor: C
Timing Resistors: R1 & R2
Triangle Sine Wave
0.001
100
0.001
100
F
1
2000
1
2000
k
Output1
Figure 3
Triangle Amplitude
Sine Wave Amplitude
160
40
60
80
160
mV/k
Figure 2, S1 Open
60
mV/k
Figure 2, S1 Closed
Max. Output Swing
6
6
Vp-p
Output Impedance
600
600
Triangle Linearity
1
1
%
Amplitude Stability
0.5
0.5
dB
For 1000:1 Sweep
%
R1 = 30k
%
See Figure 7 and Figure 8
Sine Wave Distortion
Without Adjustment
2.5
With Adjustment
0.4
2.5
1.0
0.5
1.5
Notes
1 Output amplitude is directly proportional to the resistance, R , on Pin 3. See Figure 3.
3
2 For maximum amplitude stability, R should be a positive temperature coefficient resistor.
3
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Rev. 1.03
4
XR-2206
DC ELECTRICAL CHARACTERISTICS (CONT’D)
XR-2206M/P
Parameters
Min.
Typ.
50
100
XR-2206CP/D
Max.
Min.
Typ.
Max.
Units
50
100
k
Conditions
Amplitude Modulation
Input Impedance
Modulation Range
100
100
%
Carrier Suppression
55
55
dB
Linearity
2
2
%
For 95% modulation
Amplitude
12
12
Vp-p
Measured at Pin 11.
Rise Time
250
250
ns
CL = 10pF
Fall Time
50
50
ns
CL = 10pF
Saturation Voltage
0.2
0.4
0.2
0.6
V
IL = 2mA
Leakage Current
0.1
20
0.1
100
A
VCC = 26V
Square-Wave Output
FSK Keying Level (Pin 9)
0.8
1.4
2.4
0.8
1.4
2.4
V
See section on circuit controls
Reference Bypass Voltage
2.9
3.1
3.3
2.5
3
3.5
V
Measured at Pin 10.
Notes
1 Output amplitude is directly proportional to the resistance, R , on Pin 3. See Figure 3.
3
2 For maximum amplitude stability, R should be a positive temperature coefficient resistor.
3
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 750mW
Derate Above 25°C . . . . . . . . . . . . . . . . . . . . . . 5mW/°C
Total Timing Current . . . . . . . . . . . . . . . . . . . . . . . . 6mA
Storage Temperature . . . . . . . . . . . . -65°C to +150°C
SYSTEM DESCRIPTION
The XR-2206 is comprised of four functional blocks; a
voltage-controlled oscillator (VCO), an analog multiplier
and sine-shaper; a unity gain buffer amplifier; and a set of
current switches.
terminals to ground. With two timing pins, two discrete
output frequencies can be independently produced for
FSK generation applications by using the FSK input
control pin. This input controls the current switches which
select one of the timing resistor currents, and routes it to
the VCO.
The VCO produces an output frequency proportional to
an input current, which is set by a resistor from the timing
Rev. 1.03
5
XR-2206
VCC
1mF
4
1
5
16
C
6
FSK Input
S1 = Open For Triangle
= Closed For Sinewave
15
14
13
9
7
8
R1
R2
25K
Mult.
And
Sine
Shaper
VCO
Symmetry Adjust
S1
THD Adjust
500
Current
Switches
Triangle Or
Sine Wave
Output
Square Wave
Output
2
+1
11
10 12
1mF
XR-2206
3
10K
R3
25K
+
VCC
1mF
VCC
5.1K
5.1K
Figure 2. Basic Test Circuit
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
26
70°C Max.
Package
Dissipation
Triangle
5
4
22
1KW
Sinewave
3
2
1
0
20
40
60
80
ICC (mA)
Peak Output Voltage (Volts)
6
2KW
18
10KW
14
30KW
10
8
100
12
16
20
24
28
VCC (V)
R3 in (KW)
Figure 3. Output Amplitude
as a Function of the Resistor,
R3, at Pin 3
Figure 4. Supply Current vs
Supply Voltage, Timing, R
Rev. 1.03
6
XR-2206
10M
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
1M
Normal Output Amplitude
Timing Resistor ( W )
MAXIMUM TIMING R
NORMAL RANGE
100K
TYPICAL VALUE
10K
1K
4V
1.0
0.5
MINIMUM TIMING R
10-2
102
10
104
0
VCC / 2
106
Frequency (Hz)
DC Voltage At Pin 1
Figure 5. R versus Oscillation Frequency.
Figure 6. Normalized Output Amplitude
versus DC Bias at AM Input (Pin 1)
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÁÁÁÁÁÁÁ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÁÁÁÁÁÁÁ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÁÁÁÁÁÁÁ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
5
5
3
2
1
10
100
R=3KW
VOUT =0.5VRMS Pin 2
RL=10KW
3
2
1
0
1.0
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
4
C = 0.01mF
Trimmed For Minimum
Distortion At 30 KW
Distortion (%)
Distortion (%)
4
4V
0
103
10
100
1K
10K
100K
1M
Frequency (Hz)
Timing R K(W)
Figure 7. Trimmed Distortion versus
Timing Resistor.
Figure 8. Sine Wave Distortion versus
Operating Frequency with
Timing Capacitors Varied.
Rev. 1.03
7
XR-2206
3
C=0.01F
Frequency Drift (%)
2
R=1M
R=2K
1
R=10K
R=200K
R=200K
0
-1
R=1M
Sweep
Input
R=1K
Rc
+
-
IB
VC
-2
R=1K
-3
-50
-25
0
25
IT
IC
R=10K
R=2K
50
75
R
ÁÁ
Pin 7
or 8
+
3V
-
12
125
100
Ambient Temperature (C°)
Figure 9. Frequency Drift versus
Temperature.
Figure 10. Circuit Connection for Frequency Sweep.
VCC
1F
4
1
5
C
16
Mult.
And
Sine
Shaper
VCO
6
14
13
9
2M
R1
1K
7
8
Current
Switches
+1
10
R
12
S1 Closed For Sinewave
15
S1
200
2
Triangle Or
Sine Wave Output
11
Square Wave
Output
XR-2206
3
R3
50K
+
10K
1F
+
VCC
10F
VCC
5.1K
5.1K
Figure 11. Circuit tor Sine Wave Generation without External Adjustment.
(See Figure 3 for Choice of R3)
Rev. 1.03
8
XR-2206
VCC
1F
4
1
5
C
1
F=
RC
25K
Mult.
And
Sine
Shaper
VCO
6
R1
1K
7
8
RB
15
14
S1 Closed For Sinewave
S1
13
9
2M
Symmetry Adjust
16
RA
500
Current
Switches
2
+1
Triangle Or
Sine Wave Output
Square Wave
Output
11
10
R
12
3
XR-2206
R3
50K
+
1F
10K
+
VCC
10F
VCC
5.1K
5.1K
Figure 12. Circuit for Sine Wave Generation with Minimum Harmonic Distortion.
(R3 Determines Output Swing - See Figure 3)
VCC
1F
4
1
5
>2V
F1
<1V
F2
FSK Input
C
16
VCO
6
R1
R2
9
7
8
15
Mult.
And
Sine
Shaper
14
13
Current
Switches
200
2
+1
11
F1=1/R1C
F2=1/R2C
10 12
+
3
XR-2206
R3
50K
1F
+
10F
VCC
5.1K
5.1K
Figure 13. Sinusoidal FSK Generator
Rev. 1.03
9
FSK Output
XR-2206
VCC
1
f 2
C R1 R2
1F
4
1
5
C
16
Mult.
And
Sine
Shaper
VCO
6
7
8
R1
R1 R2
15
14
9
R1
R2
Duty Cycle =
13
Current
Switches
2
+1
Sawtooth Output
11
10
12
3
R3
24K
+
Pulse Output
XR-2206
5.1K
1F
VCC
+
10F
VCC
5.1K
5.1K
Figure 14. Circuit for Pulse and Ramp Generation.
Frequency-Shift Keying
APPLICATIONS INFORMATION
The XR-2206 can be operated with two separate timing
resistors, R1 and R2, connected to the timing Pin 7 and 8,
respectively, as shown in Figure 13. Depending on the
polarity of the logic signal at Pin 9, either one or the other
of these timing resistors is activated. If Pin 9 is
open-circuited or connected to a bias voltage 2V, only
R1 is activated. Similarly, if the voltage level at Pin 9 is
1V, only R2 is activated. Thus, the output frequency can
be keyed between two levels. f1 and f2, as:
Sine Wave Generation
Without External Adjustment
Figure 11 shows the circuit connection for generating a
sinusoidal output from the XR-2206. The potentiometer,
R1 at Pin 7, provides the desired frequency tuning. The
maximum output swing is greater than V+/2, and the
typical distortion (THD) is < 2.5%. If lower sine wave
distortion is desired, additional adjustments can be
provided as described in the following section.
f1 = 1/R1C and f2 = 1/R2C
For split-supply operation, the keying voltage at Pin 9 is
referenced to V-.
The circuit of Figure 11 can be converted to split-supply
operation, simply by replacing all ground connections
with V-. For split-supply operation, R3 can be directly
connected to ground.
Output DC Level Control
The dc level at the output (Pin 2) is approximately the
same as the dc bias at Pin 3. In Figure 11, Figure 12 and
Figure 13, Pin 3 is biased midway between V+ and
ground, to give an output dc level of V+/2.
Rev. 1.03
10
XR-2206
With External Adjustment:
PRINCIPLES OF OPERATION
Description of Controls
The harmonic content of sinusoidal output can be
reduced to -0.5% by additional adjustments as shown in
Figure 12. The potentiometer, RA, adjusts the
sine-shaping resistor, and RB provides the fine
adjustment for the waveform symmetry. The adjustment
procedure is as follows:
Frequency of Operation:
The frequency of oscillation, fo, is determined by the
external timing capacitor, C, across Pin 5 and 6, and by
the timing resistor, R, connected to either Pin 7 or 8. The
frequency is given as:
1. Set RB at midpoint and adjust RA for minimum
distortion.
f 0 + 1 Hz
RC
2. With RA set as above, adjust RB to further reduce
distortion.
and can be adjusted by varying either R or C. The
recommended values of R, for a given frequency range,
as shown in Figure 5. Temperature stability is optimum
for 4k < R < 200k. Recommended values of C are from
1000pF to 100F.
Triangle Wave Generation
The circuits of Figure 11 and Figure 12 can be converted
to triangle wave generation, by simply open-circuiting Pin
13 and 14 (i.e., S1 open). Amplitude of the triangle is
approximately twice the sine wave output.
Frequency Sweep and Modulation:
Frequency of oscillation is proportional to the total timing
current, IT, drawn from Pin 7 or 8:
f+
FSK Generation
Figure 13 shows the circuit connection for sinusoidal FSK
signal operation. Mark and space frequencies can be
independently adjusted by the choice of timing resistors,
R1 and R2; the output is phase-continuous during
transitions. The keying signal is applied to Pin 9. The
circuit can be converted to split-supply operation by
simply replacing ground with V-.
320I T (mA)
Hz
C(F)
Timing terminals (Pin 7 or 8) are low-impedance points,
and are internally biased at +3V, with respect to Pin 12.
Frequency varies linearly with IT, over a wide range of
current values, from 1A to 3mA. The frequency can be
controlled by applying a control voltage, VC, to the
activated timing pin as shown in Figure 10. The frequency
of oscillation is related to VC as:
ǒ
ǒ
V
f+ 1 1 ) R 1 – C
3
RC
RC
Pulse and Ramp Generation
Figure 14 shows the circuit for pulse and ramp waveform
generation. In this mode of operation, the FSK keying
terminal (Pin 9) is shorted to the square-wave output (Pin
11), and the circuit automatically frequency-shift keys
itself between two separate frequencies during the
positive-going and negative-going output waveforms.
The pulse width and duty cycle can be adjusted from 1%
to 99% by the choice of R1 and R2. The values of R1 and
R2 should be in the range of 1k to 2M.
ǓǓHz
where VC is in volts. The voltage-to-frequency conversion
gain, K, is given as:
K + ēfńēV C + – 0.32 HzńV
R CC
CAUTION: For safety operation of the circuit, IT should be
limited to 3mA.
Rev. 1.03
11
XR-2206
Output Amplitude:
Maximum output amplitude is inversely proportional to
the external resistor, R3, connected to Pin 3 (see
Figure 3). For sine wave output, amplitude is
approximately 60mV peak per k of R3; for triangle, the
peak amplitude is approximately 160mV peak per k of
R3. Thus, for example, R3 = 50k would produce
approximately 13V sinusoidal output amplitude.
at Pin 1 is approximately 100k. Output amplitude varies
linearly with the applied voltage at Pin 1, for values of dc
bias at this pin, within 14 volts of VCC/2 as shown in
Figure 6. As this bias level approaches VCC/2, the phase
of the output signal is reversed, and the amplitude goes
through zero. This property is suitable for phase-shift
keying and suppressed-carrier AM generation. Total
dynamic range of amplitude modulation is approximately
55dB.
Amplitude Modulation:
CAUTION: AM control must be used in conjunction with a
well-regulated supply, since the output amplitude now becomes
a function of VCC.
Output amplitude can be modulated by applying a dc bias
and a modulating signal to Pin 1. The internal impedance
VR
VCC
11
15 V2 5
14
16 6
13
1
VCC
7
6
5
8
10
VR
V1
VCC
4
Int’nI.
Reg.
VR
VR
V1
V2
12
9
Figure 15. Equivalent Schematic Diagram
Rev. 1.03
12
3 2
XR-2206
16 LEAD CERAMIC DUAL-IN-LINE
(300 MIL CDIP)
Rev. 1.00
16
9
1
8
E
E1
D
A1
Base
Plane
Seating
Plane
A
L
e
c
B
α
B1
INCHES
SYMBOL
MILLIMETERS
MIN
MAX
MIN
MAX
A
0.100
0.200
2.54
5.08
A1
0.015
0.060
0.38
1.52
B
0.014
0.026
0.36
0.66
B1
0.045
0.065
1.14
1.65
c
0.008
0.018
0.20
0.46
D
0.740
0.840
18.80
21.34
E1
0.250
0.310
6.35
7.87
E
0.300 BSC
7.62 BSC
e
0.100 BSC
2.54 BSC
L
0.125
0.200
3.18
5.08
α
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev. 1.03
13
XR-2206
16 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 1.00
16
9
1
8
E1
E
D
A2
Seating
Plane
A
L
α
A1
B
INCHES
SYMBOL
eA
eB
B1
e
MILLIMETERS
MIN
MAX
MIN
MAX
A
0.145
0.210
3.68
5.33
A1
0.015
0.070
0.38
1.78
A2
0.115
0.195
2.92
4.95
B
0.014
0.024
0.36
0.56
B1
0.030
0.070
0.76
1.78
C
0.008
0.014
0.20
0.38
D
0.745
0.840
18.92
21.34
E
0.300
0.325
7.62
8.26
E1
0.240
0.280
6.10
7.11
e
eA
0.100 BSC
2.54 BSC
0.300 BSC
7.62 BSC
eB
0.310
0.430
7.87
10.92
L
0.115
0.160
2.92
4.06
α
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev. 1.03
14
C
XR-2206
16 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
Rev. 1.00
D
16
9
E
H
1
8
C
A
Seating
Plane
e
B
α
A1
L
INCHES
SYMBOL
MILLIMETERS
MIN
MAX
MIN
A
0.093
0.104
2.35
2.65
A1
0.004
0.012
0.10
0.30
B
0.013
0.020
0.33
0.51
C
0.009
0.013
0.23
0.32
D
0.398
0.413
10.10
10.50
E
0.291
0.299
7.40
7.60
e
0.050 BSC
MAX
1.27 BSC
H
0.394
0.419
10.00
10.65
L
0.016
0.050
0.40
1.27
α
0°
8°
0°
8°
Note: The control dimension is the millimeter column
Rev. 1.03
15
XR-2206
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 1972 EXAR Corporation
Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.03
16
UF4001 THRU UF4007
ULTRAFAST EFFICIENT PLASTIC RECTIFIER
Reverse Voltage - 50 to 1000 Volts
Forward Current - 1.0 Ampere
FEATURES
♦ Plastic package has Underwriters Laboratory
Flammability Classification 94V-0
♦ 1.0 ampere operation at TA=55°C with no thermal
runaway
♦ Glass passivated chip junction
♦ Low cost
♦ Ultrafast recovery
time for high efficiency
♦ Low forward voltage
♦ Low leakage current
♦ High surge current capability
♦ High temperature soldering guaranteed:
250°C/10 seconds, 0.375" (9.5mm) lead length,
5 lbs. (2.3kg) tension
DO-204AL
1.0 (25.4)
MIN.
0.107 (2.7)
0.080 (2.0)
DIA.
0.205 (5.2)
0.160 (4.1)
MECHANICAL DATA
1.0 (25.4)
MIN.
0.034 (0.86)
0.028 (0.71)
DIA.
NOTE: Lead diameter is 0.026 (0.66)
0.023 (0.58)
for suffix "E" part numbers
Dimensions in inches and (millimeters)
Case: JEDEC DO-204AL molded plastic body over
passivated chip
Terminals: Plated axial leads, solderable per MIL-STD-750,
Method 2026
Polarity: Color band denotes cathode end
Mounting Position: Any
Weight: 0.012 ounce, 0.3 gram
MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS
.Ratings at 25°C ambient temperature unless otherwise specified.
SYMBOLS
UF
4001
UF
4002
UF
4003
UF
4004
UF
4005
UF
4006
UF
4007
Maximum repetitive peak reverse voltage
VRRM
50
100
200
400
600
800 1000
Volts
Maximum RMS voltage
Volts
VRMS
35
70
140
280
420
560
Maximum DC blocking voltage
VDC
50
100
200
400
600
800 1000 Volts
Maximum average forward rectified current
0.375" (9.5mm) lead length at TA=55°C
I(AV)
1.0
Amp
Peak forward surge current
8.3ms single half sine-wave superimposed on
rated load (JEDEC Method)
IFSM
30.0
Amps
Maximum instantaneous forward voltage at 1.0A
Maximum DC reverse current
at rated DC blocking voltage
TA=25°C
TA=100°C
VF
1.0
1.7
10.0
50.0
IR
Volts
µA
Maximum reverse recovery time (NOTE 1)
trr
Typical junction capacitance (NOTE 2)
CJ
17.0
pF
RΘJA
RΘJL
60.0
15.0
°C/W
Typical thermal resistance (NOTE 3)
Operating junction and storage temperature range
TJ, TSTG
NOTES:
(1) Reverse recovery test conditions: IF=0.5A, IR=1.0A, Irr=0.25A
(2) Measured at 1.0 MHZ and applied reverse voltage of 4.0 Volts
(3) Thermal resistance from junction to ambient and from junction to lead length 0.375" ( 9.5mm), P.C.B. mounted
4/98
50.0
700
UNITS
75.0
-55
to +150
ns
°C
RATINGS AND CHARACTERISTIC CURVES UF4001 THRU UF4007
FIG. 1 - MAXIMUM FORWARD CURRENT
DERATING CURVE
30
RESISTIVE OR
INDUCTIVE LOAD
0.375" (9.5mm)
LEAD LENGTH
PEAK FORWARD SURGE CURRENT,
AMPERES
AVERAGE FORWARD RECTIFIED
CURRENT, AMPERES
1.0
0.5
0
20
40
60
80
FIG. 2 - MAXIMUM NON-REPETITIVE PEAK
FORWARD SURGE CURRENT
TA=55°C
8.3ms SINGLE HALF SINE-WAVE
(JEDEC Method)
25
20
15
10
5.0
0
1
10
AMBIENT TEMPERATURE, °C
NUMBER OF CYCLES AT 60 HZ
FIG. 4 - TYPICAL REVERSE LEAKAGE
CHARACTERISTICS
FIG. 3 - TYPICAL INSTANTANEOUS
FORWARD CHARACTERISTICS
100
1
UF4005 - UF4007
0.1
TJ=25°C
PULSE WIDTH=300µs
1% DUTY CYCLE
0.01
0.001
0.4
TJ=125°C
UF4001 - UF4004
0.6
0.8
1.0
1.2
1.4
1.6
1.8
INSTANTANEOUS REVERSE LEAKAGE CURRENT,
MICROAMPERES
INSTANTANEOUS FORWARD CURRENT,
AMPERES
10
100
100 120 140 160
TJ=100°C
10
TJ=125°C
TJ=100°C
1
TJ=25°C
0.1
INSTANTANEOUS FORWARD VOLTAGE,
VOLTS
UF4001-UF4004
UF4005-UF4007
0.01
0
20
40
60
80
100
PERCENT OF RATED PEAK REVERSE VOLTAGE, %
FIG. 5 - TYPICAL JUNCTION CAPACITANCE
JUNCTION CAPACITANCE, pF
100
TJ=25°C
f=1.0 MHz
Vsig=50mVp-p
10
1
0.1
1
10
REVERSE VOLTAGE, VOLTS
100
HIP4082
®
Data Sheet
July 2004
80V, 1.25A Peak Current H-Bridge FET
Driver
FN3676.3
Features
The HIP4082 is a medium frequency, medium voltage
H-Bridge N-Channel MOSFET driver IC, available in 16 lead
plastic SOIC (N) and DIP packages.
Specifically targeted for PWM motor control and UPS
applications, bridge based designs are made simple and
flexible with the HIP4082 H-bridge driver. With operation up
to 80V, the device is best suited to applications of moderate
power levels.
• Independently Drives 4 N-Channel FET in Half Bridge or
Full Bridge Configurations
• Bootstrap Supply Max Voltage to 95VDC
• Drives 1000pF Load in Free Air at 50°C with Rise and Fall
Times of Typically 15ns
• User-Programmable Dead Time (0.1 to 4.5µs)
• DIS (Disable) Overrides Input Control and Refreshes
Bootstrap Capacitor when Pulled Low
Similar to the HIP4081, it has a flexible input protocol for
driving every possible switch combination except those
which would cause a shoot-through condition. The
HIP4082’s reduced drive current allows smaller packaging
and it has a much wider range of programmable dead times
(0.1 to 4.5µs) making it ideal for switching frequencies up to
200kHz. The HIP4082 does not contain an internal charge
pump, but does incorporate non-latching level-shift
translation control of the upper drive circuits.
• Input Logic Thresholds Compatible with 5V to 15V Logic
Levels
This set of features and specifications is optimized for
applications where size and cost are important. For
applications needing higher drive capability the HIP4080A
and HIP4081A are recommended.
• DC Motor Controls
Ordering Information
• Noise Cancellation Systems
PART
NUMBER
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
• Shoot-Through Protection
• Undervoltage Protection
• Pb-free Available
Applications
• UPS Systems
• Full Bridge Power Supplies
• Switching Power Amplifiers
• Battery Powered Vehicles
• Peripherals
HIP4082IB
-55 to +125 16 Ld SOIC (N)
M16.15
• Medium/Large Voice Coil Motors
HIP4082IBZ
(Note)
-55 to +125 16 Ld SOIC (N) (Pb-free)
M16.15
HIP4082IP
-55 to +125 16 Ld PDIP
E16.3
• Related Literature
- TB363, Guidelines for Handling and Processing
Moisture Sensitive Surface Mount Devices (SMDs)
HIP4082IPZ
(Note)
-55 to +125 16 Ld PDIP (Pb-free)
E16.3
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
1
Pinout
HIP4082
(PDIP, SOIC)
TOP VIEW
BHB 1
16 BHO
BHI 2
15 BHS
BLI 3
14 BLO
ALI 4
13 ALO
DEL 5
12 VDD
VSS
6
11 AHS
AHI 7
10 AHO
DIS 8
9 AHB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1995. Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HIP4082
Application Block Diagram
80V
12V
BHO
BHS
BHI
LOAD
BLO
BLI
HIP4082
ALI
ALO
AHS
AHI
AHO
GND
GND
Functional Block Diagram
9
LEVEL
SHIFT
U/V
BHI
2
AHI
7
DIS
8
AHB BHB
1
DRIVER
DRIVER
LEVEL
SHIFT
10 AHO BHO 16
11 AHS
BHS 15
TURN-ON
DELAY
TURN-ON
DELAY
VDD
VDD
12
ALI
4
DEL
5
BLI
3
VSS
6
DETECTOR
UNDERVOLTAGE
DRIVER
TURN-ON
DELAY
2
DRIVER
13 ALO
BLO 14
TURN-ON
DELAY
U/V
HIP4082
Typical Application (PWM Mode Switching)
80V
12V
PWM
INPUT
DELAY RESISTOR
DIS
FROM
OPTIONAL
OVERCURRENT
LATCH
1 BHB
BHO 16
2 BHI
BHS 15
3 BLI
BLO 14
4 ALI
ALO 13
5 DEL
VDD 12
6 VSS
AHS 11
7 AHI
AHO 10
8 DIS
AHB 9
LOAD
12V
GND
RDIS
TO OPTIONAL
CURRENT CONTROLLER OR
OVERCURRENT LATCH
+
-
RSH
GND
3
HIP4082
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on AHS, BHS . . . . . -6V (Transient) to 80V (25°C to 150°C)
Voltage on AHS, BHS . . . . . -6V (Transient) to 70V (-55°C to150°C)
Voltage on AHB, BHB . . . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD
Voltage on ALO, BLO . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3V
Voltage on AHO, BHO . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input
Current, DEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 0mA
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
NOTE: All voltages are relative VSS unless otherwise specified.
Thermal Resistance, Junction-Ambient
θJA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . See Curve
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C
(For SOIC - Lead Tips Only))
Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . +8.5V to +15V
Voltage on VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V
Voltage on AHB, BHB . . . . . . . VAHS, BHS +7.5V to VAHS, BHS +VDD
Input Current, DEL . . . . . . . . . . . . . . . . . . . . . . . . . -4mA to -100µA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL = 100K
TJ = -55°C
TO +150°C
TJ = +25°C
PARAMETER
SYMBOL
MIN
TYP
MAX
MIN
All inputs = 0V, RDEL = 100K
1.2
2.3
3.5
0.85
4
mA
All inputs = 0V, RDEL = 10K
2.2
4.0
5.5
1.9
6.0
mA
f = 50kHz, no load
1.5
2.6
4.0
1.1
4.2
mA
50kHz, no load, RDEL = 10kΩ
2.5
4.0
6.4
2.1
6.6
mA
TEST CONDITIONS
MAX UNITS
SUPPLY CURRENTS & UNDER VOLTAGE PROTECTION
VDD Quiescent Current
IDD
VDD Operating Current
IDDO
AHB, BHB Off Quiescent Current
IAHBL, IBHBL
AHI = BHI = 0V
0.5
1.0
1.5
0.4
1.6
mA
AHB, BHB On Quiescent Current
IAHBH, IBHBH
AHI = BHI = VDD
65
145
240
40
250
µA
AHB, BHB Operating Current
IAHBO, IBHBO
f = 50kHz, CL = 1000pF
.65
1.1
1.8
.45
2.0
mA
AHS, BHS Leakage Current
IHLK
-
-
1.0
-
-
µA
VAHS = VBHS = 80V
VAHB = VBHB = 96
VDD Rising Undervoltage Threshold
VDDUV+
6.8
7.6
8.25
6.5
8.5
V
VDD Falling Undervoltage Threshold
VDDUV-
6.5
7.1
7.8
6.25
8.1
V
Undervoltage Hysteresis
UVHYS
0.17
0.4
0.75
0.15
0.90
V
AHB, BHB Undervoltage Threshold
VHBUV
Referenced to AHS & BHS
5
6.0
7
4.5
7.5
V
0.8
V
INPUT PINS: ALI, BLI, AHI, BHI, & DIS
Low Level Input Voltage
VIL
Full Operating Conditions
-
-
1.0
-
High Level Input Voltage
VIH
Full Operating Conditions
2.5
-
-
2.7
-
35
-
-
-
mV
Input Voltage Hysteresis
V
Low Level Input Current
IIL
VIN = 0V, Full Operating Conditions
-145
-100
-60
-150
-50
µA
High Level Input Current
IIH
VIN = 5V, Full Operating Conditions
-1
-
+1
-10
+10
µA
RDEL = 100K
2.5
4.5
8.0
2.0
8.5
µS
RDEL = 10K
0.27
0.5
0.75
0.2
0.85
µS
TURN-ON DELAY PIN DEL
Dead Time
TDEAD
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, & BHO
Low Level Output Voltage
VOL
IOUT = 50mA
0.65
1.1
0.5
1.2
V
High Level Output Voltage
VDD-VOH
IOUT = -50mA
0.7
1.2
0.5
1.3
V
4
HIP4082
Electrical Specifications
VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL = 100K (Continued)
TJ = -55°C
TO +150°C
TJ = +25°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX UNITS
Peak Pullup Current
IO +
VOUT = 0V
1.1
1.4
2.5
0.85
2.75
A
Peak Pulldown Current
IO -
VOUT = 12V
1.0
1.3
2.3
0.75
2.5
A
Switching Specifications
VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL= 100K, CL = 1000pF.
TJ = -55°C TO
+150°C
TJ = +25°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
Lower Turn-off Propagation Delay
(ALI-ALO, BLI-BLO)
TLPHL
-
25
50
-
70
ns
Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)
THPHL
-
55
80
-
100
ns
Lower Turn-on Propagation Delay
(ALI-ALO, BLI-BLO)
TLPLH
-
40
85
-
100
ns
Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)
THPLH
-
75
110
-
150
ns
Rise Time
TR
-
9
20
-
25
ns
Fall Time
TF
-
9
20
-
25
ns
TPWIN-ON/OFF
50
-
-
50
-
ns
80
ns
Minimum Input Pulse Width
Output Pulse Response to 50 ns Input Pulse
63
TPWOUT
Disable Turn-off Propagation Delay
(DIS - Lower Outputs)
TDISLOW
-
50
80
-
90
ns
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
TDISHIGH
-
75
100
-
125
ns
Disable Turn-on Propagation Delay
(DIS - ALO & BLO)
TDLPLH
-
40
70
-
100
ns
Disable Turn-on Propagation Delay
(DIS- AHO & BHO)
TDHPLH
-
1.2
2
-
3
µs
Refresh Pulse Width (ALO & BLO)
TREF-PW
375
580
900
350
950
ns
RDEL = 10K
TRUTH TABLE
INPUT
OUTPUT
ALI, BLI
AHI, BHI
VDDUV
VHBUV
DIS
ALO, BLO
AHO, BHO
X
X
X
X
1
0
0
X
X
1
X
X
0
0
0
X
0
1
0
0
0
1
X
0
X
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
NOTE:
X signifies that input can be either a “1” or “0”.
5
HIP4082
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
BHB
B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin.
2
BHI
B High-side Input. Logic level input that controls BHO driver (Pin 16). BLI (Pin 3) high level input overrides BHI high
level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides BHI high level
input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).
3
BLI
B Low-side Input. Logic level input that controls BLO driver (Pin 14). If BHI (Pin 2) is driven high or not connected
externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at DEL (Pin 5). DIS (Pin
8) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than
VDD).
4
ALI
A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected
externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at DEL (Pin 5). DIS (Pin
8) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than
VDD).
5
DEL
Turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the dead time between drivers.
All drivers turn-off with no adjustable delay, so the DEL resistor guarantees no shoot-through by delaying the turn-on
of all drivers. The voltage across the DEL resistor is approximately Vdd -2V.
6
VSS
Chip negative supply, generally will be ground.
7
AHI
A High-side Input. Logic level input that controls AHO driver (Pin 10). ALI (Pin 4) high level input overrides AHI high
level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides AHI high level
input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).
8
DIS
DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to
15V (no greater than VDD).
9
AHB
A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin.
10
AHO
A High-side Output. Connect to gate of A High-side power MOSFET.
11
AHS
A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
12
VDD
Positive supply to control logic and lower gate drivers. De-couple this pin to VSS (Pin 6).
13
ALO
A Low-side Output. Connect to gate of A Low-side power MOSFET.
14
BLO
B Low-side Output. Connect to gate of B Low-side power MOSFET.
15
BHS
B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
16
BHO
B High-side Output. Connect to gate of B High-side power MOSFET.
6
HIP4082
Timing Diagrams
X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT
TLPHL
THPHL
DIS=0
and UV
XLI
XHI
XLO
XHO
THPLH
TLPLH
FIGURE 1. INDEPENDENT MODE
DIS=0
and UV
XLI
XHI = HI OR NOT CONNECTED
XLO
XHO
FIGURE 2. BISTATE MODE
TDLPLH
DIS or UV
TDIS
TREF-PW
XLI
XHI
XLO
XHO
TDHPLH
FIGURE 3. DISABLE FUNCTION
7
TR
(10% - 90%)
TF
(10% - 90%)
HIP4082
Performance Curves
16
3.5
200kHz
VDD = 16V
3
IDD SUPPLY CURRENT (mA)
IDD SUPPLY CURRENT (mA)
15
3.25
VDD = 15V
2.75
2.5
VDD = 12V
2.25
VDD = 10V
2
VDD = 8V
1.75
1.5
-60
14
13
12
11
10
8
-20
50kHz
7
6
10kHz
5
4
-40
100kHz
9
0
20
40
60
80 100
JUNCTION TEMPERATURE (°C)
120
140
FIGURE 4. IDD SUPPLY CURRENT vs TEMPERATURE AND
VDD SUPPLY VOLTAGE
-60
7
PEAK GATE CURRENT (A)
LOADED, NL BIAS CURRENTS (mA)
1.925
6
5
4
1000pF LOAD
3
NO LOAD
2
-20
100
FREQUENCY (kHz)
150
1.5
SOURCE
ISRC(BIAS)
1.25
SINK
ISNK(BIAS)
1
0.75
8
8
200
FIGURE 6. FLOATING (IXHB) BIAS CURRENT vs FREQUENCY
AND LOAD
140
2
0.815
0.5
50
120
1.75
1
0
0
20
40
60
80 100
JUNCTION TEMPERATURE (°C)
FIGURE 5. VDD SUPPLY CURRENT vs TEMPERATURE AND
SWITCHING FREQUENCY (1000pF LOAD)
8
0
-40
9
10
11
12
13
14
BIAS
BIAS SUPPLY VOLTAGE (V) AT 25°C
15
15
FIGURE 7. GATE SOURCE/SINK PEAK CURRENT vs BIAS
SUPPLY VOLTAGE AT 25°C
1.2
-40°C
1.1
-55°C
1.2
VDD-VOH (V)
NORMALIZED GATE
SINK/SOURCE CURRENT (A)
1.4
1
0°C
25°C
1
125°C
150°C
0.8
0.9
0.6
0.8
-75
-50
-25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
125
150
FIGURE 8. GATE CURRENT vs TEMPERATURE, NORMALIZED
TO 25°C
8
8
9
10
11
12
13
VDD SUPPLY VOLTAGE (V)
14
FIGURE 9. VDD-VOH vs BIAS VOLTAGE TEMPERATURE
15
HIP4082
Performance Curves
(Continued)
8
VDD, BIAS SUPPLY VOLTAGE (V)
1.4
VOL (V)
1.2
-40°C
-55°C
0°C
25°C
1
0.8
125°C
150°C
0.6
8
9
10
11
12
13
VDD SUPPLY VOLTAGE (V)
14
LOWER U/V SET
6.5
6
UPPER U/V SET/RESET
5.5
-40
DIS TO TURN-ON/OFF TIME (ns)
80
UPPER tON
70
60
UPPER tOFF
LOWER tON
50
40
30
LOWER tOFF
20
-60
120
140 160
-40
-20
0
20
40
60
80
100
120
DISHTON
1000
DISHTOFF
100
DISLTON
10
140 160
-60 -40
JUNCTION TEMPERATURE (°C)
FIGURE 12. UPPER LOWER TURN-ON / TURN-OFF PROPAGATION DELAY vs TEMPERATURE
-20
DISLOFF
0
20
40
60
80 100
JUNCTION TEMPERATURE (°C)
120 140 160
FIGURE 13. UPPER/LOWER DIS(ABLE) TO TURN-ON/OFF vs
TEMPERATURE (°C)
2
2.5
TOTAL POWER DISSIPATION (W)
LEVEL-SHIFT CURRENT (mA)
0
20
40
60
80 100
JUNCTION TEMPERATURE (°C)
104
90
1.5
1
0.5
-20
FIGURE 11. UNDERVOLTAGE TRIP VOLTAGES vs TEMPERATURE
100
PROPAGATION DELAYS (ns)
7
5
-60
15
FIGURE 10. VOL vs BIAS VOLTAGE AND TEMPERATURE
LOWER U/V RESET
7.5
0
20
40
60
80
SWITCHING FREQUENCY (kHz)
FIGURE 14. FULL BRIDGE LEVEL-SHIFT CURRENT vs
FREQUENCY (kHz)
9
100
2
16 PIN DIP
1.5
SOIC
1
0.5
QUIESCENT BIAS COMPONENT
0
-60
-30
0
30
60
90
AMBIENT TEMPERATURE (°C)
120
FIGURE 15. MAXIMUM POWER DISSIPATION vs AMBIENT
TEMPERATURE
150
HIP4082
Performance Curves
(Continued)
104
90
VDD = 15V
VDD = 12V
VXHS-VSS
DEAD TIME (ns)
85
VDD = 9V
1000
80
75
100
0
10
20
30
40
50
60
70
DEAD TIME RESISTANCE (kΩ)
80
90 100
FIGURE 16. DEAD-TIME vs DEL RESISTANCE AND BIAS
SUPPLY (VDD) VOLTAGE
10
70
100
50
0
50
TEMPERATURE (°C)
100
150
FIGURE 17. MAXIMUM OPERATING PEAK AHS/BHS VOLTAGE
vs TEMPERATURE
HIP4082
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AE
D
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
C
D
0.735
0.775
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.005
-
0.13
-
5
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
eA
0.300 BSC
eB
-
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
L
0.115
N
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
11
5
E
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
0.355
19.68
D1
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
0.204
18.66
16
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
16
6
10.92
7
3.81
4
9
Rev. 0 12/93
HIP4082
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INCHES
INDEX
AREA
H
0.25(0.010) M
B M
SYMBOL
E
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.053
0.069
1.35
1.75
-
A1
0.004
0.010
0.10
0.25
-
B
0.014
0.019
0.35
0.49
9
C
0.007
0.010
0.19
0.25
-
D
0.386
0.394
9.80
10.00
3
E
0.150
0.157
3.80
4.00
4
e
µα
A1
MIN
0.050 BSC
1.27 BSC
-
H
0.228
0.244
5.80
6.20
-
h
0.010
0.020
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
16
0o
16
7
8o
Rev. 1 02/02
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
FEATURES
IRF540, IRF540S
SYMBOL
QUICK REFERENCE DATA
• ’Trench’ technology
• Low on-state resistance
• Fast switching
• Low thermal resistance
d
VDSS = 100 V
ID = 23 A
g
RDS(ON) ≤ 77 mΩ
s
GENERAL DESCRIPTION
N-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:• d.c. to d.c. converters
• switched mode power supplies
• T.V. and computer monitor power supplies
The IRF540 is supplied in the SOT78 (TO220AB) conventional leaded package.
The IRF540S is supplied in the SOT404 (D2PAK) surface mounting package.
PINNING
SOT78 (TO220AB)
PIN
SOT404 (D2PAK)
DESCRIPTION
tab
tab
1
gate
2
drain1
3
source
tab
2
drain
1
1 23
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
- 55
100
100
± 20
23
16
92
100
175
V
V
V
A
A
A
W
˚C
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
Tmb = 25 ˚C
1 It is not possible to make connection to pin:2 of the SOT404 package
August 1999
1
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
IRF540, IRF540S
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
EAS
Non-repetitive avalanche
energy
IAS
Peak non-repetitive
avalanche current
CONDITIONS
MIN.
MAX.
UNIT
-
230
mJ
-
23
A
Unclamped inductive load, IAS = 10 A;
tp = 350 µs; Tj prior to avalanche = 25˚C;
VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer
to fig:14
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
MIN.
SOT78 package, in free air
SOT404 package, pcb mounted, minimum
footprint
TYP. MAX. UNIT
-
-
1.5
K/W
-
60
50
-
K/W
K/W
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
VGS = 0 V; ID = 0.25 mA;
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 175˚C
Tj = -55˚C
RDS(ON)
gfs
IGSS
IDSS
Drain-source on-state
resistance
Forward transconductance
Gate source leakage current
Zero gate voltage drain
current
VGS = 10 V; ID = 17 A
Tj = 175˚C
VDS = 25 V; ID = 17 A
VGS = ± 20 V; VDS = 0 V
VDS = 100 V; VGS = 0 V
VDS = 80 V; VGS = 0 V; Tj = 175˚C
MIN.
TYP. MAX. UNIT
100
89
2
1
8.7
-
3
49
132
15.5
10
0.05
-
4
6
77
193
100
10
250
V
V
V
V
V
mΩ
mΩ
S
nA
µA
µA
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 17 A; VDD = 80 V; VGS = 10 V
-
-
65
10
29
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 50 V; RD = 2.2 Ω;
VGS = 10 V; RG = 5.6 Ω
Resistive load
-
8
39
26
24
-
ns
ns
ns
ns
Ld
Ld
Internal drain inductance
Internal drain inductance
-
3.5
4.5
-
nH
nH
Ls
Internal source inductance
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
-
7.5
-
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
890
139
83
1187
167
109
pF
pF
pF
August 1999
2
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
IRF540, IRF540S
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
VSD
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
trr
Qrr
Reverse recovery time
Reverse recovery charge
IS
ISM
August 1999
CONDITIONS
MIN.
TYP. MAX. UNIT
-
-
23
A
-
-
92
A
IF = 28 A; VGS = 0 V
-
0.94
1.5
V
IF = 17 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 25 V
-
61
200
-
ns
nC
3
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
IRF540, IRF540S
Normalised Power Derating, PD (%)
Transient thermal impedance, Zth j-mb (K/W)
10
100
90
80
D = 0.5
1
70
0.2
60
50
40
0.1
0.05
0.1
30
P
D
D = tp/T
tp
0.02
20
single pulse
10
0.01
1E-06
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
175
100
50
90
45
80
40
70
35
60
30
50
25
40
20
30
15
20
10
10
5
0
0
150
9V
1E-02
1E-01
1E+00
8V
7V
6V
5V
4V
0
175
1
2
3
4
5
6
7
8
9
10
Drain-Source Voltage, VDS (V)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
Drain-Source On Resistance, RDS(on) (Ohms)
Peak Pulsed Drain Current, IDM (A)
1000
1E-03
Drain Current, ID (A)
55
50
75
100
125
Mounting Base temperature, Tmb (C)
1E-04
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating, ID (%)
25
1E-05
Pulse width, tp (s)
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
0
T
0.8
0.7
RDS(on) = VDS/ ID
100
0.6
10
D.C.
1
tp = 10 us
0.5
100 us
0.4
1 ms
10 ms
100 ms
0.3
4V
5.5V
6V
6.5V
5V
0.2
7V
8V
0.1
VGS =9 V
0
0.1
1
10
100
Drain-Source Voltage, VDS (V)
0
1000
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
August 1999
10
20
30
Drain Current, ID (A)
40
50
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID)
4
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
IRF540, IRF540S
Drain current, ID (A)
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
4.5
VDS > ID X RDS(ON)
Threshold Voltage, VGS(TO) (V)
4
maximum
3.5
typical
3
2.5
minimum
2
175 C
Tj = 25 C
1.5
1
0.5
0
0
1
2
3
4
5
6
7
8
9
10
-60
-40
-20
Gate-source voltage, VGS (V)
20
40
60
80
100 120 140 160 180
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics.
ID = f(VGS)
20
0
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Transconductance, gfs (S)
1.0E-01
Drain current, ID (A)
VDS > ID X RDS(ON)
18
Tj = 25 C
16
14
1.0E-02
175 C
minimum
1.0E-03
12
10
typical
1.0E-04
8
maximum
6
1.0E-05
4
2
1.0E-06
0
0
2
4
6
8
0
10 12 14 16 18 20 22 24 26 28 30
Drain current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
0.5
1
1.5
2
2.5
3
3.5
Gate-source voltage, VGS (V)
4
4.5
5
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised On-state Resistance
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
Capacitances, Ciss, Coss, Crss (pF)
10000
Ciss
1000
Coss
100
Crss
10
-60
-40
-20
0
20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
0.1
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
August 1999
1
10
Drain-Source Voltage, VDS (V)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
5
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
IRF540, IRF540S
Maximum Avalanche Current, IAS (A)
Source-Drain Diode Current, IF (A)
100
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
VGS = 0 V
25 C
10
175 C
Tj = 25 C
Tj prior to avalanche = 150 C
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0.1
0.001
1.1 1.2 1.3 1.4 1.5
Source-Drain Voltage, VSDS (V)
0.1
1
10
Avalanche time, tAV (ms)
Fig.13. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
August 1999
0.01
Fig.14. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
6
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
IRF540, IRF540S
MECHANICAL DATA
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220
E
SOT78
A
A1
P
q
D1
D
L1
L2(1)
Q
b1
L
1
2
e
e
3
c
b
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
UNIT
A
A1
b
b1
c
D
D1
E
mm
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
e
L
L1
2.54
15.0
13.5
3.30
2.79
L2
max.
P
q
Q
3.0
3.8
3.6
3.0
2.7
2.6
2.2
Note
1. Terminals in this zone are not tinned.
OUTLINE
VERSION
SOT78
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-06-11
TO-220
Fig.15. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to mounting instructions for SOT78 (TO220AB) package.
3. Epoxy meets UL94 V0 at 1/8".
August 1999
7
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
IRF540, IRF540S
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)
SOT404
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
OUTLINE
VERSION
D
max.
D1
E
11
1.60
1.20
10.30
9.70
e
Lp
HD
Q
2.54
2.90
2.10
15.40
14.80
2.60
2.20
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
98-12-14
99-06-25
SOT404
Fig.16. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
August 1999
8
Rev 1.100
1N5221B-LCC3
TOB-LCC
1N5281B-LCC3
MECHANICAL DATA
Dimensions in mm (inches)
ZENER VOLTAGE REGULATOR
DIODE IN HERMETIC CERAMIC
SURFACE MOUNT PACKAGE
FOR HIGH RELIABILITY
APPLICATIONS
1.40 ± 0.15
(0.055 ± 0.006)
5.59 ± 0.13
(0.22 ± 0.005)
3
2
4
1
1.27 ± 0.05
(0.05 ± 0.002)
0.23 rad.
(0.009)
0.64 ± 0.08
(0.025 ± 0.003)
3.81 ± 0.13
(0.15 ± 0.005)
0.25 ± 0.03
(0.01 ± 0.001)
0.23 min.
(0.009)
FEATURES
• Military Screening Options available
2.03 ± 0.20
(0.08 ± 0.008)
1.02 ± 0.20
(0.04 ± 0.008)
1 = CATHODE
2 = N/C
3 = N/C
4 = ANODE
ABSOLUTE MAXIMUM RATINGS
Tcase
Tstg
PTOT
RTHJ-A
-55 to +175°C
-65 to +175°C
500mW
300°C/W
Operating temperature Range
Storage Temperature Range
Power Dissipation TA = 25°C
Thermal resistance (Junction to Ambient)
ELECTRICAL CHARACTERISTICS @ 25°C
Part No.
Nominal
Test
Zener Voltage
Current
Vz @ IZT
IZT
ZZT @ IZT
ZZK @ IZK = 0.25mA
IR
@
VR Volts
Volts
mA
Ohms
Ohms
mA
A
B, C & D
2.4
2.5
2.7
2.8
3.0
3.3
3.6
3.9
4.3
4.7
5.1
5.6
6.0
6.2
6.8
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
30
30
30
30
29
28
24
23
22
19
17
11
7.0
7.0
5.0
1200
1250
1300
1400
1600
1600
1700
1900
2000
1900
1600
1600
1600
1000
750
100
100
75
75
50
25
15
10
5.0
5.0
5.0
5.0
5.0
5.0
3.0
0.95
0.95
0.95
0.95
0.95
0.95
0.95
0.95
0.95
1.9
1.9
2.9
3.3
3.8
4.8
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
2.0
2.0
3.0
3.5
4.0
5.0
1N5221
1N5222
1N5223
1N5224
1N5225
1N5226
1N5227
1N5228
1N5229
1N5230
1N5231
1N5232
1N5233
1N5234
1N5235
Semelab plc.
Max Zener Impedance
Max Reverse Leakage Current
Max Zener Voltage
Telephone +44(0)1455 556565. Fax +44(0)1455 552612.
E-mail: [email protected]
Website: http://www.semelab.co.uk
Temp. Coeff
– 0.085
– 0.085
– 0.080
– 0.080
– 0.075
– 0.070
– 0.065
– 0.060
± 0.055
± 0.030
± 0.030
+ 0.038
+ 0.038
+ 0.045
+ 0.050
Prelim. 1/99
1N5221B-LCC3
TOB-LCC
1N5281B-LCC3
ELECTRICAL CHARACTERISTICS @ 25°C continued
Part No.
Nominal
Test
Zener Voltage
Current
Vz @ IZT
IZT
ZZT @ IZT
ZZK @ IZK = 0.25mA
IR
@
VR Volts
Temp. Coeff
Volts
mA
Ohms
Ohms
mA
A
7.5
8.2
8.7
9.1
10
11
12
13
14
15
16
17
18
19
20
22
24
25
27
28
30
33
36
39
43
47
51
56
60
62
68
75
82
87
91
100
110
120
130
140
150
160
170
180
190
200
20
20
20
20
20
20
20
9.5
9.0
8.5
7.8
7.4
7.0
6.6
6.2
5.6
5.2
5.0
4.6
4.5
4.2
3.8
3.4
3.2
3.0
2.7
2.5
2.2
2.1
2.0
1.8
1.7
1.5
1.4
1.4
1.3
1.1
1.0
0.95
0.90
0.85
0.80
0.74
0.68
0.66
0.65
6.0
8.0
8.0
10
17
22
30
13
15
16
17
19
21
23
25
29
33
35
41
44
49
58
70
80
93
105
125
150
170
185
230
270
330
370
400
500
750
900
1100
1300
1500
1700
1900
2200
2400
2500
500
500
600
600
600
600
600
600
600
600
600
600
600
600
600
600
600
600
600
600
600
700
700
800
900
1000
1100
1300
1400
1400
1600
1700
2000
2200
2300
2600
3000
4000
4500
4500
5000
5500
5500
6000
6500
7000
3.0
3.0
3.0
3.0
3.0
2.0
1.0
0.5
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
5.7
6.2
6.2
6.7
7.6
8.0
8.7
9.4
9.5
10.5
11.4
12.4
13.3
13.3
14.3
16.2
17.1
18.1
20
20
22
24
26
29
31
34
37
41
44
45
49
53
59
65
66
72
80
86
94
101
108
116
123
130
137
144
B, C & D
6.0
6.5
6.5
7.0
8.0
8.4
9.1
9.9
10
11
12
13
14
14
15
17
18
19
21
21
23
25
27
30
33
36
39
43
46
47
52
56
62
68
69
76
84
91
99
106
114
122
129
137
144
152
+ 0.058
+ 0.062
+ 0.065
+ 0.068
+ 0.075
+ 0.076
+ 0.077
+ 0.079
+ 0.082
+ 0.082
+ 0.083
+ 0.084
+ 0.085
+ 0.086
+ 0.086
+ 0.087
+ 0.088
+ 0.089
+ 0.090
+ 0.091
+ 0.091
+ 0.092
+ 0.093
+ 0.094
+ 0.095
+ 0.095
+ 0.096
+ 0.096
+ 0.097
+ 0.097
+ 0.097
+ 0.098
+ 0.098
+ 0.099
+ 0.099
+ 0.110
+ 0.110
+ 0.110
+ 0.110
+ 0.110
+ 0.110
+ 0.110
+ 0.110
+ 0.110
+ 0.110
+ 0.110
1N5236
1N5237
1N5238
1N5239
1N5240
1N5241
1N5242
1N5243
1N5244
1N5245
1N5246
1N5247
1N5248
1N5249
1N5250
1N5251
1N5252
1N5253
1N5254
1N5255
1N5256
1N5257
1N5258
1N5259
1N5260
1N5261
1N5262
1N5263
1N5264
1N5265
1N5266
1N5267
1N5268
1N5269
1N5270
1N5271
1N5272
1N5273
1N5274
1N5275
1N5276
1N5277
1N5278
1N5279
1N5280
1N5281
Semelab plc.
Max Zener Impedance
Max Reverse Leakage Current
Max Zener Voltage
Telephone +44(0)1455 556565. Fax +44(0)1455 552612.
E-mail: [email protected]
Website: http://www.semelab.co.uk
Prelim. 1/99
LM111
LM211 - LM311
VOLTAGE COMPARATORS
■ MAXIMUM INPUT CURRENT : 150nA
■ MAXIMUM OFFSET CURRENT : 20nA
■ DIFFERENTIAL INPUT VOLTAGE RANGE :
±30V
■ POWER CONSUMPTION :135mW AT ±15V
N
DIP8
■ SUPPLY VOLTAGE : +5V TO ±15V
■ OUTPUT CURRENT : 50mA
DESCRIPTION
The LM111, LM211, LM311 are voltage comparators that have low input currents.
They are also designed to operate over a wide
range of supply voltages : from standard ±15V operational amplifier supplies down to the single +5V
supply used for IC logic.
Their output is compatible with RTL-DTL and TTL
as well as MOS circuits and can switch voltages
up to +50V at outputs currents as high as 50mA.
D
SO8
PIN CONNECTIONS (top view)
ORDER CODE
Part Number
Temperature
Range
LM111
-55°C, +125°C
LM211
-40°C, +105°C
LM311
0°C, +70°C
Example : LM311D
Package
N
D
•
•
•
•
•
•
N = Dual in Line Package (DIP)
D = Small Outline Package (SO) - also available in Tape & Reel (DT)
June 2002
1234-
1
8
2
7
3
6
4
5
Ground
Non-inverting input
Inverting input
VCC-
5678-
Balance
Strobe/Balance
Output
VCC+
1/9
LM111-LM211-LM311
SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
Supply Voltage
36
V
Vid
Differential Input Voltage
±30
V
Vi
Input Voltage 1)
±15
V
30
V
V(1-4)
V(7-4)
Ground to Negative Supply Voltage
Output to Negative Supply Voltage
LM111-LM211
LM311
Output Short-Circuit Duration
VCC+
Voltage at strobe pin
pd
Tj
Tstg
50
40
10
Power Dissipation 2)
DIP8
SO8
Junction Temperature
Storage Temperature Range
V
s
-5
V
1250
710
mW
+150
°C
-65 to +150
°C
1. This rating applies for ±15V supplies. The positive input voltage limit is 30V above the negative. The negative input voltage is equal to the
negative supply voltage or 30V below the positive supply, whichever is less.
2.
Pd is calculated with T amb = +25°C, Tj = +150°C and R thja = 100°C/W for DIP8 package
= 175°C/W for SO8 package
OPERATING CONDITIONS
Symbol
VCC
Parameter
Supply Voltage
Operating Free-Air Temperature range
Toper
2/9
LM111
LM211
LM311
Value
Unit
5 to ±15
V
-55 to +125
-40 to +105
0 to +70
°C
LM111-LM211-LM311
ELECTRICAL CHARACTERISTICS
VCC+ = ±15V, Tamb = +25°C (unless otherwise specified)
LM111 - LM211
Symbol
Unit
Min.
Max.
0.7
Min.
Typ.
Max.
3
4
2
7.5
10
Vio
Iio
Input Offset Current -(see note 1)
Tamb = +25°C
Tmin ≤ Tamb ≤ Tmax
4
10
20
6
50
70
Iib
Input Bias Current - (see note 1 )
Tamb = +25°C
Tmin ≤ Tamb ≤ Tmax
60
100
150
100
250
300
Avd
Large Signal Voltage Gain
ICC+
Supply Currents
Positive
Negative
-
Vicm
VOL
IOH
tre
nA
nA
Input Common Mode Voltage Range
Tmin ≤ Tamb ≤ Tmax
Tmin ≤ Tamb ≤ Tmax
VCC+ ≥ +4.5V, VCC- = 0
IO = 8mA
High Level Output Current
Tamb = +25°C
Strobe Current
Response Time - note
200
40
200
V/mV
mA
Tmin ≤ Tamb ≤ Tmax
Istrobe
mV
40
Low Level Output Voltage
Tamb = +25°C, IO = 50mA
2.
Typ.
Input Offset Voltage (RS ≤ 50kΩ)- note 1)
Tamb = +25°C
Tmin ≤ Tamb ≤ Tmax
ICC
1.
LM311
Parameter
2)
Vi ≤ -5mV
Vi ≤ -10mV
Vi ≤ -6m
Vi ≤ -10mV
Vi ≥ +5mV,Vo = +35V
Vi ≥ +10mV,Vo = +5V
Vi ≥ +5mV,Vo = +35V
-14.5
5.1
4.1
6
5
+13.8
-14.7
+13
0.75
1.5
-14.5
5.1
4.1
7.5
5
+13.8
-14.7
+13
V
V
0.23
0.2
0.1
0.75
1.5
0.23
0.4
0.2
50
0.4
10
0.5
nA
nA
µA
3
3
mA
200
200
ns
The offset voltage, offset current and bias current specifications apply for any supply voltage from a single +5V suplly up to ±15V
supplies
The offset voltages and offset currents given are the maximum values required to drive the output down to +1V or up to +14V with a
1mA load current. Thus, these parameters define an error band and take into account the worst-case of voltage gain and input im
pedance.
The response time specified (see definitions) is for a 100mV input step with 5mV overdrive.
3/9
LM111-LM211-LM311
4/9
LM111-LM211-LM311
5/9
LM111-LM211-LM311
6/9
LM111-LM211-LM311
7/9
LM111-LM211-LM311
PACKAGE MECHANICAL DATA
8 PINS - PLASTIC DIP
Millimeters
Inches
Dimensions
Min.
A
a1
B
b
b1
D
E
e
e3
e4
F
i
L
Z
8/9
Typ.
Max.
Min.
3.32
0.51
1.15
0.356
0.204
0.020
0.045
0.014
0.008
0.065
0.022
0.012
0.430
0.384
0.313
2.54
7.62
7.62
3.18
Max.
0.131
1.65
0.55
0.304
10.92
9.75
7.95
Typ.
0.100
0.300
0.300
6.6
5.08
3.81
1.52
0.125
0260
0.200
0.150
0.060
LM111-LM211-LM311
PACKAGE MECHANICAL DATA
8 PINS - PLASTIC MICROPACKAGE (SO)
s
b1
b
a1
A
a2
C
c1
a3
L
E
e3
D
M
5
1
4
F
8
Millimeters
Inches
Dimensions
Min.
A
a1
a2
a3
b
b1
C
c1
D
E
e
e3
F
L
M
S
Typ.
Max.
0.65
0.35
0.19
0.25
1.75
0.25
1.65
0.85
0.48
0.25
0.5
4.8
5.8
5.0
6.2
0.1
Min.
Typ.
Max.
0.026
0.014
0.007
0.010
0.069
0.010
0.065
0.033
0.019
0.010
0.020
0.189
0.228
0.197
0.244
0.004
45° (typ.)
1.27
3.81
3.8
0.4
0.050
0.150
4.0
1.27
0.6
0.150
0.016
0.157
0.050
0.024
8° (max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2002 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia
Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
© http://www.st.com
9/9
[ /Title
(CD54H
C04,
CD54H
CT04,
CD74H
C04,
CD74H
CT04)
/Subject
(High
Speed
CD54HC04, CD74HC04,
CD54HCT04, CD74HCT04
Data sheet acquired from Harris Semiconductor
SCHS117E
High-Speed CMOS Logic Hex Inverter
August 1997 - Revised June 2004
Features
Description
• Buffered Inputs
The
CD54HC04,
CD54HCT04,
CD74HC04
and
CD74HCT04 logic gates utilize silicon-gate CMOS
technology to achieve operating speeds similar to LSTTL
gates, with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The 74HCT logic family functionally is pin
compatible with the standard 74LS logic family.
• Typical Propagation Delay: 6ns at VCC = 5V,
CL = 15pF, TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
Ordering Information
• Balanced Propagation Delay and Transition Times
PART NUMBER
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2-V to 6-V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5-V to 5.5-V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
TEMP. RANGE
(oC)
PACKAGE
CD54HC04F3A
-55 to 125
14 Ld CERDIP
CD54HCT04F3A
-55 to 125
14 Ld CERDIP
CD74HC04E
-55 to 125
14 Ld PDIP
CD74HC04M
-55 to 125
14 Ld SOIC
CD74HC04MT
-55 to 125
14 Ld SOIC
CD74HC04M96
-55 to 125
14 Ld SOIC
CD74HCT04E
-55 to 125
14 Ld PDIP
CD74HCT04M
-55 to 125
14 Ld SOIC
CD74HCT04MT
-55 to 125
14 Ld SOIC
CD74HCT04M96
-55 to 125
14 Ld SOIC
CD74HCT04PWR
-55 to 125
14 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes
96 and R denote tape and reel. The suffix T denotes a
small-quantity reel of 250.
Pinout
CD54HC04, CD54HCT04 (CERDIP)
CD74HC04 (PDIP, SOIC)
CD74HCT04 (PDIP, SOIC, TSSOP)
TOP VIEW
1A 1
14 VCC
1Y 2
13 6A
2A 3
12 6Y
2Y 4
11 5A
3A 5
10 5Y
3Y 6
9 4A
GND 7
8 4Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2004, Texas Instruments Incorporated
1
CD54HC04, CD74HC04, CD54HCT04, CD74HCT04
Functional Diagram
1
14
2
13
1A
6A
1Y
2A
2Y
3A
3Y
GND
VCC
3
12
4
11
5
10
6
9
7
8
6Y
5A
5Y
4A
4Y
TRUTH TABLE
INPUTS
nA
nY
L
H
H
L
H = High Voltage Level, L = Low Voltage Level
Logic Symbol
nA
nY
2
CD54HC04, CD74HC04, CD54HCT04, CD74HCT04
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating, and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
High Level Input
Voltage
VIH
-
Low Level Input
Voltage
VIL
25oC
IO (mA) VCC (V)
-40oC TO +85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
HC TYPES
High Level Output
Voltage
CMOS Loads
VOH
-
VIH or
VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
II
VCC or
GND
-
-
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
-
6
-
-
±0.1
-
±1
-
±1
µA
3
CD54HC04, CD74HC04, CD54HCT04, CD74HCT04
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
SYMBOL
VI (V)
ICC
VCC or
GND
0
High Level Input
Voltage
VIH
-
Low Level Input
Voltage
VIL
High Level Output
Voltage
CMOS Loads
VOH
PARAMETER
Quiescent Device
Current
25oC
IO (mA) VCC (V)
-40oC TO +85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
6
-
-
2
-
20
-
40
µA
-
4.5 to
5.5
2
-
-
2
-
2
-
V
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
VIH or
VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
±0.1
-
±1
-
±1
µA
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
II
VCC
and
GND
0
5.5
-
ICC
VCC or
GND
0
5.5
-
-
2
-
20
-
40
µA
∆ICC
(Note 2)
VCC
- 2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
NOTE:
2. For dual-supply systems, theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
nB
1.2
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
85
-
105
-
130
ns
4.5
-
-
17
-
21
-
26
ns
6
-
-
14
-
18
-
22
ns
5
-
6
-
-
-
-
-
ns
HC TYPES
Propagation Delay,
Input to Output (Figure 1)
Propagation Delay, Data Input to
Output Y
tPLH, tPHL
CL = 15pF
4
CD54HC04, CD74HC04, CD54HTC04, CD74HCT04
Switching Specifications Input tr, tf = 6ns
PARAMETER
Transition Times (Figure 1)
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
(Continued)
SYMBOL
TEST
CONDITIONS
tTLH, tTHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
75
-
95
18
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
CI
-
-
-
-
10
-
10
-
10
pF
CPD
-
5
-
21
-
-
-
-
-
pF
HCT TYPES
Propagation Delay, Input to
Output (Figure 2)
tPLH, tPHL
CL = 50pF
4.5
-
-
19
-
24
-
29
ns
Propagation Delay, Data Input to
Output Y
tPLH, tPHL
CL = 15pF
5
-
7
-
-
-
-
-
ns
Transition Times (Figure 2)
tTLH, tTHL
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
CI
-
-
-
-
10
-
10
-
10
pF
CPD
-
5
-
24
-
-
-
-
-
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
Test Circuits and Waveforms
tr = 6ns
tf = 6ns
90%
50%
10%
INPUT
GND
tTLH
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
tPHL
tf = 6ns
tr = 6ns
VCC
tTLH
90%
1.3V
10%
INVERTING
OUTPUT
tPHL
tPLH
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
CD54HC04F
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
CD54HC04F3A
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
CD54HCT04F
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
CD54HCT04F3A
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
CD74HC04E
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74HC04M
ACTIVE
SOIC
D
14
50
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CD74HC04M96
ACTIVE
SOIC
D
14
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CD74HC04MT
ACTIVE
SOIC
D
14
250
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CD74HCT04E
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74HCT04M
ACTIVE
SOIC
D
14
50
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CD74HCT04M96
ACTIVE
SOIC
D
14
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CD74HCT04MT
ACTIVE
SOIC
D
14
250
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CD74HCT04PWR
ACTIVE
TSSOP
PW
14
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
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MC78XX/LM78XX/MC78XXA
3-Terminal 1A Positive Voltage Regulator
Features
Description
•
•
•
•
•
The MC78XX/LM78XX/MC78XXA series of three
terminal positive regulators are available in the
TO-220/D-PAK package and with several fixed output
voltages, making them useful in a wide range of
applications. Each type employs internal current limiting,
thermal shut down and safe operating area protection,
making it essentially indestructible. If adequate heat sinking
is provided, they can deliver over 1A output current.
Although designed primarily as fixed voltage regulators,
these devices can be used with external components to
obtain adjustable voltages and currents.
Output Current up to 1A
Output Voltages of 5, 6, 8, 9, 10, 12, 15, 18, 24V
Thermal Overload Protection
Short Circuit Protection
Output Transistor Safe Operating Area Protection
TO-220
1
D-PAK
1
1. Input 2. GND 3. Output
Internal Block Digram
Rev. 1.0.1
©2001 Fairchild Semiconductor Corporation
MC78XX/LM78XX/MC78XXA
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
VI
VI
35
40
V
V
RθJC
5
Input Voltage (for VO = 5V to 18V)
(for VO = 24V)
Thermal Resistance Junction-Cases (TO-220)
o
C/W
oC/W
Thermal Resistance Junction-Air (TO-220)
RθJA
65
Operating Temperature Range
TOPR
0 ~ +125
o
-65 ~ +150
o
Storage Temperature Range
TSTG
C
C
Electrical Characteristics (MC7805/LM7805)
(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI = 10V, CI= 0.33µF, CO= 0.1µF, unless otherwise specified)
Parameter
Output Voltage
Symbol
VO
Conditions
MC7805/LM7805
Min.
Typ.
Max.
TJ =+25 oC
4.8
5.0
5.2
5.0mA ≤ Io ≤ 1.0A, PO ≤ 15W
VI = 7V to 20V
4.75
5.0
5.25
VO = 7V to 25V
-
4.0
100
VI = 8V to 12V
-
1.6
50
IO = 5.0mA to1.5A
-
9
100
IO =250mA to
750mA
-
4
50
Unit
V
Line Regulation (Note1)
Regline
TJ=+25 oC
Load Regulation (Note1)
Regload
TJ=+25 oC
IQ
TJ =+25 oC
-
5.0
8.0
IO = 5mA to 1.0A
-
0.03
0.5
VI= 7V to 25V
-
0.3
1.3
IO= 5mA
-
-0.8
-
mV/ oC
-
42
-
µV/Vo
62
73
-
dB
IO = 1A, TJ =+25 oC
-
2
-
V
f = 1KHz
-
15
-
mΩ
-
230
-
mA
-
2.2
-
A
Quiescent Current
Quiescent Current Change
Output Voltage Drift
∆IQ
∆VO/∆T
Output Noise Voltage
VN
f = 10Hz to 100KHz, TA=+25 oC
Ripple Rejection
RR
f = 120Hz
VO = 8V to 18V
Dropout Voltage
VDrop
Output Resistance
Short Circuit Current
Peak Current
rO
ISC
VI = 35V, TA =+25
IPK
o
TJ =+25 C
oC
mV
mV
mA
mA
Note:
1. Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
2
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7806)
(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =11V, CI= 0.33µF, CO= 0.1µF, unless otherwise specified)
Parameter
Output Voltage
Symbol
VO
Conditions
MC7806
Min.
Typ.
Max.
TJ =+25 oC
5.75
6.0
6.25
5.0mA ≤ IO ≤ 1.0A, PO ≤ 15W
VI = 8.0V to 21V
5.7
6.0
6.3
VI = 8V to 25V
-
5
120
VI = 9V to 13V
-
1.5
60
IO =5mA to 1.5A
-
9
120
IO =250mA to750A
-
3
60
Unit
V
Line Regulation (Note1)
Regline
TJ =+25 oC
Load Regulation (Note1)
Regload
TJ =+25 oC
IQ
TJ =+25 oC
-
5.0
8.0
IO = 5mA to 1A
-
-
0.5
VI = 8V to 25V
-
-
1.3
IO = 5mA
-
-0.8
-
mV/ oC
VN
f = 10Hz to 100KHz, TA =+25 oC
-
45
-
µV/Vo
Ripple Rejection
RR
f = 120Hz
VI = 9V to 19V
59
75
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ =+25 oC
-
2
-
V
f = 1KHz
-
19
-
mΩ
-
250
-
mA
-
2.2
-
A
Quiescent Current
Quiescent Current Change
Output Voltage Drift
Output Noise Voltage
Output Resistance
∆IQ
∆VO/∆T
rO
Short Circuit Current
ISC
VI= 35V, TA
Peak Current
IPK
TJ =+25 oC
=+25 oC
mV
mV
mA
mA
Note:
1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
3
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7808)
(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =14V, CI= 0.33µF, CO= 0.1µF, unless otherwise specified)
Parameter
Output Voltage
Symbol
VO
Conditions
MC7808
Min.
Typ. Max.
TJ =+25 oC
7.7
8.0
8.3
5.0mA ≤ IO ≤ 1.0A, PO ≤ 15W
VI = 10.5V to 23V
7.6
8.0
8.4
VI = 10.5V to 25V
-
5.0
160
VI = 11.5V to 17V
-
2.0
80
IO = 5.0mA to 1.5A
-
10
160
IO= 250mA to 750mA
-
5.0
80
Unit
V
Line Regulation (Note1)
Regline
TJ =+25 oC
Load Regulation (Note1)
Regload
TJ =+25 oC
IQ
TJ =+25 oC
-
5.0
8.0
IO = 5mA to 1.0A
-
0.05
0.5
VI = 10.5A to 25V
-
0.5
1.0
IO = 5mA
-
-0.8
-
mV/ oC
Quiescent Current
Quiescent Current Change
Output Voltage Drift
∆IQ
∆VO/∆T
mV
mV
mA
mA
Output Noise Voltage
VN
f = 10Hz to 100KHz, TA =+25 oC
-
52
-
µV/Vo
Ripple Rejection
RR
f = 120Hz, VI= 11.5V to 21.5V
56
73
-
dB
IO = 1A, TJ=+25 C
-
2
-
V
f = 1KHz
-
17
-
mΩ
-
230
-
mA
-
2.2
-
A
Dropout Voltage
Output Resistance
Short Circuit Current
Peak Current
VDrop
rO
ISC
IPK
o
VI= 35V, TA
o
TJ =+25 C
=+25 oC
Note:
1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
4
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7809)
(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =15V, CI= 0.33µF, CO= 0.1µF, unless otherwise specified)
Parameter
Output Voltage
Symbol
VO
Conditions
MC7809
Min.
Typ.
Max.
TJ =+25°C
8.65
9
9.35
5.0mA≤ IO ≤1.0A, PO ≤15W
VI= 11.5V to 24V
8.6
9
9.4
VI = 11.5V to 25V
-
6
180
VI = 12V to 17V
-
2
90
IO = 5mA to 1.5A
-
12
180
IO = 250mA to 750mA
-
4
90
Unit
V
mV
Line Regulation (Note1)
Regline
TJ=+25°C
Load Regulation (Note1)
Regload
TJ=+25°C
IQ
TJ=+25°C
-
5.0
8.0
IO = 5mA to 1.0A
-
-
0.5
VI = 11.5V to 26V
-
-
1.3
IO = 5mA
-
-1
-
mV/ °C
VN
f = 10Hz to 100KHz, TA =+25 °C
-
58
-
µV/Vo
RR
f = 120Hz
VI = 13V to 23V
56
71
-
dB
IO = 1A, TJ=+25°C
-
2
-
V
-
17
-
mΩ
Quiescent Current
Quiescent Current Change
Output Voltage Drift
Output Noise Voltage
Ripple Rejection
Dropout Voltage
∆IQ
∆VO/∆T
VDrop
mV
mA
mA
Output Resistance
rO
f = 1KHz
Short Circuit Current
ISC
VI= 35V, TA =+25°C
-
250
-
mA
Peak Current
IPK
TJ= +25°C
-
2.2
-
A
Note:
1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
5
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7810)
(Refer to test circuit ,0°C< TJ < 125°C, IO = 500mA, VI =16V, CI= 0.33µF, CO=0.1µF, unless otherwise specified)
Parameter
Output Voltage
Symbol
VO
Conditions
MC7810
Min.
Typ.
Max.
TJ =+25 °C
9.6
10
10.4
5.0mA ≤ IO≤1.0A, PO ≤15W
VI = 12.5V to 25V
9.5
10
10.5
VI = 12.5V to 25V
-
10
200
VI = 13V to 25V
-
3
100
IO = 5mA to 1.5A
-
12
200
IO = 250mA to 750mA
-
4
400
Unit
V
mV
Line Regulation (Note1)
Regline
TJ =+25°C
Load Regulation (Note1)
Regload
TJ =+25°C
IQ
TJ =+25°C
-
5.1
8.0
IO = 5mA to 1.0A
-
-
0.5
VI = 12.5V to 29V
-
-
1.0
IO = 5mA
-
-1
-
mV/°C
VN
f = 10Hz to 100KHz, TA =+25 °C
-
58
-
µV/Vo
Ripple Rejection
RR
f = 120Hz
VI = 13V to 23V
56
71
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ=+25 °C
-
2
-
V
Quiescent Current
Quiescent Current Change
Output Voltage Drift
Output Noise Voltage
∆IQ
∆VO/∆T
mV
mA
mA
Output Resistance
rO
f = 1KHz
-
17
-
mΩ
Short Circuit Current
ISC
VI = 35V, TA=+25 °C
-
250
-
mA
Peak Current
IPK
TJ =+25 °C
-
2.2
-
A
Note:
1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
6
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7812)
(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =19V, CI= 0.33µF, CO=0.1µF, unless otherwise specified)
Parameter
Symbol
Conditions
MC7812
Min.
Typ. Max.
Unit
TJ =+25 oC
11.5
12
12.5
5.0mA ≤ IO≤1.0A, PO≤15W
VI = 14.5V to 27V
11.4
12
12.6
VI = 14.5V to 30V
-
10
240
VI = 16V to 22V
-
3.0
120
IO = 5mA to 1.5A
-
11
240
IO = 250mA to 750mA
-
5.0
120
TJ =+25 oC
-
5.1
8.0
IO = 5mA to 1.0A
-
0.1
0.5
VI = 14.5V to 30V
-
0.5
1.0
IO = 5mA
-
-1
-
mV/ oC
VN
f = 10Hz to 100KHz, TA =+25 oC
-
76
-
µV/Vo
Ripple Rejection
RR
f = 120Hz
VI = 15V to 25V
55
71
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ=+25 oC
-
2
-
V
f = 1KHz
-
18
-
mΩ
-
230
-
mA
-
2.2
-
A
Output Voltage
VO
TJ =+25 oC
Line Regulation (Note1)
Regline
Load Regulation (Note1)
Regload TJ =+25 oC
Quiescent Current
Quiescent Current Change
Output Voltage Drift
Output Noise Voltage
Output Resistance
IQ
∆IQ
∆VO/∆T
rO
Short Circuit Current
ISC
VI = 35V, TA
Peak Current
IPK
TJ = +25 oC
=+25 oC
V
mV
mV
mA
mA
Note:
1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
7
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7815)
(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =23V, CI= 0.33µF, CO=0.1µF, unless otherwise specified)
Parameter
Output Voltage
Symbol
VO
MC7815
Conditions
Min.
Typ.
Max.
TJ =+25 oC
14.4
15
15.6
5.0mA ≤ IO ≤ 1.0A, PO ≤ 15W
VI = 17.5V to 30V
14.25
15
15.75
VI = 17.5V to 30V
-
11
300
VI = 20V to 26V
-
3
150
IO = 5mA to 1.5A
-
12
300
IO = 250mA to
750mA
-
4
150
Unit
V
Line Regulation (Note1)
Regline
TJ =+25 oC
Load Regulation (Note1)
Regload
TJ =+25 oC
IQ
TJ =+25 oC
-
5.2
8.0
IO = 5mA to 1.0A
-
-
0.5
VI = 17.5V to 30V
-
-
1.0
-
-1
-
mV/ oC
-
90
-
µV/Vo
Quiescent Current
Quiescent Current Change
Output Voltage Drift
∆IQ
∆VO/∆T
IO = 5mA
o
mV
mV
mA
mA
Output Noise Voltage
VN
f = 10Hz to 100KHz, TA =+25 C
Ripple Rejection
RR
f = 120Hz
VI = 18.5V to 28.5V
54
70
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ=+25 oC
-
2
-
V
Output Resistance
rO
f = 1KHz
-
19
-
mΩ
Short Circuit Current
ISC
VI = 35V, TA=+25 oC
-
250
-
mA
-
2.2
-
A
Peak Current
IPK
o
TJ =+25 C
Note:
1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
8
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7818)
(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =27V, CI= 0.33µF, CO=0.1µF, unless otherwise specified)
Parameter
Symbol
Conditions
MC7818
Min.
Typ. Max.
Unit
TJ =+25 oC
17.3
18
18.7
5.0mA ≤ IO ≤1.0A, PO ≤15W
VI = 21V to 33V
17.1
18
18.9
VI = 21V to 33V
-
15
360
VI = 24V to 30V
-
5
180
IO = 5mA to 1.5A
-
15
360
IO = 250mA to 750mA
-
5.0
180
TJ =+25 oC
-
5.2
8.0
IO = 5mA to 1.0A
-
-
0.5
VI = 21V to 33V
-
-
1
IO = 5mA
-
-1
-
mV/ oC
VN
f = 10Hz to 100KHz, TA =+25 oC
-
110
-
µV/Vo
Ripple Rejection
RR
f = 120Hz
VI = 22V to 32V
53
69
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ=+25 oC
-
2
-
V
f = 1KHz
-
22
-
mΩ
-
250
-
mA
-
2.2
-
A
Output Voltage
VO
TJ =+25 oC
Line Regulation (Note1)
Regline
Load Regulation (Note1)
Regload TJ =+25 oC
Quiescent Current
Quiescent Current Change
Output Voltage Drift
Output Noise Voltage
Output Resistance
IQ
∆IQ
∆VO/∆T
rO
Short Circuit Current
ISC
VI = 35V, TA
Peak Current
IPK
TJ =+25 oC
=+25 oC
V
mV
mV
mA
mA
Note:
1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
9
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7824)
(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =33V, CI= 0.33µF, CO=0.1µF, unless otherwise specified)
Parameter
Symbol
Conditions
TJ =+25 oC
Output Voltage
VO
MC7824
Min.
Typ. Max.
23
24
25
22.8
24
25.25
VI = 27V to 38V
-
17
480
VI = 30V to 36V
-
6
240
IO = 5mA to 1.5A
-
15
480
IO = 250mA to 750mA
-
5.0
240
5.0mA ≤ IO ≤ 1.0A, PO ≤ 15W
VI = 27V to 38V
Unit
V
Line Regulation (Note1)
Regline
TJ =+25 oC
Load Regulation (Note1)
Regload
TJ =+25 oC
IQ
TJ =+25 oC
-
5.2
8.0
IO = 5mA to 1.0A
-
0.1
0.5
VI = 27V to 38V
-
0.5
1
IO = 5mA
-
-1.5
-
mV/ oC
VN
f = 10Hz to 100KHz, TA =+25 oC
-
60
-
µV/Vo
Ripple Rejection
RR
f = 120Hz
VI = 28V to 38V
50
67
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ=+25 oC
-
2
-
V
f = 1KHz
-
28
-
mΩ
-
230
-
mA
-
2.2
-
A
Quiescent Current
Quiescent Current Change
Output Voltage Drift
Output Noise Voltage
Output Resistance
∆IQ
∆VO/∆T
rO
Short Circuit Current
ISC
VI = 35V, TA=+25
Peak Current
IPK
TJ =+25 oC
oC
mV
mV
mA
mA
Note:
1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
10
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7805A)
(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I = 10V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
4.9
5
5.1
4.8
5
5.2
VI = 7.5V to 25V
IO = 500mA
-
5
50
VI = 8V to 12V
-
3
50
VI= 7.3V to 20V
-
5
50
VI= 8V to 12V
TJ =+25
Output Voltage
Line Regulation (Note1)
VO
Regline
oC
IO = 5mA to 1A, PO ≤ 15W
VI = 7.5V to 20V
TJ =+25 oC
Load Regulation (Note1)
Quiescent Current
Quiescent Current
Change
Regload
IQ
-
1.5
25
TJ =+25 oC
IO = 5mA to 1.5A
-
9
100
IO = 5mA to 1A
-
9
100
IO = 250mA to 750mA
-
4
50
TJ =+25
oC
∆V/∆T
mV
mV
-
5.0
6
-
0.5
-
-
0.8
-
-
0.8
Io = 5mA
-
-0.8
-
mV/ oC
VI = 8 V to 25V, IO = 500mA
VI = 7.5V to 20V, TJ =+25
Output Voltage Drift
V
-
IO = 5mA to 1A
∆IQ
Unit
oC
mA
mA
Output Noise Voltage
VN
f = 10Hz to 100KHz
TA =+25 oC
-
10
-
µV/Vo
Ripple Rejection
RR
f = 120Hz, IO = 500mA
VI = 8V to 18V
-
68
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ =+25 oC
-
2
-
V
f = 1KHz
-
17
-
mΩ
-
250
-
mA
-
2.2
-
A
Output Resistance
rO
Short Circuit Current
ISC
VI= 35V, TA
Peak Current
IPK
TJ= +25 oC
=+25 oC
Note:
1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
11
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7806A)
(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I =11V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
5.58
6
6.12
5.76
6
6.24
VI= 8.6V to 25V
IO = 500mA
-
5
60
VI= 9V to 13V
-
3
60
VI= 8.3V to 21V
-
5
60
VI= 9V to 13V
TJ =+25
Output Voltage
Line Regulation (Note1)
VO
Regline
oC
IO = 5mA to 1A, PO ≤ 15W
VI = 8.6V to 21V
TJ =+25 oC
Load Regulation (Note1)
Quiescent Current
Regload
IQ
-
1.5
30
TJ =+25 oC
IO = 5mA to 1.5A
-
9
100
IO = 5mA to 1A
-
4
100
IO = 250mA to 750mA
-
5.0
50
TJ =+25
oC
∆IQ
∆V/∆T
mV
mV
-
4.3
6
-
0.5
VI = 9V to 25V, IO = 500mA
-
-
0.8
=+25 oC
-
-
0.8
IO = 5mA
-
-0.8
-
mV/ oC
VI= 8.5V to 21V, TJ
Output Voltage Drift
V
-
IO = 5mA to 1A
Quiescent Current Change
Unit
mA
mA
Output Noise Voltage
VN
f = 10Hz to 100KHz
TA =+25 oC
-
10
-
µV/Vo
Ripple Rejection
RR
f = 120Hz, IO = 500mA
VI = 9V to 19V
-
65
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ =+25 oC
-
2
-
V
f = 1KHz
-
17
-
mΩ
-
250
-
mA
-
2.2
-
A
Output Resistance
rO
Short Circuit Current
ISC
VI= 35V, TA
Peak Current
IPK
TJ=+25 oC
=+25 oC
Note:
1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
12
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7808A)
(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I = 14V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
TJ =+25 C
7.84
8
8.16
IO = 5mA to 1A, PO ≤15W
VI = 10.6V to 23V
7.7
8
8.3
-
6
80
o
Output Voltage
VO
VI= 10.6V to 25V
IO = 500mA
Line Regulation (Note1)
Regline
VI= 11V to 17V
-
3
80
VI= 10.4V to 23V
-
6
80
VI= 11V to 17V
-
2
40
TJ =+25 C
IO = 5mA to 1.5A
-
12
100
IO = 5mA to 1A
-
12
100
IO = 250mA to 750mA
-
5
50
TJ =+25 C
-
5.0
6
IO = 5mA to 1A
-
-
0.5
-
-
0.8
TJ =+25 oC
Unit
V
mV
o
Load Regulation (Note1)
Quiescent Current
Quiescent Current Change
Regload
IQ
∆IQ
o
VI = 11V to 25V, IO = 500mA
o
Output Voltage Drift
∆V/∆T
mV
mA
mA
VI= 10.6V to 23V, TJ =+25 C
-
-
0.8
IO = 5mA
-
-0.8
-
mV/ oC
Output Noise Voltage
VN
f = 10Hz to 100KHz
TA =+25 oC
-
10
-
µV/Vo
Ripple Rejection
RR
f = 120Hz, IO = 500mA
VI = 11.5V to 21.5V
-
62
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ =+25 oC
-
2
-
V
Output Resistance
rO
f = 1KHz
-
18
-
mΩ
Short Circuit Current
ISC
VI= 35V, TA =+25 oC
-
250
-
mA
-
2.2
-
A
Peak Current
IPK
o
TJ=+25 C
Note:
1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
13
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7809A)
(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I = 15V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
8.82
9.0
9.18
8.65
9.0
9.35
VI= 11.7V to 25V
IO = 500mA
-
6
90
VI= 12.5V to 19V
-
4
45
VI= 11.5V to 24V
-
6
90
VI= 12.5V to 19V
TJ
Output Voltage
Line Regulation (Note1)
VO
Regline
=+25°C
IO = 5mA to 1A, PO≤15W
VI = 11.2V to 24V
TJ =+25°C
Load Regulation (Note1)
Quiescent Current
Quiescent Current Change
Output Voltage Drift
Regload
IQ
∆IQ
∆V/∆T
-
2
45
TJ =+25°C
IO = 5mA to 1.0A
-
12
100
IO = 5mA to 1.0A
-
12
100
IO = 250mA to 750mA
-
5
50
TJ
=+25 °C
Unit
V
mV
mV
-
5.0
6.0
VI = 11.7V to 25V, TJ=+25 °C
-
-
0.8
mA
VI = 12V to 25V, IO = 500mA
-
-
0.8
IO = 5mA to 1.0A
-
-
0.5
IO = 5mA
-
-1.0
-
mV/ °C
mA
Output Noise Voltage
VN
f = 10Hz to 100KHz
TA =+25 °C
-
10
-
µV/Vo
Ripple Rejection
RR
f = 120Hz, IO = 500mA
VI = 12V to 22V
-
62
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ =+25 °C
-
2.0
-
V
f = 1KHz
-
17
-
mΩ
-
250
-
mA
-
2.2
-
A
Output Resistance
rO
Short Circuit Current
ISC
VI= 35V, TA
Peak Current
IPK
TJ=+25°C
=+25 °C
Note:
1. Load and line regulation are specified at constant, junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
14
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7810A)
(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I = 16V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
9.8
10
10.2
9.6
10
10.4
VI= 12.8V to 26V
IO = 500mA
-
8
100
VI= 13V to 20V
-
4
50
VI= 12.5V to 25V
-
8
100
VI= 13V to 20V
TJ
Output Voltage
Line Regulation (Note1)
VO
Regline
=+25°C
IO = 5mA to 1A, PO ≤ 15W
VI =12.8V to 25V
TJ =+25 °C
Load Regulation (Note1)
Quiescent Current
Quiescent Current Change
Output Voltage Drift
Regload
IQ
∆IQ
∆V/∆T
-
3
50
TJ =+25 °C
IO = 5mA to 1.5A
-
12
100
IO = 5mA to 1.0A
-
12
100
IO = 250mA to 750mA
-
5
50
TJ
=+25 °C
-
5.0
6.0
VI = 13V to 26V, TJ=+25 °C
-
-
0.5
VI = 12.8V to 25V, IO = 500mA
-
-
0.8
IO = 5mA to 1.0A
-
-
0.5
IO = 5mA
-
-1.0
-
Unit
V
mV
mV
mA
mA
mV/ °C
µV/Vo
Output Noise Voltage
VN
f = 10Hz to 100KHz
TA =+25 °C
-
10
-
Ripple Rejection
RR
f = 120Hz, IO = 500mA
VI = 14V to 24V
-
62
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ =+25°C
-
2.0
-
V
f = 1KHz
-
17
-
mΩ
-
250
-
mA
-
2.2
-
A
Output Resistance
rO
Short Circuit Current
ISC
VI= 35V, TA
Peak Current
IPK
TJ=+25 °C
=+25 °C
Note:
1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
15
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7812A)
(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I = 19V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
11.75
12
12.25
11.5
12
12.5
VI= 14.8V to 30V
IO = 500mA
-
10
120
VI= 16V to 22V
-
4
120
VI= 14.5V to 27V
-
10
120
VI= 16V to 22V
TJ
Output Voltage
Line Regulation (Note1)
VO
Regline
=+25 °C
IO = 5mA to 1A, PO ≤15W
VI = 14.8V to 27V
TJ =+25 °C
Load Regulation (Note1)
Quiescent Current
Quiescent Current Change
Output Voltage Drift
Regload
IQ
∆IQ
∆V/∆T
-
3
60
TJ =+25 °C
IO = 5mA to 1.5A
-
12
100
IO = 5mA to 1.0A
-
12
100
IO = 250mA to 750mA
-
5
50
-
5.1
6.0
TJ
=+25°C
Unit
V
mV
mV
mA
VI = 15V to 30V, TJ=+25 °C
-
0.8
VI = 14V to 27V, IO = 500mA
-
0.8
IO = 5mA to 1.0A
-
0.5
IO = 5mA
-
-1.0
-
mV/°C
mA
Output Noise Voltage
VN
f = 10Hz to 100KHz
TA =+25°C
-
10
-
µV/Vo
Ripple Rejection
RR
f = 120Hz, IO = 500mA
VI = 14V to 24V
-
60
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ =+25°C
-
2.0
-
V
f = 1KHz
-
18
-
mΩ
-
250
-
mA
-
2.2
-
A
Output Resistance
rO
Short Circuit Current
ISC
VI= 35V, TA
Peak Current
IPK
TJ=+25 °C
=+25 °C
Note:
1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
16
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7815A)
(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I =23V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
14.7
15
15.3
14.4
15
15.6
VI= 17.9V to 30V
IO = 500mA
-
10
150
VI= 20V to 26V
-
5
150
VI= 17.5V to 30V
-
11
150
VI= 20V to 26V
TJ
Output Voltage
Line Regulation (Note1)
VO
Regline
=+25 °C
IO = 5mA to 1A, PO ≤15W
VI = 17.7V to 30V
TJ =+25°C
Load Regulation (Note1)
Quiescent Current
Quiescent Current Change
Output Voltage Drift
Regload
IQ
∆IQ
∆V/∆T
-
3
75
TJ =+25 °C
IO = 5mA to 1.5A
-
12
100
IO = 5mA to 1.0A
-
12
100
IO = 250mA to 750mA
-
5
50
TJ
=+25 °C
Unit
V
mV
mV
-
5.2
6.0
VI = 17.5V to 30V, TJ =+25 °C
-
-
0.8
mA
VI = 17.5V to 30V, IO = 500mA
-
-
0.8
IO = 5mA to 1.0A
-
-
0.5
IO = 5mA
-
-1.0
-
mV/°C
mA
Output Noise Voltage
VN
f = 10Hz to 100KHz
TA =+25 °C
-
10
-
µV/Vo
Ripple Rejection
RR
f = 120Hz, IO = 500mA
VI = 18.5V to 28.5V
-
58
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ =+25 °C
-
2.0
-
V
f = 1KHz
-
19
-
mΩ
-
250
-
mA
-
2.2
-
A
Output Resistance
rO
Short Circuit Current
ISC
VI= 35V, TA
Peak Current
IPK
TJ=+25°C
=+25 °C
Note:
1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
17
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7818A)
(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I = 27V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
17.64
18
18.36
17.3
18
18.7
VI= 21V to 33V
IO = 500mA
-
15
180
VI= 21V to 33V
-
5
180
VI= 20.6V to 33V
-
15
180
VI= 24V to 30V
TJ
Output Voltage
Line Regulation (Note1)
VO
Regline
=+25 °C
IO = 5mA to 1A, PO ≤15W
VI = 21V to 33V
TJ =+25 °C
Load Regulation (Note1)
Quiescent Current
Quiescent Current Change
Output Voltage Drift
Regload
IQ
∆IQ
∆V/∆T
-
5
90
TJ =+25°C
IO = 5mA to 1.5A
-
15
100
IO = 5mA to 1.0A
-
15
100
IO = 250mA to 750mA
-
7
50
TJ
=+25 °C
-
5.2
6.0
VI = 21V to 33V, TJ=+25 °C
-
-
0.8
VI = 21V to 33V, IO = 500mA
-
-
0.8
IO = 5mA to 1.0A
-
-
0.5
IO = 5mA
-
-1.0
-
Unit
V
mV
mV
mA
mA
mV/ °C
µV/Vo
Output Noise Voltage
VN
f = 10Hz to 100KHz
TA =+25°C
-
10
-
Ripple Rejection
RR
f = 120Hz, IO = 500mA
VI = 22V to 32V
-
57
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ =+25°C
-
2.0
-
V
f = 1KHz
-
19
-
mΩ
-
250
-
mA
-
2.2
-
A
Output Resistance
rO
Short Circuit Current
ISC
VI= 35V, TA
Peak Current
IPK
TJ=+25 °C
=+25°C
Note:
1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
18
MC78XX/LM78XX/MC78XXA
Electrical Characteristics (MC7824A)
(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I = 33V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
23.5
24
24.5
23
24
25
VI= 27V to 38V
IO = 500mA
-
18
240
VI= 21V to 33V
-
6
240
VI= 26.7V to 38V
-
18
240
VI= 30V to 36V
TJ
Output Voltage
Line Regulation (Note1)
VO
Regline
=+25 °C
IO = 5mA to 1A, PO ≤15W
VI = 27.3V to 38V
TJ =+25 °C
Load Regulation (Note1)
Quiescent Current
Quiescent Current Change
Output Voltage Drift
Regload
IQ
∆IQ
∆V/∆T
-
6
120
TJ =+25 °C
IO = 5mA to 1.5A
-
15
100
IO = 5mA to 1.0A
-
15
100
IO = 250mA to 750mA
-
7
50
TJ
=+25 °C
Unit
V
mV
mV
-
5.2
6.0
VI = 27.3V to 38V, TJ =+25 °C
-
-
0.8
mA
VI = 27.3V to 38V, IO = 500mA
-
-
0.8
IO = 5mA to 1.0A
-
-
0.5
IO = 5mA
-
-1.5
-
mV/ °C
mA
Output Noise Voltage
VN
f = 10Hz to 100KHz
TA = 25 °C
-
10
-
µV/Vo
Ripple Rejection
RR
f = 120Hz, IO = 500mA
VI = 28V to 38V
-
54
-
dB
Dropout Voltage
VDrop
IO = 1A, TJ =+25 °C
-
2.0
-
V
f = 1KHz
-
20
-
mΩ
-
250
-
mA
-
2.2
-
A
Output Resistance
rO
Short Circuit Current
ISC
VI= 35V, TA
Peak Current
IPK
TJ=+25 °C
=+25 °C
Note:
1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
19
MC78XX/LM78XX/MC78XXA
Typical Perfomance Characteristics
I
20
Figure 1. Quiescent Current
Figure 2. Peak Output Current
Figure 3. Output Voltage
Figure 4. Quiescent Current
MC78XX/LM78XX/MC78XXA
Typical Applications
MC78XX/LM78XX
Input
Output
Figure 5. DC Parameters
MC78XX/LM78XX
Input
Output
Figure 6. Load Regulation
MC78XX/LM78XX
Input
Output
Figure 7. Ripple Rejection
Input
MC78XX/LM78XX
Output
Figure 8. Fixed Output Regulator
21
MC78XX/LM78XX/MC78XXA
MC78XX/LM78XX
Input
Output
CI
Co
Figure 9. Constant Current Regulator
Notes:
(1) To specify an output voltage. substitute voltage value for "XX." A common ground is required between the input and the
Output voltage. The input voltage must remain typically 2.0V above the output voltage even during the low point on the input
ripple voltage.
(2) CI is required if regulator is located an appreciable distance from power Supply filter.
(3) CO improves stability and transient response.
Output
Input
MC78XX/LM78XX
CI
Co
I RI ≥ 5IQ
VO = VXX(1+R2/R1)+IQR2
Figure 10. Circuit for Increasing Output Voltage
Input
CI
Output
MC7805
LM7805
LM741
Co
IRI ≥5 IQ
VO = VXX(1+R2/R1)+IQR2
Figure 11. Adjustable Output Regulator (7 to 30V)
22
MC78XX/LM78XX/MC78XXA
Input
Output
MC78XX/LM78XX
Figure 12. High Current Voltage Regulator
Input
MC78XX/LM78XX
Output
Figure 13. High Output Current with Short Circuit Protection
MC78XX/LM78XX
LM741
Figure 14. Tracking Voltage Regulator
23
MC78XX/LM78XX/MC78XXA
MC7815
MC7915
Figure 15. Split Power Supply ( ±15V-1A)
Output
Input
MC78XX/LM78XX
Figure 16. Negative Output Voltage Circuit
Output
Input
MC78XX/LM78XX
Figure 17. Switching Regulator
24
MC78XX/LM78XX/MC78XXA
Mechanical Dimensions
Package
TO-220
4.50 ±0.20
2.80 ±0.10
(3.00)
+0.10
1.30 –0.05
18.95MAX.
(3.70)
ø3.60 ±0.10
15.90 ±0.20
1.30 ±0.10
(8.70)
(1.46)
9.20 ±0.20
(1.70)
9.90 ±0.20
(45°
1.52 ±0.10
0.80 ±0.10
2.54TYP
[2.54 ±0.20]
10.08 ±0.30
(1.00)
13.08 ±0.20
)
1.27 ±0.10
+0.10
0.50 –0.05
2.40 ±0.20
2.54TYP
[2.54 ±0.20]
10.00 ±0.20
25
MC78XX/LM78XX/MC78XXA
Mechancal Dimensions (Continued)
Package
D-PAK
MIN0.55
0.91 ±0.10
9.50 ±0.30
0.50 ±0.10
0.76 ±0.10
0.50 ±0.10
1.02 ±0.20
2.30TYP
[2.30±0.20]
(3.05)
(2XR0.25)
(0.10)
2.70 ±0.20
6.10 ±0.20
9.50 ±0.30
0.76 ±0.10
26
(1.00)
6.60 ±0.20
(5.34)
(5.04)
(1.50)
(0.90)
2.30 ±0.20
(0.70)
2.30TYP
[2.30±0.20]
(0.50)
2.30 ±0.10
0.89 ±0.10
MAX0.96
(4.34)
2.70 ±0.20
0.80 ±0.20
0.60 ±0.20
(0.50)
6.10 ±0.20
5.34 ±0.30
0.70 ±0.20
6.60 ±0.20
MC78XX/LM78XX/MC78XXA
Ordering Information
Product Number
Output Voltage Tolerance
Package
Operating Temperature
LM7805CT
±4%
TO-220
0 ~ + 125°C
Product Number
Output Voltage Tolerance
Package
Operating Temperature
MC7805CT
MC7806CT
MC7808CT
MC7809CT
MC7810CT
TO-220
MC7812CT
MC7815CT
MC7818CT
±4%
MC7824CT
MC7805CDT
MC7806CDT
MC7808CDT
D-PAK
MC7809CDT
0 ~ + 125°C
MC7810CDT
MC7812CDT
MC7805ACT
MC7806ACT
MC7808ACT
MC7809ACT
MC7810ACT
±2%
TO-220
MC7812ACT
MC7815ACT
MC7818ACT
MC7824ACT
27
MC78XX/LM78XX/MC78XXA
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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