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Computer Organization
Que : 1. What is CPU Chip ? Explain Different types of CPU chips.
Introduction to memory chips:
Memory chips are integrated circuits that are capable of storing information. Today, memory chips can
be found on RAM and integrated on devices such as your computer video card. In the below picture, is
an example of a 512MB DIMM RAM with eight visible memory chips integrated on the circuit board.
Pentium :I
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Fifth generation of x86 family, Intel Pentium microprocessor was the first x86 superscalar CPU. The
processor included two pipelined integer units which could execute up to two integer instructions per
CPU cycle. Redesigned Floating Point Unit considerably improved performance of floating-point
operations and could execute up to 1 FP instruction per CPU cycle. Other enhancements to Pentium
core included:
To improve data transfer rates the size of data bus was increased to 64 bits.
At first Pentium processors featured separate 8 KB code and 8 KB data caches. The size of both data and
code L1 caches was doubled in Pentium processors with MMX technology.
Intel Pentium CPU used branch prediction to improve effectiveness of pipeline architecture. Branch
prediction was enhanced in Pentium MMX processors.
Many desktop Pentiums could work in dual-processor systems.
To reduce CPU power consumption the core voltage was reduced on all Pentium MMX, and many
mobile and embedded Pentium processors.
Intel manufactured desktop, mobile and embedded versions of Pentium microprocessors. Distinguishing
between different versions of Pentiums is not always easy because desktop, mobile and/or embedded
Pentiums often used the same part numbers. In some cases Pentium processors with the same part and
S-spec numbers were offered as desktop and embedded, or mobile and embedded microprocessors.
Later versions of Pentium processors - Pentium MMX - included 57 new instructions. These instructions
could be used to speed up processing of multimedia and communication applications. Like the Pentium
processors, the Penium MMX CPUs were also produced in three different versions - desktop, mobile and
embedded processors.
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Unit :5
Advanced Digital Organization of Computer
Pentium 60 MHz microprocessor was the first from Pentium series, and it was the slowest one. The CPU
was shipped in pin grid array package similar to 80486 - the CPU bottom side looked like a bigger version
of 80486. Like older 80486 processors, the Pentium 60 required 5 Volt. High core voltage and big die size
were the primary reasons of the processor running very hot even with factory supplied heatsink. Short
term fix for this problem was adding an integrated heatspreader that helped to dissipate the heat (see
other pictures). The heat problem was solved in the next generation of Pentium chips by switching from
0.8 micron to 0.6 micron manufacturing process, and reducing core voltage to 3.3 Volt.
Pentium: II
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Intel Pentium II line of processors is based on sixth generation x86 processor core. The Intel Pentium II
line consists of 6 different families:
Pentium Pro - high perfomance version. The Pentium Pro family was replaced by the Pentium II Xeon
family.
Pentium II - desktop family.
Mobile Pentium II - mobile version of the Pentium II processor.
Pentium II Xeon - high performance version.
Desktop Celeron - low-cost version.
Mobile Celeron - mobile version of Intel Celeron processor.
Pentium: III
Pentium III microprocessor family was an evolutionary upgrade from Pentium II. The first Pentium III
core, Katmai, featured SSE instruction set, which allowed SSE-enabled applications to process up to four
single-precision floating point numbers at once. Other Pentium 3 cores added other features, like 256
and 512 KB on-die L2 cache memory and smaller package size. During its lifetime, the core of Pentium III
microprocessors was shrunk twice - from 0.25 micron to 0.18 micron, and then to 0.13 micron.
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Like the previous generation of x86 processors, the Pentium III family consists of a few sub-families
targeting different segments of computer market:
Pentium III Xeon - high performance version.
Pentium III desktop processors - desktop computers.
Desktop Celeron - low-cost version.
Mobile Pentium III and mobile Pentium III-M - mobile versions of the Pentium III processor.
Mobile Celeron - mobile version of Intel Celeron processor.
ew generation of Intel Pentium III processors with Coppermine core featured not only better
manufacturing technology (0.18 micron as opposed to 0.25 micron for Katmai core), but also different
cache architecture and new package type. Smaller size of the new core allowed Intel to put level 2 cache
on the the same die as the core. While new cache was two times smaller than the L2 cache on Katmai
processors, it was twice as fast and had a few additional performance improvements. Because external
cache chips were no longer required for the new core, it became possible to put the core on smaller and
cheaper Flip-Chip Pin Grid Array package.
Que : 2. What is Computer Bus ? Explain bus clocking,arbitration,operation and width of bus.
COMPUTER BUSSES
When referring to a computer, the bus also known as the address bus, data bus, or local bus is a data
connection between two or more devices connected to the computer. For example, a bus enables a
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computer processor to communicate with the memory or a video card to communicate with the
memory
A bus is capable of being a parallel or serial bus and today all computers utilize two bus types, an
internal bus or local bus and an external bus, also called the expansion bus. An internal bus enables a
communication between internal components such as a computer video card and memory and an
external bus is capable of communicating with external components such as a USB or SCSI device.
A computer or device's bus speed or throughput is always measured in bits per second or megabytes per
second.
A bus is a common electrical pathway between multiple devices.
Can be internal to the CPU to transport data to and from the ALU.
Can be external to the CPU, to connect it to memory or to I/O devices.
Early PCs had a single external bus or system bus.
Modern PCs have a special-purpose bus between the CPU and memory and (at least) one other bus for
the I/O devices.
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In order to make it possible for boards designed by third parties to attach to the system
bus, there must be well-defined rules about how the bus works, and which all attached
devices must obey.
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These rules are called the bus protocol.
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In addition, there must be mechanical and electrical specifications.
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A number of buses are in widespread use in the computer world.
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Multibus (8086)
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IBM PC (PC/XT)
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ISA bus (PC/AT)
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EISA bus (80386)
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Microchannel (PS/2)
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PCI bus (Many PCs)
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Nubus (macintosh)
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Universal Serial Bus (modern PCs)
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FireWire (consumer electronics)
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Some devices that attach to a bus are active and can initiate bus transfers. They are
called masters.
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Some devices are passive and wait for requests. They are called slaves.
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Some devices may act as slaves at some times and masters at others.
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Memory can never be a master device.
The binary signals that computer devices output are frequently not strong enough to power a
chip.
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The bus may be relatively long or have several devices attached to it.
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Most bus masters are connected to the bus by a chip called a bus driver which is
essentially a digital amplifier.
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Most slaves are connected to the bus by a bus receiver.
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For devices which can be both master and slave, a device called a bus transceiver is
used.
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These bus interface devices are often tri-state devices to allow them to disconnect when
they are not needed.
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A bus has address, data, and control lines, but there is not necessarily a one-to-one
mapping between CPU pins and bus lines. A decoder chip between CPU and bus would
be needed in this case.
Bus width:
The more address lines a bus has, the more memory the CPU can address directly.
If a bus has n address lines, then the CPU can use it to address 2n different memory locations.
Larger buses are more expensive:
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they need more wires
they take up more space on the motherboard
they need bigger connectors
Early PC buses did not contain enough address lines leading several backward compatible
upgrades to the bus.
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The number of data lines needed also tends to increase over time.
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There are two ways to increase the data bandwidth of a bus:
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decrease the bus cycle time
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increase the data bus width
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Speeding up the bus results in problems of bus skew since data on individual lines travel
at slightly different speeds. This also makes the bus non-compatible with pre-existing
devices.
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Therefore, an increased data width is the usual answer (e.g. in the PC which went from 8
data lines to 16 and then to 32 on essentially the same bus).
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Another solution is to use a multiplexed bus.
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The same lines are used for both data and addressing by breaking up the bus operation
into multiple steps. This slows down bus performance.
Bus Clocking:
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Buses can be divided up into two categories depending on their clocking.
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A synchronous bus has a line driven by a crystal oscillator.
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The signal on this line consists of a square wave with a frequency of 5 - 100
MHz.
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All bus activities take an integral number of these cycles, called bus cycles.
The asynchronous bus does not have a master clock. Bus cycles can be of any length
required and need not be the same.
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Although synchronous buses are easy to work with due to their discrete time intervals,
they also have some problems.
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Everything works in multiples of the bus clock.
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If a CPU and memory can complete a transfer in 3.1 cycles they have to stretch
it to 4.0 because fractional cycles are forbidden.
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Once a bus cycle has been chosen, and memory and I/O cards have been built
for it, it is difficult to take advantage of future improvements in technology. The
bus has to be geared to the slowest devices (legacy devices) on the bus.
Mixed technology can be handled by going to an asynchronous bus.
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The master device asserts MREQ’, RD’, etc. and then asserts MSYN’ (Master
SYNchronization).
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Seeing this, the slave device starts to work.
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When it is finished it asserts SSYN’ (Slave SYNchronization).
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Seeing this, the master reads the data.
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When it is done, it negates MREQ’, RD’, the address lines, MSYN’ and SSYN’.
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This ends the read.
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A set of signals that interlocks in this way is called a full handshake.
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Full handshakes are timing independent. Each event is caused by a prior event, not by a
clock cycle.
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Despite the advantages of asynchronous buses, most buses are synchronous since they
are easier to build, and since there is such a large investment in synchronous bus
technology.
Bus Arbitration:
I/O chips have to become bus master to read and write memory and to cause interrupts.
If two or more devices want to become bus master at the same time, a bus arbitration mechanism is
needed.
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Arbitration mechanisms can be centralized or decentralized. A simple form of centralized arbitration is
shown on the next slide.
When the arbiter sees that one or more devices want to become master, it issues a grant by asserting
the bus grant line.
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In the first scheme shown, the closest device always wins.
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In the second scheme, there are multiple levels of priority. A device assert the line for its
priority, and the arbiter grants the request by asserting the line with the highest priority.
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Since the CPU must compete for the device on most every cycle (i.e. it must read a word
of memory) the memory is often put on a separate bus from the I/O devices so it
doesn’t have to compete.
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Decentralized bus arbitration is also possible.
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A computer could have 16 prioritized bus request lines. When a device wants to
use the bus, it assert its request line.
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All devices monitor all request lines, so at the end of each bus cycle, each device
knows whether it was the highest priority requester.
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This method avoids the necessity of an arbiter, but requires more bus lines.
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Another decentralized scheme equivalent to the daisy chain arbitration minus
the arbiter is shown on the following slide.
Bus Operations:
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Up until now, we have only considered ordinary bus cycles, with a master reading from
a slave or writing to one. In fact, several other kinds of bus cycles exist.
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Normally one word at a time is transferred. However, when caching is used it is often
desirable to fetch an entire cache line at once.
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Block transfers can often be more efficient than successive individual transfers.
The master puts the number of words to be transferred on the data lines during
the first bus cycle.
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Another important kind of bus cycle is for handling interrupts. When the CPU commands
an I/O device to do something, it usually expects an interrupt when the work is done.
The interrupt signaling requires the bus.
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Since multiple devices may want to cause an interrupt simultaneously, the same kind or
arbitration problems we had with ordinary bus cycles are present.
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The usual solution is to assign priorities and use a centralized arbiter.
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Standard interrupt controller chips exist and are widely used.
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The IBM PC and all its successors use the Intel 8259A chip.
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Up to eight I/O controllers can be directly connected to the eight IR inputs to the 8259A.
When one of these devices wants to cause an interrupt, it asserts its input line.
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When one or more interrupts are asserted, the 8259A asserts INT which drives
the interrupt pin on the CPU.
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When the CPU is able to handle the interrupt, it sends back a pulse on INTA.
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At that point, the 8259A specifies which input caused the interrupt by outputting the
input’s number on the data bus.
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The CPU uses that number to index into a table of pointers called interrupt vectors, to
find the address of the procedure to run to service the interrupt.
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Several 8259As can be cascaded to handle more than eight I/O devices.
Que : 3. Explain different types of computer buses.
Types of Bus
ISA BUS:
The original version of the ISA bus (Industry Standard Architecture) that appeared in 1981 with PC XT was an 8-bit
bus with a clock speed of 4.77 MHz.
In 1984, with the appearance of PC AT (the Intel 286 processor), the bit was expanded into a 16-bit bus and the clock
speed went from 6 to 8 MHz and finally to 8.33 MHz, offering a maximum transfer rate of 16 Mb/s (in practice only 8
Mb/s because one cycle out of every two was used for addressing).
The ISA bus permitted bus mastering, i.e. it enabled controllers connected directly to the bus to communicate directly
with the other peripherals without going through the processor. One of the consequences of bus mastering is direct
memory access (DMA). However, the ISA bus only allows hardware to address the first 16 megabytes of RAM.
Up until the end of the 1990s, almost all PC computers were equipped with the ISA bus, but it was progressively
replaced by the PCI bus, which offered a better performance.
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8-bit ISA Connector:
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16-bit ISA Connector:
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PCI BUS:
Short for Peripheral Component Interconnect, PCI was introduced by Intel in 1992, revised in 1993to version 2.0,
and later revised in 1995 to PCI 2.1 and is as an expansion to the ISA bus. The PCI bus is a 32-bit computer bus that
is also available as a 64-bit bus and was the most commonly found and used computer bus in computers during the
late 1990's and early 2000's. Today's computers have replace PCI with PCI-Express. Below is a graphic illustration of
the PCI slot on a motherboard.
PCI Connectors
At least 3 or 4 PCI connectors are generally present on motherboards and can generally be recognised by their
standardized white color.
The PCI interface exists in 32 bits with a 124-pin connector, or in 64 bits with a 188-pin connector. There are also two
signaling voltage levels:
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3.3V, for laptop computers
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5V, for desktop computers
The signaling voltage does not equal the voltage of the motherboard power supply but rather the voltage threshold for
the digital encryption of data.
There are 2 types of 32-bit connectors:
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32-bit PCI connector, 5V:
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32-bit PCI connector, 3.3V:
The 64-bit PCI connectors offer additional pins and can accommodate 32-bit PCI cards. There are 2 types of 64-bit
connectors:
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64-bit PCI connector, 5V:
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64-bit PCI connector, 3.3V:
USB Bus:
Short for Universal Serial Bus, USB is a standard that was introduced in 1995 by Intel, Compaq, Microsoft
and several other computer companies. USB 1.x is an external bus standard that supports data transfer
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rates of 12 Mbps and is capable of supporting up to 127 peripheral devices. In the picture to the right, is
an example of a USB cable being connected into the USB port.
USB 2.0, also known as hi-speed USB, was developed by Compaq, Hewlett Packard, Intel, Lucent,
Microsoft, NECand Philips and was introduced in 2001. Hi-speed USB is capable of supporting a transfer
rate of up to 480 Mbps and is backwards compatible, meaning it is capable of supporting USB 1.0 and
1.1 devices and cables.
As of 2012, USB 3.0 is the latest version of the USB protocol. Most new computers feature USB 3.0 ports
built-in, offering data transfer speeds of up to 5 gigabits per second. USB 3.0 improved upon the USB 2.0
technology with speed and performance increases, improved power management and increased
bandwidth capability (providing two unidirectional data paths for receiving and sending data at the
same time).
USB 3.0 devices were first made available in November 2009 by Buffalo Technology, but the first
certified devices weren't available until January 2010. The first certified devices included motherboards
from ASUS and Gigabyte Technology. Dell began including USB 3.0 ports in their Inspiron and Dell XPS
series of computers in April 2011. Today, many devices use the USB 3.0 revision for improved
performance and speed, including USB thumb drives, digital cameras, external hard drives, MP3 players,
and other devices.
USB devices
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Today, there are millions of different USB devices that can be connected to your computer. Below are
just a few of the more common USB devices you'll likely find and use.
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Camera
External drive
iPod or other MP3 player
Keyboard
Keypad
Microphone
Mouse
Printer
Joystick
Jump drive aka Thumb drive
Scanner
Webcams
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