Download Minimizing TRF79xx Current Use During Power‑Down Mode

Application Report
SLOA205 – August 2014
Minimizing TRF79xx Current Use During
Power‑Down Mode
Alexander Kozitsky ......................................................................... MCU Safety and Security Applications
ABSTRACT
NFC/RFID applications that are battery powered, such as digital door locks or portable terminals, need to
conserve as much power as possible in sleep mode to extend battery life. Because the TRF79xx
NFC/RFID transceiver generally spends a majority of its time in power-down mode in these applications,
optimizing current consumption while in this mode is very important.
This application report provides recommendations on circuit and firmware design to reduce current
consumption in power-down mode for the TRF79xx family of devices (TRF796x, TRF796xA, and
TRF7970A). Various designs are considered, and they are analyzed based on their current consumption.
This application report is particularly targeted for dual-voltage systems that are powered by battery.
1
2
3
4
5
Contents
Introduction ...................................................................................................................
Current Design Analysis ....................................................................................................
Low-Voltage MCU System..................................................................................................
Conclusion ....................................................................................................................
Schematics ...................................................................................................................
2
2
2
8
8
List of Figures
1
TRF79xx I/O 1 and 2 Connected to a Power Supply ................................................................... 3
2
TRF79xx I/O Impedance During EN = 0 .................................................................................. 3
3
Slave Select Pulled High.................................................................................................... 4
4
Example Case of Non-Digital Voltage on MCU I/O
5
Recommended Design ...................................................................................................... 6
6
Sleep and Wake Timings ................................................................................................... 7
7
Schematic ..................................................................................................................... 9
.....................................................................
5
List of Tables
1
Suggested States of TRF79xx I/O Bus During Power-Down Mode ................................................... 7
2
System Current Consumption .............................................................................................. 7
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1
Introduction
1
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Introduction
The key points that are addressed in this application report focus on obtaining the best power
performance. The examples included in this report use the MSP430F2370 and the TRF7964A. There
should not be any significant changes for the TRF7970A (or other TRF79xx variations).
The bus communication between the MCU and the TRF79xx is SPI with Slave Select (SS) in this
document. The parallel bus interface is not analyzed.
For the scope of this report, the terms power down and sleep are used interchangeably.
2
Current Design Analysis
The current TRF79xx EVM has the I/O_1 and I/O_2 pins pulled high with a 10-kΩ resistor on each pin,
selecting the SPI with SS mode (along with I/O_0 being connected to ground (GND) These pullups are
sourced from the VDD_X supply. VDD_X supply is not powered when EN = 0. Thus, these two I/O pins
slowly turn off as the VDD_X power decays. Refer to the TRF796x and TRF797x EVM schematic in
Section 5 for details.
When putting the TRF79xx into power-down mode, as long as Slave Select (SS) and MOSI are driven low
immediately, the resulting configuration is current efficient while in sleep mode (the MSP430 and TRF79xx
devices consume less than 1 µA).
However, there are systems where the MCU and TRF79xx are supplied by different voltage sources. For
example, in a battery-powered system, the TRF79xx may be powered by 3.3 V and the MCU by 2.8 V.
This configuration requires a different design for the system to safely operate.
3
Low-Voltage MCU System
When the MCU is running at a different voltage than the TRF79xx, generally this means that VDD_X must
be decoupled from the VDD_I/O pin. This is necessary because VDD_X on TRF79xx reset (EN = 0 then
EN = 1) sources VDD_X up to 3.4 V when EN = 1. Because the MCU in this example is a low-voltage
powered one, (in this case 2.8 V), this can exceed the MCU's absolute maximum voltage on the GPIOs
that are being driven by the TRF79xx device (MISO, IRQ).
This VDD_X voltage can be changed to a compatible voltage for the MCU (by configuring the Regulator
and I/O Control Register (TRF79xxA register 0x08). However, during the initial configuration, the MCU is
exposed to the higher voltage. If the MCU can tolerate the higher voltage, then the current EVM design
can be used with its low sleep currents in this multiple power source scenario.
3.1
Possible Non-Ideal Multiple Power Source Design
Figure 1 shows a design that draws extra current when in power-down mode (PDM) as compared to the
previous example. The reason is that the TRF79xx I/O is pulled down by 44-kΩ resistors internally when it
enters PDM (EN = 0, see Figure 2). Because the I/O_1 and I/O_2 are connected to a constantly driven
power rail in this example, there is current drawn from the power-rail through these pulldown resistors.
Therefore, it is important to make sure that these I/Os are high-impedance or are driven to ground to
achieve the lowest current consumption possible.
2
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2.8 V
VDD_I/O
VDD
3.3 V
Vin
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Current
I/O 2
I/O 1
I/O 0
TRF79xx
IRQ
(all other pins per
default recommended MOSI - I/O 8
connections)
MISO- I/O 7
GPIO
GPIO
MCU
GPIO
SS - I/O 4
GPIO
Data CLK
GPIO
EN
GPIO
EN2
GPIO
GND
GND
10k
10k
Figure 1. TRF79xx I/O 1 and 2 Connected to a Power Supply
TRF79xx
EN
I/O 0-7
44k
Figure 2. TRF79xx I/O Impedance During EN = 0
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Low-Voltage MCU System
3.2
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Slave Select (SS) Pulled-Up Design
In the design case where slave select (SS) is pulled high (see Figure 3), there is a certain disadvantage.
With SS pulled high, when EN = 0, there is current through the SS pullup through the internal pulldowns
on the TRF79xx.
As long as the EN and EN2 pins are pulled low, the SS pullup should not be required. As long as SS is
high when EN goes high, the TRF79xx can power up safely.
If the SS pullup design is used, it is recommended to have the MCU drive the SS line low, instead of to
high impedance, to prevent extra current being lost through the input buffer of the MCU due to the
intermediate voltage on that pin (0.86 V) (see Figure 4).
2.8 V
100k
VDD
VDD_I/O
Vin
3.3 V
GPIO - Digitally
Controllable
SS - I/O 4
GPIO
I/O 2
5k
I/O 1
I/O 0
TRF79xx
IRQ
(all other pins per
default recommended MOSI - I/O 8
connections)
MISO- I/O 7
GPIO
GPIO
GPIO
Data CLK
GPIO
EN
GPIO
EN2
GPIO
GND
MCU
GND
10k
10k
Figure 3. Slave Select Pulled High
4
Minimizing TRF79xx Current Use During Power‑Down Mode
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TRF79xx
EN
+2.8 V
(example)
MCU
100k
I/O 0-7
I/O
0.86 V
44k
Current path
Figure 4. Example Case of Non-Digital Voltage on MCU I/O
3.3
TRF79xx Sharing the SPI Bus
It is possible for the TRF79xx to share the SPI bus with another device. The TRF79xx must be disabled
(EN = Low) when the communication with the other device occurs. Because each of the I/O lines on the
TRF79xx is pulled low when EN = Low, the system incurs extra current on every high level of the MOSI,
MISO, and CLK signals. The current loss per pin is:
Current Loss = MCU Voltage / 44 kΩ
For example: 2.8 V / 44 kΩ = 64 µA
This is for a high level on a single line. When the SPI signal is low, no extra current is consumed.
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Low-Voltage MCU System
3.4
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Recommended Multiple Power Source Design
In Figure 5, the VDD_I/O can be powered constantly with no extra current loss in total power-down mode.
The reason it is recommended to have the I/O pins connected to an MCU is that they can be set low when
the TRF79xx EN = Low. This conserves current.
2.8 V
VDD_I/O
VDD
3.3 V
Vin
Also having control over EN2 is essential to a proper power up (for the TRF7970A). Refer to the
TRF7970A device data sheet (SLOS743) for more information.
GPIO - Digitally
Controllable
I/O 2
5k
I/O 1
I/O 0
TRF79xx
IRQ
(all other pins per
default recommended MOSI - I/O 8
connections)
MISO- I/O 7
GPIO
GPIO
MCU
GPIO
SS - I/O 4
GPIO
Data CLK
GPIO
EN
GPIO
EN2
GPIO
GND
GND
10k
10k
Figure 5. Recommended Design
6
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3.5
Recommended Voltage Levels in Power-Down Mode (EN = Low)
Table 1 shows the recommended settings for the TRF79xx I/O bus.
Table 1. Suggested States of TRF79xx I/O Bus During Power-Down Mode
I/O Pin
State
MISO, MOSI
(I/O_6, I/O_7)
(1)
3.6
Notes
Low or Hi-Z
(1)
Data Clock
Low or Hi-Z (1)
SS (I/O_4)
Low or Hi-Z (1)
I/O_0,1,2
Low or Hi-Z (1)
Hi-Z may draw extra current with a pullup resistor
Note there are no current differences between having the I/O bus driven low or set to high-impedance, except in the case with
SS pulled high.
Timings Section
Bus sharing during TRF79xx power-down state causes a slight increase in current due to the 44-kΩ
pulldown resistors active on the bus.
For the power-up sequence it is important that SS is high before the EN signal is set high (see Figure 6).
Enter TRF79xx
Power-Down State
EN
SS
I/O 1,2
MOSI x
MISO x
CLK
Shared SPI
Power-Up Sequence
x
x
x
rise time of SS, I/
O_1, and I/O_2
Figure 6. Sleep and Wake Timings
3.7
Power Measurements
An example case is given in Table 2 in which TRF79xx is powered by 3.3 V and the MCU is powered by
2.8 V. The pullup that is used in this example is 100 kΩ.
In Table 2, the state and current measurements are after EN and EN2 are set to Low.
Table 2. System Current Consumption
VDD_IO
During Power
Down (V)
SS Pullup
SS Drive
MOSI,
MISO, CLK
I/O 0,1,2
TRF7964A
3.3-V Rail
Current (µA)
MSP430 2.8-V
Rail Current
(µA)
Refer To
2.8
No pullup
Low
Low
All Low
<1
<1
Section 3.4
Hi-Z
No pullup
Low
Low
All Low
<1
<1
Section 3.4
2.8
100 kΩ to 2.8 V
Low
Low
All Low
<1
29
Section 3.2
2.8
100 kΩ to 2.8 V
Hi-Z
Low
All Low
<1
26 (1)
Figure 4
2.8
100 kΩ to 2.8 V
High
Low
I/O 1 and 2
pulled high by
10 kΩ to 2.8 V
<1
166
Section 3.1
(partially)
(1)
Care must be taken before deciding to set this pin to Hi-Z when an SS pullup is used, because of an intermediate external
voltage level that can cause extra current leakage by the input circuitry (see Figure 4).
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Conclusion
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Conclusion
This application report shows the key features that are important to minimize TRF79xx current
consumption in power-down mode.
Without careful attention to the design, power could be lost in power-down mode when designing with the
TRF79xx. With these simple considerations, this problem can be fixed.
5
Schematics
Figure 7 shows the reference to use to analyze the current setup. This schematic is nearly the same as
the TRF7970A EVM.
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Schematics
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+
Figure 7. Schematic
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