Download 2. delay elements

SURVEY OF VARIOUS TYPES
OF DLL ELEMENTS
ECE 518
RAHUL SRIKONDA
112147600
28TH April
CONTENTS
1.
2.
3
3.
4.
5
5.
INTRODUCTION
DELAY ELEMENTS
EXAMPLES
CONCLUSION
REFERENCES
1.INTRODUCTION
CLOCK SIGNAL LOCKED WITH THE INCOMING SINGAL
NECESSITY OF DLL
OUTPUT JITTER
Φclock/Φout is zero
TRANSFER FUNCTION:
RISE TIME FOR A STEP RESPONSE IS GIVEN BY :
VARIATION IN C1/Ipump AND Kv CAN INCREASE JITTER
2. DELAY ELEMENTS:
ANALOG DELAY LINE VS DIGITAL DELAY LINE
JITTER PERFORMANCE
COMPLEXITY
LAYOUT AREA AND POWER
SIMPLICITY
PORTABLITY
SUPPLY VOLTAGE
3. EXAMPLES:
1. DELAY LINES BASED ON INVERTERS:
CONVENTIONAL DELAY LINES BASED ON INVERTERS:
CHARACTERISTICS:
PROVIDE THE SHORTEST DELAY
DELAY LINE IS TAPPED AT EVERY OTHER INVERTER TO PROVIDE PHASE MATCHING
BETWEEN ADJACENT TAPS
USAGE OF A LONG DELAY LINE(LARGER AREA AND LARGER POWER CONSUMPTION)
POOR
OO POWER
O
S
SUPPLY REJECTION
C O RATIO
A O
ACCUMULATION OF JITTER
IMPROVEMENTS IN DESIGN OF CONVENTIONAL DELAY LINES:
CHARACTERISTICS:
USAGE OF COMPLEMENTARY INPUTS PROVIDES TAPPING AT EVERY NODE
REDUCTION IN TOTAL DELAY
REDUCED JITTER ACCUMULATION
LOW POWER CONSUMPTION AND LAYOUT AREA
CREATES PROBLEMS REGARDING TAPPING OF TRUE TAPS AND COMPLEMENTARY TAPS
ADDITONAL EOC DETECTOR IS NEEDED
REFERENCE:
THIS DELAY LINE HAS BEEN USED TO ACHIEVE INFINITE PHASE RANGE IN A 3.3v,0.4µm
µ
STANDARD CMOS PROCESS
“A Portable Digital DLL for High-Speed CMOS Interface Circuits,1998”
2. DUAL LOOP DLL:
DUAL LOOP DLL WITH LINEAR DELAY ELEMENT:
CHARACTERISTICS:
COMBINES THE ADVANTAGE OF FINE DELAY TUNING OF ANALOG DLL AND COARSE
TUNING OF DIGITAL DLL
ADVANTAGES:
FINE GRAIN DELAY VARIATION IS OBTAINED VIA ANALOG DELAY ELEMENT
COARSE GRAIN DELAY VARIATION IS OBTAINED VIA DIGITAL DELAY ELEMENT
DISADVANTAGES:
INHERENT CLOCK SKEW DUE TO DIGITAL DELAY LINE
NARROW FREQENCY RANGE DUE TO ANALOG DELAY LINE
ANALOG DELAY ELEMENT:
CURRENT STARVED DELAY ELEMENT
SIMPLE CIRCUIT
NON LINEAR RELATION BETWEEN CONTROLL VOLTAGE AND OUTPUT FREQUENCY
Q
CAN BE LINEARIZED BY USING A CURRENT MIRROR CIRCUIT IN SERIES WITH RESISTOR
ADDITONAL CIRCUITORY REQUIRED
DIGITAL DELAY ELEMENT:
M9-M14 MAIN ELEMENT,M6-M9 CURRENT MIRROR, M1-M4 CONTROLL
ADVANTAGE:16 DELAY STEPS
DISADVANTAGE:COMPLEX CIRCUIT
REFERENCE:
USED IN DUAL LOOP DLL BY 1.8V POWER SUPPLY BASED ON 0.18µm PROCESS
“A
A Novel Low-Power
Low Power and High
High-Performance
Performance Dual-Loop
Dual Loop DLL with Linear Delay Element
Element”,2008
2008
3. DELAY CELL USING DIFFERENTIAL AMPLIFIER:
CHARACTERISTICS:
M3 AND M4 ARE MADE WEAK TO SPEED UP SIGNAL TRANSITION
M5 AND M6 IMPROVE THE DRIVING CAPABILITY
M7 AND M8 ARE USED TO ADJUST THE DELAY
ADVANTAGE: SIMPLE CIRCUITRY
DISADVANTAGE: WEAK PMOS M3 AND M4 TEND TO SLOW DOWN THE SLEW RATE
ADDITIONAL DUMMY CELLS HAVE TO BE INCLUDED AFTER EACH
ELEMENT FOR EQUAL LOADING
REFERENCE:
USED TO GENERATE 8 MULTIPHASE OUTPUTS AND HENCE 8 DELAY ELEMENTS ARE
REQUIRED TO GENERATE 0.5
5GHz WIDE
RANGE MULTIPHASE DLL WITH A CALIBRATED
0 5-5GHz
WIDE-RANGE
CHARGE PUMP IN A 0.13µm CMOS PROCESS WITH A SUPPLY VOLTAGE OF 1.2V
“A 0.5-5GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump”,2007
4 PSEDUDO-NMOS
4.
PSEDUDO NMOS VCDL:
CHARACTERISTICS:
PMOS USED AS A VARIABLE RESISTOR CONTROLLED BY Vctrl
ADVANTAGE:
REQUIRED DELAY CAN BE EASILY INTRODUCED VIA Vctrl
DISADVANTAGE:
AS RESISTANCE OF PMOS IS VARIABLE THE DUTY CYCLE WILL NOT BE 50% EXACT.
HENCE EVEN NUMBER OF ELEMENTS SHOULD BE USED THUS INCREASING THE DELAY
REFERENCE:
“Voltage Controlled Delay Line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to Zero-IF
multistandard LO”,2009
5. ANALOG DELAY LOCKED LOOP:
8 IDENTICAL DELAY CELLS ARE CONNECTED IN SERIES TO BUILD UP A 3 BIT DELAY
LINE AND THE DELAY CELL IS AS SHOWN:
CHARACTERISTICS:
INV_2
INV
2 AND MI FORM THE BASIC CURRENT STARVED INVERTER
INV_1 AND INV_4 ARE ADDED TO GENERATE A STEEPER RAISING AND FALLING EDGE AND
HENCE ACCURACY CAN BE IMPROVED
ADVANTAGE: SIMPLE CIRCUITRY
DISADVANTAGE: NON LINEARITY CAN BE A PROBLEM
REFERENCE:
Hybrid DPWM with Analog Delay Locked Loop Xuzhen Shen, Xiaobo Wu, and Jing Lu, Lin Qin, 2010
6. OTHER DELAY ELEMENTS:
SINGLE ENDED DELAY
FULLY DIFFERENTIAL DELAY
CHARACTERISTICS:
BETTER COMMON MODE NOISE REJECTION AND DUTY CYCLE DISTORTION FOR FULLY
DIFFERENTIAL DELAY
LEVEL TRANSLATION IS REQUIRED
DEPENDENCE ON SELF BIASING TECHNIQUES
Q
REFERENCES:
“DRAM circuit design”, Brent Keeth, R Jacob Baker, Brian Johnson, Feng Lin
4. CONCLUSION:
VARIOUS DELAY ELEMENTS HAVE BEEN STUDIED AND THE USAGE OF THE TYPE OF DELAY
ELEMENT DEPENDS ON THE APPLICATION IN WHICH IT IS PUT INTO USE
VARIOUS FACTORS TO BE CONSIDERED WHILE CHOOSING THE DELAY ELEMENT CONSISTS
OF POWER CONSUMPTIONM LAYOUT AREA, REDUCTION IN JITTER, COMPLEXITY AND SO ON
5. REFERENCES:
1. A 0.5–5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump Chi-Nan Chuang, Student Member, IEEE, and
Shen-Iuan Liu, Senior Member, IEEE,2007
2. A Novel Low‐Power and High‐Performance Dual‐Loop DLL with Linear Delay Element, M. Gharib, Department of Electrical Engineering of IUST, Iran University of Science & Technology,Tehran, Iran AND A. Abrishamifar, Department of Electrical Engineering of IUST, Iran University of Science & Technology, Tehran, Iran, 2008
3. Voltage Controlled Delay Line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to Zero-IF multistandard
LO Cédric Majek, Yann Deval, Hervé Lapuyade and Jean-Baptiste Bégueret IMS Laboratory, University of Bordeaux
Bordeaux, France,2009
4. A Portable Digital DLL for High‐Speed CMOS Interface Circuits Bruno W. Garlepp, Kevin S. Donnelly, Associate Member, IEEE, Jun Kim, Pak S. Chau,,Jared L. Zerbe, Charles Huang, Chanh V. Tran, Clemenz L. Portmann, Member, IEEE, Donald Stark, Yiu‐Fai Chan, Member, IEEE, Thomas H. Lee, Member, IEEE, and Mark A. Horowitz,1998
5. Hybrid DPWM with Analog Delay Locked Loop Xuzhen Shen, Xiaobo Wu, and Jing Lu, Lin Qin, 2010
6. “DRAM circuit design”, Brent Keeth, R Jacob Baker, Brian Johnson, Feng Lin
7 CMOS circuit design,
7.
design layout and simulation,
simulation R Jacob Baker