Download CUSTOMER_CODE SMUDE DIVISION_CODE SMUDE

CUSTOMER_CODE
SMUDE
DIVISION_CODE
SMUDE
EVENT_CODE
Oct2016
ASSESSMENT_CODE BCA3030_Oct2016
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
18006
QUESTION_TEXT
Explain IEEE 1284 modes.
IEEE 1284 has five modes.(2 marks each)
1. Compatibility mode
2. Nibble mode
SCHEME OF EVALUATION
3. Byte mode
4. ECP mode
5. EPP mode
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
18009
QUESTION_TEXT
What are the different types of packages styles?
1.Dual inline package
2.Single inline
3.Small-outline “j” lend
SCHEME OF EVALUATION
4.Thin, small-outline package
5.Chip scale package
(2 marks for each)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
74017
QUESTION_TEXT
What are the different essentials of the CPU? Explain.
SCHEME OF
EVALUATION
The basic requirements for any CPU are BUS s and processor modes
The Buses
Usually the BUS is the common means for sharing data and this data transfer is
done between all the devices connected to it. The BUSes are also called
processor signals. The several sets of these signals are divided three main
sets, mainly
The data Bus: This BUS is responsible for the to and fro movement of
information in the CPU. It acts as a measure of CPU performance. It is also
used to carry data in and out of the CPU at any given time. The data BUS is
used to carry the information from CPU to RAM, ROM and I/O units as well as
among Timing and control.
The address Bus: This BUS is used to define address in the CPU. It is also
called as memory BUS. The Address BUS does not carry the actual data but
carries the specific address of that particular data. The address BUS measures
the data in terms of address lines. For example, the CPU with address lines =
10 may have address 210 = 1024 bytes.
The Control Bus: The BUS is also called as timing and control BUS. It is used
to control aid coordinate the CPU operations. The various signals are read,
write, interrupt, and acknowledge; parity checking, cache operation and power
control and management.
Processor modes
In generic term, mode is a way that creates a system for itself for its processor
creation and operations. Processor mode is responsible for managing and
controlling the system memory and its use. Processor modes are classified into
three types as:
Real mode: This mode operates CPU in a limited environment. The real mode
has the advantage of accessing speed. It is compatible with Intel 8088 chip. All
processors can support real mode. Computers normally boot in real mode or
DOS mode.
Protected mode: This mode used in modem multitasking operating systems
was first implemented in 80826. Protected Mode has several advantages.

It offers faster access to memory

It supports multitasking facility that manages the operating

System in the execution of many programs at a time.

There is no limit for accessing the memory.

It allows the computer to use additional memory whenever

Needed along with the support of virtual memory.
Virtual real mode: This mode of operation is the enhancement of
protected mode. Protected mode is used to run graphical multitasking
Os like windows. If you want to run DOS program in the windows
system then you would have to use the virtual real mode. This is
because the necessity of running DOS program on real mode and not
in protected mode has given rise to the virtual real mode. This mode
will simulate the real mode to start in the protected mode and help in
running DOS programs in windows. The virtual machine will have
separate address space dedicated to it, which helps in invoking this
feature of operating virtual real mode machines.
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
119567
QUESTION_TEXT
Explain in detail various types of Memory.
1.
ROM:–is a integrated circuit chip that allow the user only to read
and not to edit or modify the data inside it. Due to the embedding of
programmes data is not erased or neither be changed. But the
disadvantage with ROM chip is once the data is stored by the
manufacture it cannot be erased.
Types of ROM:
a.
PROM–you can write the data only once into it.
b.
EPROM–you can erase the data and overwrite the data into
it. But you cannot keep or delete the part of old content and add new.
c.
EEPROM–you can edit/modify or delete a part of data and
use it for storing the data.
SCHEME OF
EVALUATION
2.
RAM:–
EDORAM–extends the validity time of the output.
BEDORAM–is the extended versions of EDORAM which was
developed to read large blocks of data bits than EDO RAM.
DRAM–is mostly used by the PCs for their system’s main memory. It
uses single capacitor and transistor to hold the data bit.
SRAM–is used to hold data that can stay for a longer time without the
need of refresh circuit. It holds data bit as long as current supply exists in
the circuit.
SDRAM–is very much different from other types since it is connected to
the system clock and able to read and write in burst mode at the rate of 1
clock cycle per data bit.
DDRSDRAM–its functions are similar to SDRAM but it supports more
bandwidth by transferring twice data bit per cycle.
EDRAM–is a DRAM in which small amount of SRAM is embedded
inside the large amount of DRAM so that the memory access can be
made faster by embedding two memory into one.
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
119568
QUESTION_TEXT
Explain configuration, layout and signals of PCI.
PCI configuration:
PCI is a vast improvement over ISA bus architecture with the increase in
its speed from 8.33MHz to 33MHz frequency. This increased the data
transfer from 5MB/sec to 132MB/sec. Another important characteristic
was that it gave automatic configuration property to the switches and
peripherals. The following are the features supported by PCI bus which
are used today:
–Linear bursts:whenever memory sends data to the peripheral devices it
will be in linear address order. Linear burst is a method of continually
filling the data line in the bus by transferring the data.
–Low access latency: access latency is the time taken by the CPU to
permit the request access by the peripheral for its control. Reducing this
time increases the performance of the PCI.
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EVALUATION
–Bus mastering: is a feature of PCI which helps in any intelligent
peripheral to have a control of the bus which is used in boosting the
throughput of the bus which is used in boosting the throughput of the
architecture.
–Concurrency: when a processor chip works with Bus masters
simultaneously rather than waiting for them to complete, the process is
called concurrency.
–Dual voltage architecture: dual voltage features expects two different
voltages to be supported.
PCI bus layout:A +3.3 volts connector is added with a key at the 12th
position of the bus just to avoid any insertion of the +5 volts board to
+3.3 volts bus. A +5volts connector is added with a key at the 50th
position to avoid the wrong insertion of +3.3volts board into the +5volts
slot. PCI bus has its own internal interrupts which handle the requests on
the bus. PCI uses a technique which holds the signal dynamically and
whenever there is a requirement it can be reassigned. This technique is
called Interrupt ReQuest. IRQ can be shared by two or more PCI
devices. These IRQs can be accessed during CMOS setup routine.
PCI signals:
Clock Signal
Reset signal
Command/–Byte enable signal
Parity/PAR64 signal
–Request)–REQ) signal/line
Grant(–GNT) signal/line
Frame signal
Target Ready(–TRDY) signal
Initiator Ready(_IRDY) signal
Stop(–STOP) signal
Initialization Device Select(DEVSEL) signal
Lock(–LOCK) signal
Primary and secondary error reporting(PERR and SERR)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
119572
QUESTION_TEXT
Write a note on chronic problems which will help you to identify the
power supply which might arise midway in the course of working
The chronic problems listed below are
SCHEME OF
EVALUATION
a.
The computer freezes midway of the system working explain
b.
Random memory errors
c.
Hard drive data is lost or corrupted
d.
Trouble in communicating with modems or peripherals
e.
Hardware failures
(Scheme: 2*5 = 10 marks)