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0406EF3-Tanner.doc Keywords: analog, analog mixed signal, EDA tools Editorial Feature Tabs: Analog ---- AMS Design Flow and Tool Costs @head: EDA Tools Shouldn’t Cost More Than the Design Engineer @deck: As the analog content in chips increases, EDA-tool costs must be balanced with engineering-intensive design-time requirements. @text: EDA tools from the big three vendors are expensive. In fact, they’re comparable to the cost of an experienced engineer in the U.S., Europe, or Japan. As market forces move some design activities to lower-wage countries, the cost of those tools becomes unacceptable. Fortunately, some EDA companies are filling this gap with affordable tools that have ever-increasing functionality. The pressure to reduce design cost exists everywhere. Yet it is more pronounced in the chips that include analog circuits. In recent years, the demand for mixed-signal (analog and digital) IC products has accelerated. According to a recent Fabless Semiconductor Association survey, about 40% of the wafers ordered by its members were for mixedsignal design. This increase in demand is growing rapidly, thanks to high-growth markets like wireless networks and digital-audio devices. According to the International Data Corporation (IDC), for example, the cumulative semiconductor revenue from wireless networks from 2003 to 2008 will hit more than $180 billion. The market for audio ICs is set to exceed $6 billion in three years. Despite such strong growth, increasing pressure is being placed on semiconductor companies to keep design costs down in order to remain competitive. Reducing Design Costs Mask fabrication, design-engineering labor, and EDA tools are the three major contributors to design cost. Mask-fabrication cost remains high for now. Mask cost is expected to decrease, however, as newcomers in Malaysia and China become established in the mask-fabrication market. Due to their locations, these companies have a lower cost of operations and labor. They’re therefore positioned to contribute downward pressure on this important design cost. Although mask costs are an issue for all types of design, the differences between alldigital and mixed-signal design costs result in different market forces. Digital design engineers have benefited significantly from the automation offered by EDA tools. Topdown, synthesis-driven techniques have made the design of a multi-million-transistor digital chip highly achievable with fewer design engineers. Even though the EDA tools from the large EDA vendors are expensive, such tools are crucial to the digital design flow. With the level of abstraction made possible through hardware description languages (HDLs), the design of highly integrated ICs has become possible without the need for numerous digital design engineers. For some time, the greater design productivity of the expensive engineers operating costly EDA tools may be able to compete with the lower-wage teams--and their inexpensive tools--operating in developing countries. The dynamic for mixed-signal design and smaller digital chips is somewhat different. This statement is especially true for the majority of chip designs, which are manufactured only in medium to low volume. Here, companies must often contain their labor costs and expenditures on EDA tools in order to survive. Under competitive pressure, larger companies have off-shored some of their design work by opening wholly owned design centers in countries with lower wages. More recently, even lower-wage countries like India and China have sufficient numbers of competent engineers to attract multinational investments. Although smaller companies cannot afford to set up permanent design centers, they can reap some of the same benefits by outsourcing. They contract for temporary design services from companies that have workers in the lower-wage countries. The increasing pressure on EDA costs comes with the changes in mask and engineeringlabor costs. In many cases, companies that are designing high-volume digital chips have been willing to pay on the order of $100,000 per year for software that will be used by an engineer who is paid about that amount annually. To reduce the cost of the engineer to $20,000 per year by off-shoring or outsourcing and then continue to pay $100,000 per year for design software is often considered unpalatable. Some design companies attempted to reuse their floating licenses, which they already owned for their high-wage engineers, for an off-shore design center located in an opposite time zone. For the most part, the big EDA companies have modified their licensing policies to prevent such reuse. For design companies, one benefit is that a variety of EDA tools are available from some other EDA companies. Many of these tools are comparable in price to the lower-wage engineers. In addition, they’re easier to install, learn, and maintain. Plus, tools from more targeted EDA vendors often run on affordable and ubiquitous PC platforms that can be obtained and supported anywhere in the world. These more affordable EDA design tools are especially compelling in the case of analog or mixed analog-digital design. Why The Difference? Analog design is unlike digital design. Figure 1 summarizes the analog and digital design flows. Synthesis and place-and-route steps are largely automated by EDA tools for the digital flow. It’s very rare that a reusable analog algorithm can be used for different circuit types through automation. In analog design, the skill lies in choosing the right circuit topology. This choice heavily depends on the application. Although the number of transistors in the analog design is very small, the design can still be very challenging. After all, it requires a detailed understanding of the relationship between the transistors and the passive devices on the chip. Unlike digital tools, analog EDA tools can only support what the design engineers do. Because a high degree of automation isn’t offered for analog design, effective analog design tools shouldn’t be expensive. Analog tools don’t automate the circuit design directly. Yet there have been some attempts to speed up this custom design cycle. Circuit simulation is a key aspect of analog design. Some EDA vendors advocate fullchip simulation. Although simulating the entire chip is useful as a final sanity check, the majority of the analog engineer’s time is spent simulating key blocks in the design using a Spice circuit simulator--many of which aren’t expensive. For example, the T-Spice Pro package from Tanner EDA includes a Spice simulator, schematic editor, and postprocessing waveform viewer. Other Spice products are available for under $10,000 from many other companies. General-Purpose Analog Synthesis – Not A couple of years ago, there was a lot of buzz in the industry about analog synthesis. Now, many of the startup EDA companies from that time are gone. Most people have recognized that a general-purpose analog-synthesis tool remains a dream. A few of the surviving companies have been successful at developing specific, standardized, analog IP blocks that can be quickly generated within a fairly narrow range of performance parameters and process technologies. Whether it is proper to call the production of these specific customizable blocks “analog synthesis” is debatable. The success of some companies in this space isn’t debatable, however. One such company’s phase-locked-loop (PLL) intellectual property has found its way into numerous computer and consumer product chips. To be successful in the analog IP market requires the customer list, technological expertise, and tools for the analog expert to quickly produce customized layout blocks. Affordable analog EDA tools from various vendors have contributed to the success of many analog-IP specialists. Custom Automation Some tools offer built-in support for custom automation. Often, mixed-signal designers will design similar circuits for different ICs or different cores for the same IC. An example is the phase-locked loops that drive different digital blocks. Laying them out polygon by polygon for each new design is a tedious process. Fortunately, these costefficient tools provide scripting and programming interfaces. Such interfaces are as effective as those found in high-end mixed-signal tools. The providers of high-end mixed-signal tools have made big claims about the productivity improvements offered by their tools. A few of these claims actually are valid. When one looks closely at the mixed-signal design function, it becomes clear that features like schematic-driven layout (SDL) and “on-the-fly” design-rule checks (DRCs) can dramatically improve designer efficiency. The SDL allows the designer to generate the layout quickly from the schematic while continuously keeping track of the circuit elements’ connectivity. Typically, interactive DRCs contain only simplified design rules. But they indicate violations of these rules to the designer as they’re creating or editing the offending polygons. The designer corrects errors as they are made, which dramatically reduces rework. Fortunately, SDL and interactive DRC are now available from some EDA vendors at affordable prices. A good interactive DRC improves design efficiency by catching 90% to 95% of designrule violations early--when they are easy to fix. Yet the need remains for a more comprehensive DRC at the full-chip level. Such a DRC would take into account all design rules including connectivity-based and antenna rules. As process technology advances, the complexity of the full, final sign-off design rules is growing. A more capable, full-chip DRC is required to handle the full complexity of the sign-off rules. Cost-Effective Solutions The design-rule checkers from the largest EDA companies read design rules in the proprietary formats defined by the vendors. The dominance of a few of these tools has resulted in de-facto standards in rule-file formats. These standard-setting companies charge a premium price for their products. Some EDA companies have taken advantage of the standardization of DRCs and built their own tools to natively support these standards. For example, Tanner EDA introduced HiPer Verify. It can run Mentor’s Calibre and Cadence Dracula DRC files unmodified. Analog design cannot be performed as automatically by the design tools as digital design has been. The totally integrated analog design flow that’s proposed by the largest EDA vendors may look good in theory. But it’s difficult to see how the expense can be justified when more cost-effective tools from other EDA vendors can achieve the same results at a tenth of the price. Many of these EDA vendors offer compatibility with industry standards, such as GDSII and Calibre/Dracula. Support Responsiveness When selecting an EDA tool vendor, a design company should consider support as well as price and functionality. Some EDA companies are known for supporting large accounts. Yet a number of the alternative EDA companies are often much more responsive. Many of these companies have honed their products over the years to need less support. In addition, the major EDA companies have developed tool suites over the years from acquisitions. After an acquisition, the engineering staff that developed and supported these tools typically retires. The company is left with less knowledgeable staff to support the tools. As a result, it may be hard for a customer to find someone who knows how a tool is supposed to work. In contrast, some other EDA companies develop their tools in house and engineer them to work with other tools and to require little support. Some EDA companies have very responsive support departments. But the best support is when support isn’t needed. Quality tools that have standardized user interfaces running on Windows PCs, good online documentation, and minimal bugs mean less calls to support. The tool will do what is expected. The EDA vendors that deliver this level of tool save themselves support costs while saving their customers’ engineering time. Changing Venture-Capitalist Views In the exuberance of the late 1990s, venture capital flowed freely. In those “gold-rush” times, it was deemed more important to get to market as quickly as possible. Getting value for expenditures often was second priority. During these times, many chip-design companies were funded by venture capital. Up to half of the initial investment went toward purchasing high-end EDA tools. As many of these companies failed, however, CEOs and venture capitalists alike have come to regret these expensive EDA purchases. Many realize that if they’d gone with cost-effective tools, they would’ve had sufficient funds to ride through the market downturns or other perils of fledging companies. Instead, these companies ceased to exist. At the same time, the startup companies that chose less expensive tools have turned into successful, large companies. As word of these experiences spread throughout the VC community, attitudes shifted. Now, many venture capitalists are much more valueconscious. They’re insisting that the companies that they fund be much more discerning about EDA expenditures. The situations in which the high-priced EDA tools are justified are just not that many. Figure 2 shows the applicability of high-priced tools: large die, digital, and expensive engineer. In years past, the decision to buy EDA tools was easier. If a company could afford to buy the most expensive tools, it did. Now, it’s more complex. The growing analog content in chips demands a more engineer-intensive design methodology. This requirement drives off-shoring, outsourcing, and the purchase of affordable EDA tools. Some of the small and medium-sized EDA vendors have been around for a long time. They keep the loyalty of their customers with affordable prices along with ease of use, flexible licensing, low maintenance cost, superior customer support, and a growing range of functionality. Unless a company is working on a state-of-the-art, high-volume, digital-only chip with high-priced engineers, EDA tools from a small or medium-sized EDA company may now be a good fit. John Tanner is the President and CEO of Tanner EDA. He co-founded Stac Electronics, which was best known for the Stacker disk-doubler program for the PC. Dr. Tanner has been a visiting Professor of Computer Science at Caltech. He holds a BA from Wartburg College in Waverly, Iowa, and an MSEE and PhD in Computer Science from Caltech. ++++++++++ Captions: Figure 1: This diagram summarizes the typical analog/mixed-signal (AMS) and digital design flow. Figure 2: Here, a three-dimensional decision matrix highlights the applicability of highpriced tools: large die, digital, and expensive engineer.