Download ` = A` + B`

Lecture 6
BOOLEAN ALGEBRA
and GATES
Building a 32 bit processor
PH 3: B.1-B.5
1
Lets Build a Processor
•
•
Almost ready to move into chapter 5 and start building a processor
First, let’s review Boolean Logic and build the ALU we’ll need
(Material from Appendix B)
operation
a
32
ALU
result
32
b
32
2
Boolean Algebra
• In Boolean Algebra, all variables are 0 and 1 and
there are 3 operators
• OR is written as + as in A + B, called logical sum.
(Sometimes denoted with A U B)
• AND is written as ∙ , as in A ∙ B, (also denoted AB)
called the logical product. (Sometimes denoted by
A ∩ B)
• NOT is written as A’. The result of NOT A is 0 if A is
1 and 1 if A is 0.
3
Laws of Boolean Algebra
•
•
•
•
•
Identity law: A + 0 = A and A ∙ 1 = A
Zero and One laws: A + 1 = 1 and A ∙ 0 = 0
Inverse laws: A + A’ = 1 and A ∙ A’ = 0
Commutative laws: A + B = B + A and A ∙ B = B ∙ A
Associative laws: A + (B + C) = (A + B) + C
A ∙ (B ∙ C) = (A ∙ B) ∙ C
• Distributive laws: A ∙ (B + C) = A ∙ B + A ∙ C
A + (B ∙ C) = (A + B) ∙ (A + C)
• DeMorgan’s laws: (A + B)’ = A’ ∙ B’ and
(A ∙ B)’ = A’ + B’
4
Boolean Algebra & Gates
• Problem: Consider a logic function with three inputs: A, B,
and C.
Output D is true if at least one input is true
Output E is true if exactly two inputs are true
Output F is true only if all three inputs are true
• Show the truth table for these three functions.
• Show the Boolean equations for these three functions.
• Show an implementation consisting of inverters, AND, and
OR gates.
5
Truth Tables
6
Sum of Products
• The sum of products form is constructed from a
truth table by choosing only those inputs that
result in an output of 1 and forming the product of
the inputs that are 1 and the complements of the
inputs that are false. The sum of all such products
gives an implementation of the function.
• For D this would mean D = A’B’C + A’BC’ + A’BC +
… (7 terms in all). It works but we can do it easier
by noting that D’ = A’B’C’.
• By one of DeMorgan’s Laws we have D = A + B + C
7
Boolean Equations
• D=A+B+C
• F = ABC
• E = ABC’ + AB’C + A’BC or
E = (AB + BC + AC) (ABC)’
• It is easy to show the two equations for E are
equivalent by using truth tables or by using
DeMorgan’s law to change (ABC)’ into A’ + B’ + C’,
then using the distributive law a few times.
8
Another example of Sum of Products
The sum of products gives D = A’B’C + A’BC’ + AB’C’ + ABC
9
Simplification of Boolean Expressions
• The Karnaugh map is a graphic method that can handle
Boolean expressions up to 6 variables
• It is a simplification method that uses the following relations:
x + x’ = 1 and y ∙ 1 = 1 ∙ y = y
• Basic idea is the sum of two expressions can be combined
and simplified if they have a distance of 1 where distance is
defined as follows:
• The distance between two product terms is equal to the
number of literals that occur differently, i.e., one is
complemented while the other is not. For example A’B’C and
A’B’C’ have a distance of 1 whereas A’BC and A’B’C’ have a
distance of 2.
• Now the sum of the distance 1 pair can be simplified as
follows:
A’B’C + A’B’C’ = A’B’(C + C’) = A’B’
10
A one-variable Boolean function. (a) Truth table.
(b) Karnaugh map.
11
A two-variable Boolean function. (a) Truth table.
(b) Karnaugh map
12
An illustrative three-variable Boolean function.
(a) Truth table. (b) Karnaugh map.
13
A four-variable Boolean function. (a) Truth table.
(b) Karnaugh map.
14
Karnaugh map for a four-variable map functions.
15
Typical map subcubes for the elimination of one
variable in a product term.
16
Typical map subcubes for the elimination of two
variables in a product term.
17
Typical map subcubes for the elimination of three
variables in a product term.
18
Addition
19
Adder
20
You can see that the carry out is correct with a
Karnaugh map if it is not obvious already
bc
0
00
0
01
0
11
1
10
0
1
0
1
1
1
a
You have a column of two 1’s that gives bc, a left most
row of two 1’s that gives ac and a right most row of
two 1’s that gives ab
21
Exclusive-Or
• Truth table
x
y
0
0
0
1
1
0
1
1
•
x xor y
0
1
1
0
(x xor y)’
1
0
0
1
Equation
x xor y = x’y + xy’
Where xy means x and y and x + y means x or y
22
Exclusive-or continued
The following equation can be represented as (a xor b) xor carryin
Proof: (a xor b) xor ci = (ab’ + a’b) ci’ + (ab’ + a’b)’ ci
= (ab’ + a’b) ci’ + (a’b’ + ab) ci .
Note it is easily shown that (a xor b)’ = a’b’ + ab
23
Realization of a full binary adder
24
Parallel (Ripple) binary adder
25
A 32-bit Ripple Carry Adder/Subtractor
Remember 2’s
complement is just

complement all the bits
control
(0=add,1=sub)
B0

B0 if control = 0,
!B0 if control = 1
add a 1 in the least
significant bit
A
0111
B - 0110
c0=carry_in
A0
1-bit
FA
c1
S0
A1
1-bit
FA
c2
S1
A2
1-bit
FA
c3
S2
B0
B1
B2
...

add/sub

0111
 +
c31
A31
B31
1-bit
FA
S31
c32=carry_out
26
An ALU (arithmetic logic unit)
•
Let's build an ALU to support the and and or instructions
– we'll just build a 1 bit ALU, and use 32 of them
operation
a
op a
b
res
result
b
•
•
For AND just use an AND gate and
for OR just use an OR gate
27
Review: The Multiplexor
•
Selects one of the inputs to be the output, based on a control input
S
•
•
A
0
B
1
C
note: we call this a 2-input mux
even though it has 3 inputs!
S causes A or B to be selected.
Lets build our ALU using a MUX:
28
Different Implementations
•
Not easy to decide the “best” way to build something
•
– Don't want too many inputs to a single gate
– Don’t want to have to go through too many gates
– for our purposes, ease of comprehension is important
Let's look at a 1-bit ALU for addition:
CarryIn
a
Sum
b
cout = a b + a cin + b cin
sum = a xor b xor cin
CarryOut
•
How could we build a 1-bit ALU for add, and, and or?
•
How could we build a 32-bit ALU?
29
Building a 32 bit ALU
CarryIn
Operation
Operation
CarryIn
a0
a
b0
0
1
ALU0
Result0
CarryOut
Result
a1
b1
2
CarryIn
ALU1
Result1
CarryOut
b
CarryOut
CarryIn
a2
b2
CarryIn
ALU2
Result2
CarryOut
a31
b31
CarryIn
ALU31
Result31
30
What about subtraction (a – b) ?
•
•
Two's complement approach: just negate b and add.
How do we negate?
•
A very clever solution:
Binvert
Operation
CarryIn
a
0
1
b
0
Result
2
1
CarryOut
31
Subtractor circuit from modified adder
32
Binary adder/subtractor
33
Adding a NOR function
•
•
Can also choose to invert a. How do we get “a NOR b” ?
Invert both a and b and input to an and gate since (a + b)’ = a’b’
Ainvert
Operation
Binvert
a
CarryIn
0
0
1
1
b
0
+
Result
2
1
CarryOut
34
Tailoring the ALU to the MIPS
•
Need to support the set-on-less-than instruction (slt)
– remember: slt is an arithmetic instruction
– produces a 1 if rs < rt and 0 otherwise
– use subtraction: (a - b) < 0 implies a < b
•
Need to support test for equality (beq $t5, $t6, $t7)
– use subtraction: (a - b) = 0 implies a = b
35
Supporting slt Can we figure out the idea?
Operation
Ainvert
Binvert
a
CarryIn
0
0
Handling the
most significant
bit
1
1
Result
b
0
+
2
1
Less
3
Set
Overflow
detection
Overflow
All other bits for slt
Operation
Ainvert
Binvert
a
CarryIn
0
0
1
1
Result
b
0
+
2
1
Less
3
CarryOut
37
Supporting slt
Operation
Binvert
Ainvert
CarryIn
a0
b0
CarryIn
ALU0
Less
CarryOut
Result0
a1
b1
0
CarryIn
ALU1
Less
CarryOut
Result1
a2
b2
0
CarryIn
ALU2
Less
CarryOut
Result2
..
.
a31
b31
0
..
. CarryIn
CarryIn
ALU31
Less
..
.
Result31
Set
Overflow
38
Equality Test
•
If a – b = 0 in the slt test the two numbers are equal. One can add a
test for this by setting an output flag, zero = 1 if the two values are
equal and to 0 otherwise.
•
Therefore zero can be defined by
Zero = (Result31 + Result30 + … + Result0)’
•
It can then be added as output as in the following diagram.
39
Equality
•
Notice control
lines:
0000 = and
0001 = or
0010 = add
0110 =
subtract
0111 = slt
1100 = NOR
• The right two bits
are the operation
•Note: zero is a 1
when the result
is zero!
Operation
Bnegate
Ainvert
a0
b0
CarryIn
ALU0
Less
CarryOut
a1
b1
0
CarryIn
ALU1
Less
CarryOut
a2
b2
0
CarryIn
ALU2
Less
CarryOut
..
.
a31
b31
0
Result0
Result1
..
.
Result2
..
. CarryIn
CarryIn
ALU31
Less
Zero
..
.
..
.
Result31
Set
Overflow
40
Conclusion
•
We can build an ALU to support the MIPS instruction set
– key idea: use multiplexor to select the output we want
– we can efficiently perform subtraction using two’s complement
– we can replicate a 1-bit ALU to produce a 32-bit ALU
•
Important points about hardware
– all of the gates are always working
– the speed of a gate is affected by the number of inputs to the
gate
– the speed of a circuit is affected by the number of gates in series
(on the “critical path” or the “deepest level of logic”)
•
Our primary focus: comprehension, however,
– Clever changes to organization can improve performance
(similar to using better algorithms in software)
– We saw this in multiplication, let’s look at addition now
41
Reading material for next time
• PH 3: B.6-B.11
42