Download denigration of harmonics in a 7-level cascaded multilevel

International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)
ISSN: 0976-1353 Volume 12 Issue 4 –FEBRUARY 2015.
DENIGRATION OF HARMONICS IN A 7LEVEL CASCADED MULTILEVEL
INVERTER USING A SPECIFIC PWM
TECHNIQUE
K.Gaayathry 1, Dr.S.M.GiriRajkumar2
1
Research Scholar, Department of Electrical and Electronics Engineering, TRP Engineering College
(SRM Group), Trichy, India.
2
Supervisor,Department of Instrumentation and Control Engineering,Saranathan College of Engineering,
Trichy,India.
Abstract- The Multilevel inverters (MLI) have emerged as a
very important alternative in the area of high-power,
medium-voltage
applications.
Consequently
several
Multilevel Inverter topologies are developed. The MLI is
mainly used to attain higher power by using series of power
semiconductor switches with lower voltage dc sources to
exhibit the power conversion by synthesizing a staircase
voltage waveform. The dc voltage sources preferred here is
batteries. The objective of this paper is to optimize the
Efficiency of Cascaded Multilevel Inverter by minimizing the
harmonics. This paper emphasis on unipolar Inverted Sine
Carrier Pulse Width Modulation (ISCPWM) switching
strategy for voltage source inverter through carrier
modification which develops the fundamental output with
minimization of Total Harmonic Distortion (THD) and
switching losses and helps to obtain better harmonic
spectrum. This paper presents a bibliographical review of
cascaded multilevel inverters, control techniques, Simulation
results, Hardware Implementation and finally, future scope
and applications are addressed. Simulation is done using
MATLAB and the computational results are demonstrated
graphically for better understanding and to prove the
effectiveness of the method.
An experimental 7-level
Cascaded MLI is employed to validate the computational
results.
conventional 2 – level converter. Utilization of MLI
has become popular in Industries and Research have
increased the utilization of MLI for high voltage
applications like static VAR compensators [4-5], active
power filters [6], and Adjustable speed drives (ASDs)
for medium-voltage Induction motors [7-8] etc.,
because of its ability to synthesize stepped waveforms
with better harmonic spectrum and attain higher
voltages with a limited maximum device rating and
characteristics like voltage operation above classic
semiconductor limits, lower common mode voltages,
less voltage stress. The utilization of Multilevel
Inverters is widespread in medium voltage applications
because of their inherent voltage sharing among the
devices. This paper is organized as follows. Sec I
shows the inverter classification, working and basic
circuit topology.
II. CASCADED MULTILEVEL INVERTER(CMLI)
The topologies of MLI are classified into 3
types such as Diode clamped, Cascaded Multilevel
Inverters and Flying capacitors. The selection of an
particular multilevel topology to supply a specific load
in this paper is based on some features which is given
below in the table.
Index Terms- Multilevel Inverter(MLI), Inverted Sine
Carrier Pulse Width Modulation (ISCPWM), Total Harmonic
Distortion (THD).
I. INTRODUCTION
Inverter
Configuration
The multilevel inverter concept has been
introduced since 1970’s. The term multilevel starts
from 3 level converter . Various MLI topologies are
projected since after a decade. There are different MLI
structures such as Cascaded Multilevel Inverter with
separate dc sources [1], Diode clamped [2] and Flying
capacitors [3]. But, this paper focuses on Symmetrical
Cascaded Multilevel Inverter due to its various
benefits. Many modulation techniques and control
paradigms have been used for MLI such as Sinusoidal
Pulse Width modulation (SPWM), Selective Harmonic
Elimination (SHE –PWM), Space Vector Modulation
(SVM) etc. MLI has various benefits over a
Main Switching
Devices
Main Diodes
Clamping
Diodes
DC Bus
Capacitors
Balancing
Capacitors
Diode Clamped
Flying
Capacitors
Cascaded
MLI
2(m-1)
2(m-1)
2(m-1)
2(m-1)
(m-1)
(m-2)
(m-1)
2(m-1)
0
2(m-1)
0
(m-1)
(m-1)/2
(m-1)
(m-2)/2
0
0
This configuration is free from the problem of
voltage balancing, which is a common issue in DiodeClamped and Flying Capacitor type. The Cascaded
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International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)
ISSN: 0976-1353 Volume 12 Issue 4 –FEBRUARY 2015.
Multilevel Inverters (CMLI) is preferred due to its
advantages like high degree of modularity, possibility
of connecting directly to medium voltage, high power
quality, power flow control in regenerative version,
smaller voltage stress compared to series connected 2level,requires least number of components, because
there is no need for clamping diodes and flying
capacitors. CMLI is used to synthesize a medium
voltage output based on power cells which are
connected in series and it uses standard low voltage
component configurations. This feature helps to
achieve high quality output voltages and input currents
and also outstanding availability due to their
redundancy. Because of this characteristic, the CMLI is
recognized as an vital alternative in medium-voltage
inverter market.
III. EXISTING MODULATION TECHNIQUE
Various Modulation Techniques have been
proposed for CMLI. Modulation techniques for
cascaded multilevel inverters are usually an extension
of the two-level modulations . A higher count of power
electronic devices and switching redundancies will
result in a higher level of difficulty compared with a 2level inverter counterpart. Anyhow, this difficulty
could be utilized to add additional capabilities to the
modulation technique namely, decreasing the switching
frequency, reducing the common mode voltage or
balancing the dc voltages. Based upon the switching
frequency, CMLI can be classified as follows, 1)
fundamental switching frequency and 2) high
switching frequency. The Modulation Techniques
namely Multilevel Selective Harmonic Elimination
(SHE) comes under fundamental switching frequency
and multilevel Space Vector Pulse Width Modulation
(SVPWM) comes under high switching frequency.
Fig 1 : Multilevel Level shifted carrier based technique
Phase shifted PWM is the widely used
modulation Technique for CMLI because it produces
an even power distribution among cells and it is very
simple to implement independently of the number of
inverters [12-13]. The main advantage of this technique
is that it shifts the phase of each carrier in a proper
angle to decrease the output voltage harmonic content
as shown in Fig.2. It can be able to withstand in the
over modulation region.
IV. PROPOSED MODULATION TECHNIQUE
Here Multilevel carrier based PWM is going
to be used, because when compared to SVPWM
methods the carrier based PWM methods can be
advantageously utilized in 1) controlling common
mode voltage 2) controlling complicated inoerter
topologies such as 4-leg and 5-leg multilevel inverters
and 3) compensating unbalanced dc soures [9 – 10].
This modulation technique uses many triangular carrier
signals which can be modified in phase / vertical
position in order to decrease the output voltage
harmonic content. There are 2 common carrier
modifications which can be applied to the CMLI
namely, Level shifted PWM and Phase shifted PWM.
Generally Level shifted PWM is commonly used in
Diode-Clamped inverters and rarely preferred for
cascaded inverters due to its major drawback that it
produces an uneven distribution of power among cells
as in Fig.1, and higher input current harmonic content.
In [11], it is shown that this technique is used for a 5
level inverter.
Fig 2 : Multilevel Phase shifted carrier based technique
V. PURPOSE OF HARMONICS MINIMIZATION
A sinusoidal component of a periodic wave /
quantity having a frequency that is an integral multiple
of the fundamental frequency is defined as harmonics.
Total harmonic distortion (THD) is the widely used
power quality index to describe the quality of power
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International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)
ISSN: 0976-1353 Volume 12 Issue 4 –FEBRUARY 2015.
electronic converter. The THD of the output voltage
which is defined as the square root of sum of squares of
harmonic voltages divided by fundamental voltage (V1)
can be calculated as,
THD = √(V22+V32+V42+…..+Vn2)/V1
The harmonic content in the output of the
inverter can be decreased by using PWM. The PWM
techniques and strategies are the subject of intensive
research since 1970’s were to synthesize a sinusoidal
ac output voltage. Sinusoidal PWM (SPWM) is
effective in minimizing lower order harmonics while
varying the output voltage. [14-18]. The fundamental
amplitude in the SPWM output waveform is smaller
than for the rectangular waveform. The SPWM
technique, however, explores poor performance with
regard to maximum attainable voltage and power. The
proposed ISCPWM method, which utilizes the
conventional sinusoidal reference signal and an
inverter sine carrier, possesses a better spectral quality
and a higher fundamental component compared to the
conventional SPWM without any pulse dropping and it
does not produce Harmonics of carrier frequencies or
its multiples.
(1)
The output voltage of the MLI is a
symmetrical stepped voltage waveform. The output
voltage consists of fundamental and the associated
harmonics. These harmonics generate additional
heating, when the output voltage of the inverter is fed
to the load. Henceforth, in order to reduce that,
harmonics minimization is necessary.
VI. INVERTED SINE CARRIER PULSE WIDTH
MODULATION (ISCPWM) METHOD
The ISCPWM method gives higher
fundamental throughout the inverter working range. Its
performance is more appreciable in lower modulation
index ranges. For instance, at Ma = 0.1, ISCPWM
gives fundamental component value three times of
SPWM at the same time the THD value 40% less.
Hence, the ISCPWM scheme is more favourable than
the SPWM technique for use in the inverter. The
application of unipolar PWM to inverted sine carrier
results in the reduction of carrier frequencies or its
multiples and significant reduction in switching losses.
So, the advantage of inverted sine and unipolar PWM
are combined to improve the performance of the
hybrid multilevel inverter. From the Fig.3, it is clear
that the pulses are generated whenever the amplitude
of the reference sine wave is greater than that of the
inverted sine carrier wave.
The ISCPWM strategy enhances the
fundamental output voltage expecially at lower
modulation index ranges while keeping the THD
lower without including changes in switching losses of
the device. There is a reduction in the total harmonic
distortion (THD) and switching losses.The control
strategy uses the same reference (synchronized
sinusoidal signal) as the conventional SPWM while
the carrier triangle is a modified one. The control
scheme uses an inverted (high frequency) sine carrier
that helps to increase the output voltage. Enhanced
fundamental component demands greater pulse area.
The difference in pulse widths resulting from triangle
wave and inverted sine wave with the low (output)
frequency reference sine wave in different sections can
be easily understood. In the gating pulse generation of
the proposed ISCPWM scheme shown in Fig. 3, the
triangular carrier waveform of SPWM is replaced by
an inverted sine waveform. For the ISCPWM pulse
pattern the switching angles may be computed as the
same way as SPWM scheme.
VII. SIMULATION RESULTS
The Simulation Diagram and results for the
Symmetrical Cascaded Multilevel Inverter with
Inverted Sine Carrier pulse Width Modulation
(ISCPWM) are shown below :
Fig 3 : Inverted Sine Carrier Pulse Width Modulation (ISCPWM)
Pulse Pattern
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International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)
ISSN: 0976-1353 Volume 12 Issue 4 –FEBRUARY 2015.
Fig 6 : Sinusoidal Reference Signal And Inverted Sinusoidal Carrier
Signal
Fig 4 : Block Diagram of Cascaded multilevel Inverter
Fig 5 : Inverted Sinusoidal Carrier Signal Generation
Fig 7 : Output Waveform of Unipolar Inverted Sinusoidal Carrier
Signal Generation
(a)
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International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)
ISSN: 0976-1353 Volume 12 Issue 4 –FEBRUARY 2015.
Fig 9 : Prototype of 7-level Cascaded Multilevel Inverter with
ISCPWM technique.
(b)
Fig 8 : Inverted Sine Carrier pulse Width Modulation (ISCPWM)
Method
a) Output Phase Voltage Waveform and
b) Harmonic Spectrum
Fig 10 : Experimental Result of 7-level Cascaded Multilevel Inverter
with ISCPWM technique.
IX. FUTURE SCOPE AND APPLICATIONS
The modulation technique used in this paper
has a greater scope in applications involving electrical
vehicles,Medium voltage levels with high-power
applications, Utility Interface for Renewable Energy
Systems, Industrial medium-voltage motor drives,
Flexible AC transmission system (FACTS), Traction
Drive systems, Laminators, Pumps, Conveyors,
Compressors, Fans, Blowers and Mills.
8. EXPERIMENTAL RESULTS
To experimentally evaluate the Proposed
Cascaded Multilevel Inverter , a prototype 7-level
Inverter has been built using IRF840B MOSFETS
as the switching devices. The Experimental
waveform for the proposed MLI is shown in Fig. 9
and 10.
X.CONCLUSION
The paper presents the proposed technique
to prove that the fundamental voltage is improved
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International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)
ISSN: 0976-1353 Volume 12 Issue 4 –FEBRUARY 2015.
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throughout the working range and is higher than the
voltage obtained using conventional method which
uses triangular carrier waveforms for modulation. In
addition to this, switching losses and THD are also
lower compared to the conventional PWM technique.
This paper also employs symmetrical DC sources
thus decreasing the complexity and the cost of the
circuit. The main advantage of this approach is that it
adopts a consistent strategy for the entire range of
modulation index. The improvement in THD in the
lower range of modulation depth attracts drive
applications where low speed operation is required.
The minimized distortions even at low modulation
depth provide scope for the ISCPWM scheme not
only when higher fundamental demanded and also
obtaining low fundamental values.
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