Download MASTER'S THESIS Development of an Ultra-precise Digital Phasemeter for the LISA Gravitational

MASTER'S THESIS
Development of an Ultra-precise Digital
Phasemeter for the LISA Gravitational
Wave Detector
Carlos M. Burnett
Master of Science
Space Engineering
Luleå University of Technology
Department of Computer Science, Electrical and Space Engieering
Master’s Thesis
Development of an Ultra-precise Digital
Phasemeter for the LISA Gravitational
Wave Detector
Carlos M. Burnett
September 21, 2010
a
Master’s Thesis conducted under the framework of the Erasmus Mundus Programme from the Education,
Audiovisual and Culture Executive Agency (EACEA) of the European Commission.
Degree Program
Joint European Master in Space Science & Technology
Thesis Title
Development of an Ultra-precise Digital Phasemeter for the LISA
Gravitational Wave Detector
Author
Carlos Miranda Burnett1,2,3
Supervisors
Johnny Ejemalm1, Hakan Kayal2, Dennis Weise3
Luleå University of Technology1
Department of Space Science
Institutionen för Rymdvetenskap
Luleå Tekniska Universitet
Rymdcampus 1
981 92 Kiruna
Sweden
University of Würzburg2
Department of Aerospace Information Technology
Lehrstuhl für Informatik VIII
Julius-Maximilians-University Würzburg
Am Hubland
D-97074 Würzburg
Germany
EADS Astrium3
Astrium Satellites
Department of Science Missions & Systems
Laboratory for Enabling Technologies
Claude-Dornier-Str.
88090 Immenstaad
Germany
Abstract
The first direct detection of gravitational waves is greatly anticipated by scientists since
it would lead to a whole new observational spectrum, beyond electromagnetic radiation
and highly energetic particles. ESA and NASA are currently planning a space-based gravitational wave detector named LISA, or Laser Interferometer Space Antenna, but key
technologies are yet to be developed before such ambitious mission can be realized. In
this respect, the Laboratory for Enabling Technologies (LET) at EADS Astrium has been
engaged with the development of state-of-the-art enabling technologies for LISA, including
the development of an ultra-precise phasemeter. The LISA metrology concept requires the
detection of picometer distance
√ variations in the frequency range from 0.1 mHz to 0.1 Hz
and with sensitivity of 12 pm/ Hz. √
Therefore, the phasemeter is required to perform with
microradian precision (few µcycles/ Hz). The goal of this work was the development of
a FPGA-based digital phasemeter as a technology demonstrator for LISA. As a result, a
prototype for the LISA phasemeter was developed which can support up to eight parallel
channels. Therefore, it allows for the measurement of phase differences between a pair
of quadrant photodiodes, which can be useful for differential wavefront sensing. In addition, an analog compensation scheme for phase noise corrections was investigated. This
investigation resulted in the design and fabrication of a pilot tone board for ADC jitter calibration. Finally, it was also demonstrated that, under certain conditions, the phasemeter
can operate within the stipulated LISA requirements.
Acknowledgments
First of all, I would like to show my gratitude to the European Commission for granting
the scholarship which made this Master’s studies possible. Hopefully more initiatives like
this will continue to allow students from all over the world, across any border, to pursue
their dreams and aspirations, while receiving a world-class education.
Secondly, I would like to thank the people behind the SpaceMaster consortium who has not
only founded such a magnificent program, but has also been supporting its continuation.
For that, I would like to give a special thanks to Sven Molin, Victoria Barabash, Klaus
Schilling, and all the many others involved.
Certainly, I also have to give a very special thanks to everyone at JMUW, LTU and IRF
who has been with us during this last couple of years. Especially I would like to thank
Anette Snällfot-Brändström, Maria Winnebäck, Heidi Schaber, Stefan Rova, and Victoria
Barabash (again). You all promptly assisted us when needed, and you often went beyond
your duties to do so. I am ever grateful for that.
Thanks also to my colleagues at EADS Astrium. Thanks to you I will always have good
memories from my time at Lake Constance (and Allgäu). I also have to thank my supervisor
Dennis Weise for providing me with the opportunity to work with the LISA mission, and for
supporting and motivating me whenever I wanted to learn more about this thrilling space
science mission. Also many thanks to Martin Gohlke, Hans-Reiner Schulte, Andreas Keller,
and all my colleagues at the Laboratory for Enabling Technologies for all the invaluable
discussions and support for my work.
I also want to acknowledge my academic supervisors Hakan Kayal and Johnny Ejemalm
for the cordial cooperation. It was great to have you both as professors during the lecturing
periods and as supervisors for my thesis work.
Last, but not least, I want to thank my friends and family in Brazil and throughout the
world. You have been my greatest source of inspiration and motivation all along.
Thank You!
Kiruna, Sweden
September 13, 2010
iii
Contents
List of Figures
vii
List of Tables
x
List of Abbreviations
xiii
List of Symbols
xv
1. Introduction
1.1. A Brief History of General Relativity . . . . . . . . . . . . . . . . . . . . .
1.2. Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2. Gravitational Waves
2.1. What Are Gravitational Waves? . . . . . . . . . . . . . . . . . . . . . . . .
2.2. Mathematical Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3. Detection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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3. The
3.1.
3.2.
3.3.
LISA Mission
Mission Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scientific and Technical Requirements . . . . . . . . . . . . . . . . . . . . .
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4. LISA Phasemeter Overview
4.1. General Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2. Prototype Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1. Status Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5. Development of a FPGA-based Digital
5.1. DPLL Basics . . . . . . . . . . . .
5.2. FPGA Architecture . . . . . . . . .
5.2.1. DPLL . . . . . . . . . . . .
5.2.2. Decimation Filter . . . . . .
5.2.3. Data Transfer . . . . . . . .
5.3. Hardware Implementation . . . . .
5.3.1. FPGA System Build . . . .
5.3.2. RS232 Interface Card . . . .
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Phasemeter
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v
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Contents
5.3.3. System Housing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6. Pilot Tone Calibration for ADC Jitter Corrections
6.1. Description . . . . . . . . . . . . . . . . . . . .
6.2. Pilot Tone Board . . . . . . . . . . . . . . . . .
6.2.1. Symmetric Design . . . . . . . . . . . . .
6.2.2. Asymmetric Design . . . . . . . . . . . .
6.2.3. Power Loss . . . . . . . . . . . . . . . .
6.2.4. Isolation . . . . . . . . . . . . . . . . . .
6.2.5. Wideband Amplifiers . . . . . . . . . . .
6.2.6. Voltage Regulation . . . . . . . . . . . .
6.2.7. Anti-aliasing Filter . . . . . . . . . . . .
6.2.8. PCB Implementation . . . . . . . . . . .
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7. Analysis and Results
7.1. Phasemeter Evaluation . . . .
7.1.1. Performance . . . . . .
7.1.2. Frequency Dependency
7.1.3. Amplitude Dependency
7.2. Pilot Tone Calibration . . . .
7.2.1. Pilot Tone Detection .
7.2.2. Phase Corrections . . .
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8. Conclusions
63
9. Further Work
65
Bibliography
65
A. FPGA Development
A.1. SignalTap II Logic Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2. DE3 System Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.3. DCC_Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
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B. PCB Design
B.1. Pilot Tone Board (Symmetric Design) . . . . . . . . . . . . . . .
B.1.1. PCB Layout - Pilot Tone Board (Symmetric Design) . .
B.1.2. PCB Schematic - Pilot Tone Board (Symmetric Design) .
B.2. Pilot Tone Board (Asymmetric Design) . . . . . . . . . . . . . .
B.2.1. PCB Layout - Pilot Tone Board (Asymmetric Design) . .
B.2.2. PCB Schematic - Pilot Tone Board (Asymmetric Design)
B.3. Bill of Materials (BOM) . . . . . . . . . . . . . . . . . . . . . .
B.4. List of Orders . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
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List of Figures
1.1. Albert Einstein and some of the tests of general relativity, along with examples of applications. Albert Einstein (top left), Eddington’s eclipse (top
middle), gravitational lensing (bottom left), Cassini-Huygens (bottom middle) and GPS navigation system (far right)[29]. . . . . . . . . . . . . . . .
1.2. Photo taken of one of the laboratories belonging to the Laboratory for Enabling Technologies at EADS Astrium [Astrium/HTWG]. . . . . . . . . . .
2.1. Geometrical representation of the effect of gravitational waves on free-falling
particles. The separation between particles will expand and contract perpendicularly to the direction of wave travel. The top row is resulted from
+ polarization and the bottom from × polarization [16]. . . . . . . . . . .
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.7.
3.8.
Artist’s conception of the LISA constellation [Astrium]. . . . . . . . . . . .
Orbital configuration of the LISA triad [ESA]. . . . . . . . . . . . . . . . .
Annular motion of the LISA constellation [ESA]. . . . . . . . . . . . . . . .
Basic principle of LISA’s measurement principle. Two free-falling proof
masses will fly within each LISA spacecraft. The distance variations between a pair of proof masses will then be measured over and a baseline of 5
million kilometers [Astrium]. . . . . . . . . . . . . . . . . . . . . . . . . . .
Current baseline design for the LISA to measure displacement between the
three spacecrafts. Essentially, three measurements will be performed individually: local proof mass to local optical bench (PM-OB), local optical
bench to remote optical bench (OB-OB), and remote optical bench to remote proof mass (OB-PM) [Astrium]. . . . . . . . . . . . . . . . . . . . . .
Basic setup of the polarizing heterodyne interferometer for the LISA optical
bench. A Polarizing Beam Splitter (PBS) is used to split the measurement
beam as required. The beams measurement beam is also combined with
reference beam prior to detection [Astrium]. . . . . . . . . . . . . . . . . .
Basic principle of Differential Wavefront Sensing. The measurement beams
are detected by a pair of Quadrant Photodiodes, and the wavefront is then
spatially resolved w.r.t a reference beam. The phase differences between the
pair of QPDs are then measured [Astrium]. . . . . . . . . . . . . . . . . . .
Gravitational wave sensitivity requirements for both LISA and LIGO [16].
4.1. Sensitivity requirements of the LISA phasemeter. . . . . . . . . . . . . . .
3
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vii
viii
List of Figures
4.2. Expected Doppler shift along the three interferometric arms of LISA [Astrium/ESA]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3. Expected Doppler drift along the three interferometric arms of LISA. . . .
4.4. Altera DSP Development Kit Statix II Edition. . . . . . . . . . . . . . . .
4.5. PSD plot showing the performance of the first phasemeter prototype developed at Astrium. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
Block diagram of a Digital Phase Locked Loop (DPLL). . . . . . . . . . . .
Architecture of the digital phasemeter implemented with a FPGA. . . . . .
Terasic development hardware utilized for the phasemeter implementation.
Data acquisition timing diagram for the AD9254 [3]. . . . . . . . . . . . . .
Block diagram of Direct Digital Synthesizer (DDS). . . . . . . . . . . . . .
Phasemeter Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phasemeter (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phasemeter (front panel). . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phasemeter (back panel). . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6.1. The effects of ADC jitter in the sampling process. . . . . . . . . . . . . . .
6.2. A 2-Way resistive splitter. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3. Circuit diagram for a pilot tone board designed with a symmetric 8-way
resistive splitter cascaded with a symmetric 2-way resistive combiner. . . .
6.4. Hybrid design of an asymmetric N-way resistive splitter combined with an
asymmetric 2-way resistive combiner. . . . . . . . . . . . . . . . . . . . . .
6.5. Asymmetric 2-way resistive splitter/combiner. . . . . . . . . . . . . . . . .
6.6. Circuit diagram for a pilot tone board designed with an asymmetric 8-way
resistive splitter cascaded with an asymmetric 2-way resistive combiner. . .
6.7. Phasor representation of phase noise introduced by cross-talk from adjacent
channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8. Pilot tone power loss path (DAC → ADC). . . . . . . . . . . . . . . . . .
6.9. Adjacent channel isolation path (QP Dn → ADCm ). . . . . . . . . . . . . .
6.10. HMC460LC5 wideband amplifier from Hittite Microwave [13] . . . . . . . .
6.11. HMC920LC5 active bias controller from Hittite Microwave [14] . . . . . . .
6.12. Wideband amplifier (SOT363 Package) from NXP Semiconductors [20]. . .
6.13. Block diagram of the final pilot tone board design. . . . . . . . . . . . . . .
6.14. Circuit schematic: LPF and 8-way splitter (symmetric design). . . . . . . .
6.15. Circuit schematic: LPF and 8-way splitter (Asymmetric design). . . . . . .
6.16. Circuit schematic: Wideband amplifier (w/ biasing circuitry) and 2-way
combiner (Symmetric design). . . . . . . . . . . . . . . . . . . . . . . . . .
6.17. Circuit schematic: Wideband amplifier (w/ biasing circuitry) and 2-way
combiner (Asymmetric design). . . . . . . . . . . . . . . . . . . . . . . . .
6.18. Circuit schematic: Linear voltage regulator. . . . . . . . . . . . . . . . . .
6.19. Pilot tone board layout (Symmetric design) . . . . . . . . . . . . . . . . .
6.20. Pilot tone board layout (Asymmetric design) . . . . . . . . . . . . . . . . .
34
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List of Figures
6.21. Pilot tone board (top side). . . . . . . . . . . . . . . . . . . . . . . . . . .
6.22. Pilot tone board (bottom side). . . . . . . . . . . . . . . . . . . . . . . . .
6.23. Close-up view of the 4 AD/DA conversion cards and the pilot tone board. .
7.1. DPLL frequencies measured by channels 1-2 (Top) and the calculated frequency difference between channels 1-2 (Bottom). As observed in the top
figure, the measured frequency at channel 1, shown in blue, seems to precisely match that of channel 2, shown in green. That would be the ideal case.
However, as observed in the bottom figure, there is residual time-dependent
noise present in the calculated frequency difference. . . . . . . . . . . . . .
7.2. DPLL phases measured by channels 1-2 (Top) and the calculated phase
difference between channels 1-2 (Bottom). As observed in the top figure, the
measured phase at channel 1, shown in blue, also seems to precisely match
that of channel 2, shown in green. Similarly, as in the frequency readout
case, there is residual time-dependent noise present in the calculated phase
difference. This is expected since the phase was obtained by integrating the
frequency measurements over time. . . . . . . . . . . . . . . . . . . . . . .
7.3. Detrended phase difference. . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4. Detected phase differences by 8 parallel channels. Differences are taken
pairwise between channels 1-2, 3-4, 5-6 and 7-8. . . . . . . . . . . . . . . .
7.5. PSD plot of the detected phase differences (Channels 1-2, 3-4, 5-6 and 7-8).
7.6. Comparison between the first and second phasemeter prototypes. . . . . .
7.7. Frequency dependency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8. Amplitude dependency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9. DPLL frequencies measured by channels 1-2 (Top), and the calculated frequency difference (Bottom) from a pilot tone generated with the FPGA
board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.10. DPLL phases measured by channels 1-2 (Top), and the calculated phase
difference (Bottom) from a pilot tone generated with the FPGA board. . .
7.11. Detrended phase difference of the detected pilot tone (generated with the
FPGA board). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12. PSD plot of the detected pilot tone (generated with the FPGA board). . .
7.13. Pilot tone corrections. 5 MHz and 5.5 MHz input signals. . . . . . . . . . .
7.14. Pilot tone corrections. 2 MHz and 2.5 MHz input signals. . . . . . . . . . .
A.1. Screen shot of the Signal Tap II Logic Analyzer which was used to inspect
the implmentation of the FPGA design. The current screen is displaying
the input signals are 8 parallel ADC channels. . . . . . . . . . . . . . . .
A.2. Screen shot of the System Builder software tool provided with the Terasic DE3 development kit. The current screen displays the top-level design
configuration of the DE3 Phasemeter. . . . . . . . . . . . . . . . . . . . . .
ix
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x
List of Figures
A.3. Second screen shot of the System Builder. This screen displays the necessary interconnections to integrate the DE3 FPGA motherboard with four
AD/DA conversion cards. . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.4. Block symbol file of the DCC_Driver design. . . . . . . . . . . . . . . . .
73
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List of Tables
2.1. Gravitational wave detection methods organized according to its spectral
character and targeted sources . . . . . . . . . . . . . . . . . . . . . . . . .
6.1. Power loss between the DAC and ADC ports of the proposed pilot tone
board designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2. Comparison of the isolation between adjacent channels for was of the proposed design (symmetric and asymmetric) . . . . . . . . . . . . . . . . . .
6.3. Amplifier selection for the assymetric pilot tone board design. . . . . . . .
6.4. Amplifier selection for the assymetric pilot tone board design. . . . . . . .
8
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41
45
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xi
List of Abbreviations
ADC Analog-to-digital converter. 19–21, 25, 28–37, 39, 40, 43, 53, 54, 57, 59, 63
DAC Digital-to-analog converter. 28, 30, 31, 35–37, 39, 43, 46, 59
DCO Data Output Clock. 30
DDS Direct Digital Synthesizer. 30, 31
DPLL Digital Phase-Locked Loop. 19–21, 23, 24, 27, 30, 31, 54
DWS Differential Wavefront Sensing. 15
EADS European Aeronautic Defence and Space Company. 4, 11, 19, 23
EFE Einstein’s Field Equations. 2
EJSM Europa Jupiter System Mission. 11
ESA European Space Agency. 3, 11
FIFO First In First Out. 20, 28
FPGA Field Programmable Gate Array. 19, 23, 25, 28–32, 35, 36, 53, 59–61
GPIO General Purpose Input/Output. 28, 31
GPS Global Positioning System. 2
GRS Gravitational Reference Sensor. 13
HSTC High-Speed Terasic Connector. 28
IIR Infinite Impulse Response. 26
IXO International X-ray Observatory. 11
LET Laboratory for Enabling Technologies. 4
LIGO Laser Interferometer Gravitational-Wave Observatory. 8, 16
xiii
xiv
List of Abbreviations
LISA Laser Interferometer Space Antenna. 3, 4, 11–14, 16–19, 21, 23, 34, 42, 61, 63, 65
LO Local Oscillator. 23
LPF Low Pass Filter. 23, 24, 47
LTP LISA Technology Package. 12
LUT Lookup Table. 27, 31, 61, 67
LVDS Low-voltage differential signaling. 30
MOSA Moving Optical Aubassembly. 13
NASA National Aeronautics and Space Administration. 3, 11
NCO Numerically Controlled Oscillator. 23–25, 27, 30, 31
OB Optical Bench. 13
PCB Printed Circuit Board. 49, 50
PD Phase Detector. 23–25
PI Proportional-Integral. 24, 27
PMS Phase Measurement System. 17
PSD Power Spectrum Density. 20, 56, 57
QPD Quadrant Photodiode. 15, 21, 36, 37, 43, 55, 65
RMS Root-mean-squared. 21, 33
TDI Time Delay Interferometry. 13
USO Ultra Stable Oscillator. 15, 19, 31
VHDL Very-high-speed integrated circuits Hardware Description Language. 19, 29
List of Symbols
G universal gravitational constant. 7
Gαβ Einstein tensor. 5
K0 gain factor. 24, 27
Ki integral term of a PI-controller. 27
Kp proportional term of a PI-controller. 27
Se error signal. 24, 27
Sh heterodyne signal. 33
Sin input signal. 24
Slpf low pass filter signal. 24
Sosc oscillator signal. 24
T αβ stress-energy tensor. 5
Vpp voltage peak-to-peak. 39
ZL load impedance. 36, 39
Zin input impedance. 36
Ω unit of electrical resistance. 36–39, 43, 44
δφjitter phase variation due to ADC jitter. 35
ηαβ Minkowski metric. 6
τa aperture uncertainty. 33
ϕin input phase. 24
ϕosc oscillator phase. 24
c speed of light. 7
f0 center frequency. 27
fclk clock frequency. 33
xv
xvi
fc cut-off frequency. 26
fh heterodyne signal frequency. 33, 34
fin input frequency. 24
fosc oscillator frequency. 24
fs sampling frequency. 26
h strain. 6, 7
mquad portion of mass which is involved with the quadrupole moment. 6
r distance. 7
v velocity. 7
List of Symbols
1. Introduction
1.1. A Brief History of General Relativity
In the late 19th century, a series of experiments lead to a great debate in the scientific
community. These experiments, being the most famous the Michelson-Morley experiment,
were aimed at detecting Earth’s motion relative to a hypothetical universal medium in
which light was thought to propagate (historically known as ether). To do so, Michelson
and Morley used a Michelson interferometer to measure the speed of light as Earth
completes one rotation around the Sun. If we were to be moving relative to a medium,
or an absolute inertial reference frame, the observed speed of light would change as Earth
changes its direction of travel throughout its orbit. In their experimentation however, such
behavior of light was not observed. This outcome not only served as evidence against the
existence of ether, but it also supported the notion that the speed of light is not dependent
on the speed of the observer.
As a result, a slight turmoil was caused amongst physicists. On one side, the constancy
of the speed of light was not admissible. It would simply shatter some of the most easily
accepted concepts in physics to that date, including the Galilean addition of velocities.
On the other side, due to the previously derived Maxwell’s equations, a constant speed of
light was indispensable. Following this debate, in 1905, Albert Einstein published a paper
entitled "On the Electrodynamics of Moving Bodies". In this paper Einstein introduced the
Theory of Special Relativity which combined the Principle of Relativity with the postulate
of constant light-speed. Special relativity allowed both the outcome of the Michlson-Morley
experiment and the Galilean addition of velocities to coalesce, but in return, it lead to very
strange implications such as length contraction, time dilation and failure of simultaneity.
Even though the theory could be mathematically proven with great vigor, it was incomplete
since it only applied to inertial (non-accelerating) frames of reference, and thus excluding
gravity.
For over a decade Einstein strived to extend special relativity to account for non-inertial
reference frames. His efforts finally culminated into the General Theory of Relativity
which was published in 1916. With general relativity, Einstein essentially unified Newton’s
Universal Law of Gravitation with the principles of special relativity. In order to do so,
he had to put forth an audacious view that gravity should be interpreted not as a force,
but as a curvature of spacetime. Thus, planets orbit around the Sun not due to a force of
attraction between them, but simply because they are following the shortest path through
1
2
CHAPTER 1. INTRODUCTION
the curved dimensions of spacetime, also known as geodesic. In this case, of course, the
curvature of spacetime is inflicted by the Sun’s mass. In fact, it follows from relativistic
notions that any amount of mass-energy will inflict a corresponding amount of curvature
in spacetime.
The geometry of warped spacetime due to mass-energy is described by Einstein’s Field
Equations (EFE). The EFE are a set of dreadfully complex equations, but under special
circumstances (i.e. low velocity, small mass and large distances) it reduces to the Newtonian description of gravity. Which is why Newton’s Laws were enough to majestically
describe the motions of planets in our Solar System for many years. However, there was
at least one known exception to this case. As early as the late 1800s, discrepancies were
observed between Mercury’s orbital motions with that which was predicted according to
Newtonian mechanics. A similar case had already been observed with Uranus, but the
very same Newtonian mechanics predicted that such discrepancies would be caused by the
gravitational pull of a, yet unknown, nearby planet. Consequently, Neptune was discovered
at the precise location as predicted. With that in mind, astronomers struggled in vain to
discover a new planet which could be perturbing Mercury’s orbit. Obviously, nothing was
ever found and the mystery remained. Interestingly enough, such peculiar orbital motions
were precisely predicted by general relativity as a phenomenon which is now known as
precession of perihelion. In fact, in the very same paper in which Einstein introduced
general relativity, he uses relativistic formulations to accurately calculate Mercury’s orbit,
and thus solving the mystery.
General relativity also predicted other post-Newtonian effects such as the deflection of light
due to gravitational fields. This was first observed by astronomer Sir Arthur Eddington
while observing a solar eclipse in 1919. Due to the deflection of light by the Sun’s gravity,
stars should appear to shift their position as they pass behind the Sun. This was exactly
what Eddington observed, and he then published his results. With these publications,
Einstein became internationally famous overnight. Today, astronomers take advantage
of light deflection with a technique called gravitational lensing. Basically, this works by
observing cosmological objects as they pass behind other massive objects which bend the
light of the source into a focal point, and thus functioning as a giant cosmic lens. Such
technique allows astronomers to gaze deeper into the cosmos in the search for exoplanets
and beyond.
Another phenomenon predicted by general relativity is known as gravitational redshift.
Gravitational redshift is the result of the loss of energy by light as it escapes a gravitational
field. Since light can’t slow down, it loses energy by reducing its wavelength; hence it is
red-shifted. This has been demonstrated experimentally in laboratories as it was done in
the Pound-Rebka experiment. It was also verified with an experiment performed with the
Cassini-Huygens space probe. Nowadays, the Global Positioning System (GPS) take into
account gravitational redshift effects in order to perform time-stamp corrections. Without
such corrections, the GPS system would not remain accurate for more than a few minutes.
These post-Newtonian effects discussed so far have been verified with an overwhelming
1.1. A BRIEF HISTORY OF GENERAL RELATIVITY
3
Figure 1.1.: Albert Einstein and some of the tests of general relativity, along with examples
of applications. Albert Einstein (top left), Eddington’s eclipse (top middle),
gravitational lensing (bottom left), Cassini-Huygens (bottom middle) and GPS
navigation system (far right)[29].
amount of evidence. However, the implications of general relativity are far vaster, and
that perhaps was the beauty of Einstein’s genius. He predicted a new range of physical
phenomena which were previously inconceivable to human imagination. Now, for almost
one century since his publication, many of his predictions are still being tested, and perhaps
the greatest discoveries are yet to come. Arguably, one of the most promising scientific
fields for the near future concerns a post-Newtonian effect which has yet to be directly
detected - gravitational waves.
The first direct detection of gravitational waves is greatly anticipated by physicists since
it would lead to a whole new observational spectrum, which would allow us to literally
gaze at the edges of the Universe. It would allow us to observe phenomena which not even
light can escape from such as the primordial cosmic fluctuations of the early Universe and
the depths of super-massive black holes. It is speculated that these observations could test
general relativity to its limits, and even brake the grounds for the foundations of the Theory
of Everything (in which gravity is unified with quantum mechanics, and thus equating to
Quantum Gravity).
In the pursuit of gravitational waves, ESA and NASA are currently planning a space-based
gravitational wave detector named Laser Interferometer Space Antenna (LISA). Now, over
one century years after the Michelson-Morely experiment, scientists and engineers are
again at the verge of scientific revolution. This time however, with a virtual Michelson
interferometer with an arm length almost fifteen times greater than the distance from
the Earth to the Moon.
4
CHAPTER 1. INTRODUCTION
1.2. Thesis Overview
The main goal of this thesis work was the development of an ultra-precise phasemeter for
LISA. During this development, the scientific and technical requirements of the LISA space
mission were also investigated.
This thesis work was performed in the Laboratory for Enabling Technologies (LET) at
Astrium, the aerospace subsidiary of the European Aeronautic Defence and Space Company (EADS). LET is part of the Science Missions and Systems department of Astrium
Satellites (Friedrichshafen, Germany) and it is operated in cooperation with the Constance
University of Applied Sciences. The current activities at LET are mainly concerned with
the development of state-of-the-art enabling technologies for LISA. Some of the current
undergoing research topics are:
• Picometer & Nanoradian Heterodyne Interferometry
– Novel Integration Techniques for Ultrastable Opto-Mechanical Systems
– Development of RF Quadrant Photodetectors
– Development of an Ultra-precise Digital Phasemeter
– Laser Freqeuncy Stabilization to Optical Resonators
• Precision Dilatometry
• Validation of In-Field Pointing Concepts for LISA
• Investigation towards micro-Newton ion thrusters
• High precision metrology
Figure 1.2.: Photo taken of one of the laboratories belonging to the Laboratory for Enabling
Technologies at EADS Astrium [Astrium/HTWG].
2. Gravitational Waves
2.1. What Are Gravitational Waves?
Gravitational waves are ripples in the fabric of spacetime. They are generated by massiveenergetic objects while undergoing colossal accelerations. Such events induce gravitational
field fluctuations which propagate from the source at the speed of light. As a result,
spacetime stretches and compresses perpendicularly to the direction of wave travel. When
detectable, an observer would notice fractional length changes, or strains, in spacetime.
Although they were never directly detected, indirect evidence of gravitational waves was
first presented by monitoring the orbital decay of the Hulse-Taylor binary star system
(PSR-1913+16). Orbital decay is predicted to occur by general relativity since the energy
radiated by gravitational waves will lead orbiting bodies to inspiral towards each other.
The predictions precisely matched the orbital decay measurements which were made over
several years. The 1993 Nobel Prize was awarded to Hulse and Taylor for the discovery
of PSR-1913+16; and for identifying it as a pulsar in orbit with another neutron star by
measuring the period between radio pulses.
2.2. Mathematical Description
General Relativity can be mathematically described, in abbreviated form, by the following
relation
Gαβ = 8πT αβ
(2.1)
where Gαβ is the Einstein tensor and T αβ is the stress-energy tensor, both given in component notation [1]. The Einstein tensor defines the geometry of curved spacetime induced
by a gravitational field which is quantified by the stress-energy tensor. The indices αβ take
values from [0 1 2 3] which represents the four-coordinate system (t,x,y,z) of Minkowski
space. Given that these are symmetric tensors in 4-dimensional spacetime, then this relation should be regarded as a system of ten coupled differential equations. Therefore, for a
given source T αβ , this system should be solved for ten components gαβ . Solving this system
is not only computationally demanding, but in some cases, impossible. For a more practical approach, the system can be reduced by making certain approximations. A commonly
5
6
CHAPTER 2. GRAVITATIONAL WAVES
used method is the weak-field approximation which considers the source to be far away. In
this case, spacetime can be considered to be nearly flat, and therefore the nonlinear terms
of the system may be neglected. The curvature tensor gαβ can then be simply expressed
with the Minkowski metric ηαβ plus a very small perturbation, or strain, hαβ [4].
gαβ = ηαβ + hαβ
(2.2)
Using the transverse-traceless gauge, the general solution from (2.2) can be found as [8]
0
0
0
0 h
h
+
×
=

0 −h× h+
0
0
0

hαβ
0
0

 exp (jwt − jkx) .
0
0

(2.3)
From (2.3), it can be determined that the general solution for the strain h, in the given
weak-field approximations, comes in form of a wave equation. It also follows from this
relation that the leading order of radiation is quadrupolar (as opposed to dipolar for EM
waves), and the quadrupolar moment can be + polarized (h+ ) or × polarized (h× ).
The effects of gravitational waves on free-falling particles in spacetime is shown in Figure
2.1. As the wave propagates, the lengths between particles will expand and contract
perpendicularly to the direction of propagation. The direction of expansion and contraction
depends on the type of polarization.
Figure 2.1.: Geometrical representation of the effect of gravitational waves on free-falling
particles. The separation between particles will expand and contract perpendicularly to the direction of wave travel. The top row is resulted from +
polarization and the bottom from × polarization [16].
The magnitude of the strain h induced by a source mquad (portion of mass which is involved
with the quadrupole moment) is given by
Gmquad v 2
h∼
,
rc4
(2.4)
7
2.3. DETECTION METHODS
where G is the universal gravitational constant, c is the speed of light, v if the velocity of
the source and r is the distance from the source [25]. By calculating the order of magnitude
of the constant term in (2.4) as
G
∼ 10−50 ,
4
c
(2.5)
it becomes clear that gravitational radiation coupled to the source is remarkably small.
The strain h can also be expressed as a relative length change
h∼
∆L
,
L
(2.6)
where ∆L is the length variation of a length, or baseline, L.
2.3. Detection Methods
Due to the extremely small magnitude of gravitational wave strains, major technical difficulties arise when attempting to detect them. Nevertheless, it is predicted that the universe
is swarming with gravitational waves from a multitude of sources. This allows for various
methods of direct (or indirect) detection, each depending on the targeted source. Both
the source and its corresponding detection method can be well categorized based on the
spectral character of the gravitational waves.
The detections methods presented in Table 2.1 are briefly described as follows:
• Cosmic microwave background anisotropy. By studying the anisotropies of the
cosmic microwave background (CMB), it would be possible to find trace signatures
of gravitational waves arising from the early Universe and even the Big Bang.
• Millisecond pulsar timing. Pulsars are perhaps one of the most accurate clocks
in the Universe. However, a passing gravitational wave would cause irregularities
in the observed period between pulses. Radio astronomers are currently attempting
to identify these irregularities in order to correlate them with possible gravitational
wave sources.
• Spacecraft tracking. In principle, gravitational waves can be detected by observing
very small fluctuations in the radio round-trip time between Earth and interplanetary
spacecrafts.
• Resonant bar detectors. These were the first purpose-built gravitational wave
detectors. Also known as Weber bars (name after its inventor Joseph Weber), these
devices are designed to resonate at the frequency of the targeted gravitational wave.
8
CHAPTER 2. GRAVITATIONAL WAVES
Table 2.1.: Gravitational wave detection methods organized according to its spectral character and targeted sources
Detection Method
Frequency (Hz) Wavelength
Sources
Cosmic microwave background anisotropy
10−16
109 ly
Early universe
Pulsar timing
10−9
10 ly
Early universe, cosmic strings
Space-based laser interferometer, spacecraft
tracking
10−4 to 10−1
10−2 AU to 10 AU
Compact
binary
systems, supermassive black holes,
extreme mass ratio
inspirals
300 km to 30,000 km
Supernovae, spinnig neutron stars,
inspirals
Earth-based laser inter- 101 to 103
ferometer, resonant bar
detectors
The resonance would amplify the effects of the gravitational wave and thus allowing
for detectable changes in the length of these bars.
• Laser interferometry. Laser interferometry can be used to precisely determine the
distance between free masses. An incident gravitational wave can then be detected
by observing small fluctuations in the measured distances. The interferometer setup
can be either Earth-based or space-based.
– Earth-based. On Earth, these interferometers can be realized with vacuum tunnels with up to a few kilometers in length.
– Space-based. In space, the setup can be realized with inter-spacecraft laser
ranging, with an interferometer armlength up to millions of kilometers long.
The detection of gravitational waves has been mainly limited so far by the very high
sensitivity required by these detection methods. Currently, one of the most promising
method of detection are the Earth-based laser interferometry detectors. These have
already achieved the required sensitivity, and several are already operational throughout the world: Laser Interferometer Gravitational-Wave Observatory (LIGO) in the
USA, TAMA in Japan, GEO600 in Germany and VIRGO in Italy. However, these
detectors have their sensitivity bounded by disturbances on the Earth’s surface, and
by the achievable physical dimensions of the interferometric arm length (few kilometers). This limits the detection range to cosmological events which are relatively
2.3. DETECTION METHODS
9
infrequent and of very short durations (i.e. supernovae). Therefore, Earth-based
detectors may have to wait another decade or so until their first detection.
The limitations of Earth-based detection can be avoided by realizing a space-based
detector. With the quietness of space and an interferometric arm length with up to
a few million kilometers, these detectors would be able to target guaranteed sources,
(i.e. compact binary systems) which thousands are known to exist in the Milky-way
alone. They would also be able to target one of the most intriguing cosmological
objects - black holes. As we will see in the following chapter, a space-based detector
is already being planned, which would provide an invaluable complement to its Earthbase counterparts.
3. The LISA Mission
The LISA mission is a joint ESA/NASA project which has as its primary goal, to detect
and observe gravitational waves from astronomical sources. The low-frequency gravitational waves which are targeted by LISA are not accessible by Earth-based observation.
Furthermore, on the Earth’s surface, these signals would be drowned by local gravitational
noise arising from seismic activities and atmospheric disturbances. Therefore, LISA was
planned as a space-based detection scheme which would consist of three spacecrafts in heliocentric, Earth-trailing orbits. This setup would be used to measure picometer variations
over a distance of 5 million kilometers by means of interferometric laser ranging between
the spacecraft triad.
Figure 3.1.: Artist’s conception of the LISA constellation [Astrium].
Currently, LISA is part of Cosmic Vision 2015-2025, which is ESA’s current cycle for longterm planning for space science missions. It has been classified as an L-Class (Large)
mission along with two other space science missions, EJSM/Laplace and IXO/XEUS [10].
One of these missions will be selected to fly in a launch window which is scheduled, at
earliest, for 2020. Nevertheless, the LISA project is already engaged in Phase A at both
ESA and NASA since 2004. Since 2005, EADS Astrium has been a major player in the
design of LISA as it was contracted by ESA to perform a Mission Formulation Study. The
preparations for LISA will also take an important step with the LISA Pathfinder mission
which is due for launch in 2011. LISA Pathfinder will fly the LISA Technology Package
(LTP) which will demonstrate key technologies for the LISA mission.
11
12
CHAPTER 3. THE LISA MISSION
3.1. Mission Overview
Essentially, the LISA constellation will form three interferometric baselines with a nominal
arm length of 5 million kilometers. The spacecrafts will orbit the Sun in a quasi-equilateral
triangular formation, with its plane inclined by 60 degrees in respect to the ecliptic, while
trailing Earth by 20 degrees (Figure 3.2). Each spacecraft will occupy its own heliocentric
orbit with different values for right ascension and inclination, which will cause the triangle
to rotate annually (Figure 3.3).
Figure 3.2.: Orbital configuration of the LISA triad [ESA].
Figure 3.3.: Annular motion of the LISA constellation [ESA].
The orbital configuration was designed to minimize unwanted disturbances while maintaining an optimal range for communications. The circular orbit will maintain the spacecrafts
3.2. MEASUREMENT PRINCIPLE
13
at a nearly constant distance of 1 A.U. from the Sun, and thus reducing variations in temperature, solar wind intensity, and solar radiation pressure. It is critical to minimize such
disturbances and variations as they could "leak" into the frequency band of the gravitational
wave sources.
The spacecraft triad will be launched simultaneously by an Atlas V rocket into a parking
orbit. Each spacecraft will be equipped with its own propulsion module which will set them
on a 14-month long transfer orbit. Upon arrival at the destination, the propulsion modules
will be jettisoned. The triad’s flying formation is designed to remain in shape by means
of orbital mechanics only. Therefore, further station-keeping burn maneuvers would not
be necessary. However, tidal forces will cause the formation to "breathe". In other words,
the distances between spacecrafts will vary in up to 50,000 km. The spacecraft triad and
its orbital configuration shall remain within its operational limits for at least 5 years as
determined by the nominal mission lifetime.
3.2. Measurement Principle
The LISA interferometric metrology system will detect gravitational waves by measuring
distance variations between free-falling proof masses. Within each LISA spacecraft, two
proof masses will float in space, ideally isolated from any disturbance other than gravity.
These will essentially act as mirrors of a virtual Michelson-type interferometer. The interferometric setup will be comprised of two Moving Optical Aubassembly (MOSA) units
aboard each spacecraft. The MOSA has as its main constituents an Optical Bench (OB),
a Gravitational Reference Sensor (GRS) and a 40 cm telescope.
Figure 3.4.: Basic principle of LISA’s measurement principle. Two free-falling proof masses
will fly within each LISA spacecraft. The distance variations between a pair of
proof masses will then be measured over and a baseline of 5 million kilometers
[Astrium].
The distance variations between two proof masses L12 are to be measured in three parts:
14
CHAPTER 3. THE LISA MISSION
• d1 , local proof mass to local optical bench
• d12 , local optical bench to remote optical bench
• d2 , remote proof mass to remote optical bench
This so-called "strap-down architecture", as displayed in Figure 3.5, has the advantage
of simplifying the development of the system since the long-arm interferometer and the
free-falling proof mass metrology have their own set of challenges. The three individual
measurements will be combined on ground and the potential gravitational wave signals will
be extracted with a process called Time Delay Interferometry (TDI).
Figure 3.5.: Current baseline design for the LISA to measure displacement between the
three spacecrafts. Essentially, three measurements will be performed individually: local proof mass to local optical bench (PM-OB), local optical bench
to remote optical bench (OB-OB), and remote optical bench to remote proof
mass (OB-PM) [Astrium].
It should be emphasized here that only the distance variations, not the absolute distance,
between spacecrafts are important. Hence, the desired measurements can be achieved by
setting up an inter-spacecraft Doppler Link. This can be done by transmitting a laser beam
and combining it with that which was reflected from the distant spacecrafts. Due to the
large distances involved, direct reflection is not viable. Instead, LISA shall employ an active
transponder scheme. In this scheme, the received laser beams are combined with a local
oscillator derived from the transmitted beams, and the phase difference is then measured.
In this way, the laser frequencies can be controlled so that the phase of the transmitted
signal is an exact replica of received signal. When recombining the transmitted and received
laser beams, a beat note is produced which should contain a predictable Doppler Shift due
to constellation "breathing" (Section 3.1). A passing gravitational wave could then be
identified by observing variations of this predicted Doppler shift.
The sinusoidal beat note measurements will be performed by polarizing heterodyne interferometry [9]. A diagram demonstrating this metrology principle is shown in Figure
3.2. MEASUREMENT PRINCIPLE
15
3.6. Aboard the spacecrafts, two active laser heads will supply each optical bench and its
respective interferometer arm. Since the received and transmitted laser beams will share a
common telescope, linear orthogonal polarization will be used for signal multiplexing. The
individual beat note phases are then measured with a digital phasemeter w.r.t an Ultra
Stable Oscillator (USO).
Figure 3.6.: Basic setup of the polarizing heterodyne interferometer for the LISA optical
bench. A Polarizing Beam Splitter (PBS) is used to split the measurement
beam as required. The beams measurement beam is also combined with reference beam prior to detection [Astrium].
The phase of the heterodyne signals will also be spatially resolved by means of Differential
Wavefront Sensing (DWS). This is accomplished by combining heterodyne interferometry
with a spatially resolved phase measurement through the use of Quadrant Photodiodes
(QPDs). The signals obtained from the individual quadrants show relative phase shifts,
depending on the spatially dependent phase difference. The use of DWS allows for the
determination of spacecraft alignment and proof mass orientation.
Figure 3.7.: Basic principle of Differential Wavefront Sensing. The measurement beams
are detected by a pair of Quadrant Photodiodes, and the wavefront is then
spatially resolved w.r.t a reference beam. The phase differences between the
pair of QPDs are then measured [Astrium].
16
CHAPTER 3. THE LISA MISSION
3.3. Scientific and Technical Requirements
The scientific and technical requirements for LISA are mainly driven by the frequency band
of the targeted gravitational wave sources,
which ranges from 10−4 Hz to 10−1 Hz. The
√
expected strains are in the order of 10−20 / Hz. Therefore, LISA must be able to measure
distance√variations between the free-falling proof masses with a sensitivity in the order of
12 pm/ Hz. A graph displaying the required strain sensitivity versus frequency is shown
in Figure 3.8. The displayed graph also provides a comparison of the LISA requirements
with the Earth-based detector LIGO. As observed, the requirements for LISA are more
relaxed, and each detection method is aimed at a different variety of gravitational wave
sources.
Figure 3.8.: Gravitational wave sensitivity requirements for both LISA and LIGO [16].
4. LISA Phasemeter Overview
4.1. General Requirements
The main purpose of the LISA phasemeter is to measure phase variations of sinusoidal
beat signals from a heterodyne interferometer. These phase measurements will contain the
path length variations of the interferometer arms. A path length variation of one wavelength will correspond to approximately 1 µm, which translates into a heterodyne signal
phase
√ variation of 2π radians. Therefore, in order to achieve the required sensitivity of 12
pm/ Hz,
√ the phase measurements has to be performed with
√ mircoradian precision (few
µcycles/√ Hz). Correspondingly, a noise budget of 1 pm/ Hz (allocated from the overall
12 pm/ Hz) was assigned to the Phase Measurement System (PMS). The required sensitivity is shown in Figure 4.1. At frequencies below approximately 3 mHz, the requirements
are relaxed since the sensitivity limitations become dominated by residual acceleration
noise.
-2
10
-3
φ (rad/√Hz)
10
-4
10
-5
10
-6
10
-7
10 -4
10
-3
10
-2
-1
10
10
0
10
1
10
f (Hz)
Figure 4.1.: Sensitivity requirements of the LISA phasemeter.
The frequencies of the heterodyne signals will be of a few MHz. However, due to the expected Doppler shifts arising from the relative motions between spacecrafts, the heterodyne
frequencies will drift in the range of 2 to 20 MHz. Therefore, the chosen phase detection
17
18
CHAPTER 4. LISA PHASEMETER OVERVIEW
scheme shall be able to track varying frequencies. The profile of the varying frequencies
can be determined from the expected Doppler shift versus the mission lifetime (Figure 4.2).
As observed, the Doppler shift will vary in up to, approximately, 15 MHz.
20
Arm 1
Arm 2
Arm 3
15
Doppler Shift [MHz]
10
5
0
-5
-10
-15
0
500
1000
1500
2000
2500
3000
3500
t [days]
Figure 4.2.: Expected Doppler shift along the three interferometric arms of LISA [Astrium/ESA].
By taking the derivative of the expected Doppler shift (given by the data provided in
Figure 4.2), the frequency drift was then determined as shown in Figure 4.3. Therefore,
the LISA phasemeter shall also be able to track frequency drifts at rates up to 4 Hz/s,
under the given sensitivity requirements.
5
Arm 1
Arm 2
Arm 3
Doppler Shift Drift Rate [Hz/s]
4
3
2
1
0
-1
-2
-3
-4
0
500
1000
1500
2000
2500
3000
3500
t [days]
Figure 4.3.: Expected Doppler drift along the three interferometric arms of LISA.
4.2. PROTOTYPE DEVELOPMENT
19
Aside from measuring heterodyne signals w.r.t to a USO, the phasemeter is also required to
measure clock noise between individual spacecrafts relative to a master clock. Furthermore
the phasemeter will also be used to demodulate/decode pseudo-random code sequences for
inter-spacecraft communications and clock synchronization. Since these signals will share
the same telescope and detector, the phasemeter shall also be able to detect multiple tones.
4.2. Prototype Development
Prior to commencement of this thesis work, EADS Astrium had already developed a first
prototype of an ultra-precise digital phasemeter. The design was fully implemented in a
Field Programmable Gate Array (FPGA). A FPGA is essentially a programmable integrated circuit which can be used to implement digital functions. It can be programmed
with hardware description languages such as VHDL (Very-high-speed integrated circuits
Hardware Description Language) or Verilog. For the LISA phasemeter, FPGAs are preferred over microprocessors due to its capability to process multiple parallel channels at
high-speed.
The hardware implementation was done with an Altera DSP Development Kit Statix II
Edition with a Stratix II EP2S60F1020C FPGA chip on board (Figure 4.4). The analog
inputs are provided by a two-channel, 12-bit, 125-million samples per second (125 MSPS),
Analog-to-digital converter (ADC). The development board also contain a RS232 serial
port to interface the FPGA with a computer.
Figure 4.4.: Altera DSP Development Kit Statix II Edition.
The first prototype supported two parallel channels which had analog inputs provided by
the two-channel ADC on board. Once digitized, each input signal is driven into a Digital
Phase-Locked Loop (DPLL), which performs phase readings by tracking the frequency of
the input signal. A phase locked loop is used so that the frequency of the DPLL is locked
with the frequency of the input signal. This is necessary due to the expected Dopplershifted frequency drifts.
20
CHAPTER 4. LISA PHASEMETER OVERVIEW
The ADC sampling and DPLLs are clocked by a built-in 100 MHz crystal oscillator on
the development board. Following the DPLLs, the phase read-outs are decimated from
100 MHz to approximately 12 Hz by a decimation (or averaging) filter. Downsampling is
required since the Earth-space communications link must operate with a data transfer rate
much lower than 100 Mhz. It is also required for the prototype implementation because
the data transfer via the RS232 must also operate at much lower rates. In order to perform
the RS232 interface, the measured phase and frequency of the input signals are stored in
a First In First Out (FIFO) stack. The registers containing the measured values are then
transferred bit-by-bit through the serial interface. More details on the implementation and
design of the first prototype are available in [11].
4.2.1. Status Review
The performance of this implementation was evaluated by plotting the Power Spectrum
Density (PSD) of the phase difference between two equal signals, measured at different
ADC channels. Ideally, since the signals are equal, the phase difference should be zero.
However, due to noise sources in the phase measurement process, the measured phase
differences are actually non-zero. The PSD allow us to determine whether the phase noise
levels of the time-varying residuals are within requirements for frequency band of interest
(see Figure 4.1). The PSD plot for a typical phase difference measurement for the first
phasemeter prototype is shown in Figure 4.5. As observed, the first prototype did not yet
fully fulfill the requirements.
PSD
-2
1/2
with ts: 0.083333 s, Win: blackmanharris, Seg: 9 and Ovl: 50 %
10
First Prototype
LISA Requirement
-3
φ (rad/√Hz)
10
-4
10
-5
10
-6
10
-7
10 -4
10
-3
10
-2
-1
10
10
0
10
1
10
f (Hz)
Figure 4.5.: PSD plot showing the performance of the first phasemeter prototype developed
at Astrium.
A study was performed and it was determined that ADC jitter could be responsible for
4.2. PROTOTYPE DEVELOPMENT
21
higher phase noise levels at this frequency range. This was determined by inspecting the
Root-mean-squared (RMS) values of the measured phase differences. The calculated RMS
values corresponded to the timing jitter as specified by the datasheet of the onboard ADC
chip, which is given as 0.25 ps.
The first prototype implementation was regarded as a success since it verified that both
the DPLL design and data transfer protocol were functional. It also allowed for the identification of technical limitations (i.e. ADC jitter) which could hinder the phasemeter’s
performance. A second prototype was then devised which would extend the phasemeter to
8 parallel channels. This would allow for the demonstration of phase difference measurements between a pair of QPDs (1 phase reading per quadrant). The extension of channels
is also necessary since the actual LISA phasemeter would require as many as 58 parallel
channels. With that in mind, the new phasemeter system shall be implemented in such
a way that further channel extension is made easy. Furthermore, the new prototype shall
also support a pilot tone calibration scheme (described in Chapter 6) which could be used
for ADC jitter corrections. For Chapter 5, it is sufficient to know that the pilot tone
calibration scheme requires that the phasemeter is able to generate and detect pilot tone,
which can essentially be an analog sine wave.
5. Development of a FPGA-based
Digital Phasemeter
In this chapter, the development of a FPGA-based digital phasemeter is described. More
specifically, it concerns the development of the second LISA phasemeter prototype at EADS
Astrium. However, prior to the discussion on the implementation of the second prototype,
it is important to understand the previous implementation. This is necessary not only to
properly migrate the digital phasemeter design to the new hardware implementation, but
also to gain a better understanding of the background theory.
5.1. DPLL Basics
The DPLL, as observed in Figure 5.1, is basically composed of a Phase Detector (PD),
Low Pass Filter (LPF) and a Numerically Controlled Oscillator (NCO).
PD
Sin
Spd
LPF
SNCO
Slpf
NCO
Figure 5.1.: Block diagram of a Digital Phase Locked Loop (DPLL).
The behavior of a DPLL can be mathematically described as follows:
Initially, the input signal is mixed with a Local Oscillator (LO), which in this case is
provided by the NCO. The output of the PD then yields
Spd (t) = Sin · Sosc
(5.1)
23
24
CHAPTER 5. DEVELOPMENT OF A FPGA-BASED DIGITAL PHASEMETER
Given an input signal Sin with frequency fin and phase ϕin , and an oscillator signal Sosc
with frequency fosc and phase ϕosc :
Sin (t) = Ain sin(2πfin t + ϕin )
(5.2)
Sosc (t) = Aosc cos(2πfosc t + ϕosc ),
(5.3)
we can then re-write the PD output as
Ain Aosc
Spd (t) =
2
"
sin 2π (fin − fosc ) t+ϕin −ϕosc +sin 2π (fin + fosc ) t+ϕin +ϕosc
#
.
(5.4)
As observed in (5.4), the output of the PD will contain both the sum and difference
of frequencies from the input and oscillator signals. Assuming the oscillator and input
frequencies are locked, then the difference frequency (fin - fosc ) should be zero. Therefore,
only the sum frequency (fin + fosc ) should remain. By passing this signal through a LPF,
then only the constant term remains. We can then approximate the output of the LPF,
Slpf , as
Ain Aosc
sin(ϕin − ϕosc ).
Slpf (t) ≈
2
(5.5)
Hence, the LPF signal will be proportional to the phase difference between the input and
oscillator signals. Since the NCO has to lock itself to the input signal, it interprets (5.5)
as a phase error multiplied by a gain factor. The LPF signal then becomes
Slpf (t) ≈ Kpd · sin (ϕerror ) .
(5.6)
Given (5.6), an error signal can be derived with a Proportional-Integral (PI) controller.
The output of the PI controller, Se , is then multiplied with a gain factor K0 , to find the
frequency difference ∆ω, which is used to update the frequency of the NCO. The NCO
frequency is then integrated to update the NCO phase. Since a PI controller is used in
the control loop, then the error signal can be reduced to zero. When this happens, it is
then said that the DPLL is locked, and in this case the phase difference (ϕin - ϕosc ) is also
reduced to zero. Consequently, the frequency and phase of the input signal will be equal
to that of the oscillator signal. The phase of the input signal can then be determined by
directly reading the phase of the oscillator signal.
25
5.2. FPGA ARCHITECTURE
5.2. FPGA Architecture
A functional diagram displaying the architecture of the first prototype is displayed in Figure
5.2. In this section, each of the architectural components and its digital implementation
are elucidated.
Spd
Sin
Digital Filter
(IIR)
Slf
Snco
ω0
NCO
LUT
φnco
ωnco
Δω
K0
Se
PI-Controller
Decimation
Filter
Data Block
Decimation
Filter
FIFO
RS-232
Figure 5.2.: Architecture of the digital phasemeter implemented with a FPGA.
5.2.1. DPLL
Phase Detector
The phase detector was implemented by simply multiplying the input signal with the NCO
signal. Since the input signal is provided by a 12-bit ADC in two’s complement format, the
NCO signal was designed to have the same format. This allows for the FPGA to perform
simpler and more efficient calculations. The output of the PD is then driven to a 24-bit
register (in binary multiplication, the bit-length of the product should be equal to the sum
of the bit-lengths of the factors).
Digital IIR Filter
The digital filter was implemented based on the transfer function of an ordinary first-order
low pass filter, which can be written as
26
CHAPTER 5. DEVELOPMENT OF A FPGA-BASED DIGITAL PHASEMETER
GL (s) =
1
1+
1
s
2πfc
(5.7)
where fc is the cut-off frequency.
In discrete time, the transfer function (5.7) can be realized as an Infinite Impulse Response
(IIR) filter. The transform function of a digital IIR filter takes the form of
L(z) =
α0 + α1 z −1
,
1 + β1 z −1
(5.8)
where in this case
α0 = α1 =
1
fs
1 + πf
c
(5.9)
and
β1 =
1−
1+
fs
πfc
fs
πfc
(5.10)
where fs is the sampling frequency. For the phasemeter design fs is 100 MHz and a cut-off
frequency chosen as 1 MHz. With these values we can calculate the filter coefficients as
α0 = α1 = 0.03; β1 = −0.939
(5.11)
However, for a better implementation, the filter was realized by performing the substitution
β1 = −1 + β10 ,
(5.12)
where β10 = -0.061.
In this way, the division in the transfer function given by (5.8), can be avoided. The digital
IIR filter can then be simply implemented as
Slf = Spd · α0 + Spd · α1 · z −1 − Slf · β10 .
(5.13)
Since the coefficients α0 , α1 are approximately equal to 2−4 and β10 is approximately 2−5 ,
then it became possible to implement the multiplications with bit-shifting.
27
5.2. FPGA ARCHITECTURE
Numerically Controlled Oscillator
The NCO is composed of a PI controller, gain factor, frequency resister, phase register
and a Lookup Table (LUT). The first component in the signal path of the NCO is the PI
controller, which has a transfer function given by
GF (s) = Kp +
Ki
.
s
(5.14)
where Kp and Ki are the proportional and integral terms of control loop, respectively. In
its digital form, this transfer function can be rewritten as
F (z) = Kp +
1 Ki
fs 1 − z −1
(5.15)
For this implementation, the following controller parameters were used:
Kp = 1.257 · 106 ∼ 220
(5.16)
5.67 · 1011
Ki
∼ 212
=
8
fs
10
(5.17)
The output of the PI controller yields the error signal Se , which is then multiplied by a
gain factor to give the frequency difference ∆ω. In this case, the gain factor K0 is 2−8 .
The frequency difference is then added with the center frequency, f0 in order to update the
frequency of the DPLL. The DPLL frequency is then integrated to obtain the phase. The
phase value is then used to as input to the LUT in order to synthesize the NCO signal.
The LUT in this case is essentially an array of 1024 values of a quarter of a sine wave. The
NCO frequency is then determined by the phase increment provided to the LUT. Assuming
a phase increment x, the NCO frequency would be given by
fnco =
fclk · x
,
2n
(5.18)
where 2n is the total number of steps of the full sine wave (in this case 4096).
5.2.2. Decimation Filter
The decimation filter can be realized by averaging n samples. Hence, the transfer function
if given by
28
CHAPTER 5. DEVELOPMENT OF A FPGA-BASED DIGITAL PHASEMETER
G(z) =
X
1 n−1
z −i .
n i=0
(5.19)
The decimation filter was configured to decimate the 100 MHz clock into approximately
12 Hz. Therefore, in this case, n is equal to 223 .
5.2.3. Data Transfer
The data transfer from the FPGA to a PC is essentially performed in three steps. First,
the decimated phase and frequency readouts are packaged into a data block. Subsequently,
the data block is stored in a FIFO stack. The FIFO is then read at a rate of one byte per
clock cycle, while each byte is transfered bit-by-bit through a RS232 interface. The baud
rate can be configured from 1200 Baud/s and 115200 Baud/s.
5.3. Hardware Implementation
The second prototype was implemented on a Terasic Altera DE3 development board with a
Stratix III EP3SL340H1152C2 FPGA on board. The DE3 board neither contains built-in
ADCs nor an RS232 serial interface, but it offers the possibility to expand the system via
eight High-Speed Terasic Connector (HSTC) and two 40-pin headers for General Purpose
Input/Output (GPIO). The top four HSTCs can be used to connect daughter-board cards
while the bottom four can be used to integrate multiple DE3 boards together. Another
distinct feature of the DE3 board, as compared to the previously utilized DE2, is that it
has a 50 MHz built-in crystal oscillator (instead of 100 MHz).
In order to achieve eight parallel channels, the phasemeter system was designed with one
DE3 mother board and four Terasic AD/DA Data Conversion Cards. Each conversion
card contain two 14-bit ADC, and two 14-bit Digital-to-analog converter (DAC) which can
run up to 150 MSPS and 250 MSPS respectively, and this allowing a total of eight analog
I/O channels. At least one of the DACs would be used for the purpose of generating the
pilot tone. The FPGA hardware implementation was entirely designed with the Quartus
II development software by Altera. The Quartus II software can also be used to synthesize
the digital design and to program the hardware in the FPGA.
29
5.3. HARDWARE IMPLEMENTATION
(a) DE3 Board.
(b) AD/DA Card.
(c) Integrated system.
Figure 5.3.: Terasic development hardware utilized for the phasemeter implementation.
5.3.1. FPGA System Build
Design Top-level
The first step into setting up the phasemeter on the DE3 board is to build the system on
the FPGA. For that, a top-level design entity was created for the purpose of declaring the
signals to be driven to/from the FPGA pins, to control the attached AD/DA Conversion
Cards, to generate a 100 MHz signal from the 50 MHz crystal oscillator, and to instantiate
a phasemeter design instance. In this case the phasemeter design instance is essentially
the FPGA design from the first prototype (coded in VHDL), but with some adaptations.
It is important to note here that a top-level design entity for an FPGA design is arbitrary.
Generally, any FPGA design file can be assigned to be at the top-level. In fact, in the first
prototype, the phasemeter design itself acted as the top-level entity. A higher top-level was
created for the second prototype mainly to separate the complexity of integrating the DE3
board with the external AD/DA Conversion Cards. Also, a higher level was necessary in
order to instantiate an entity which generates a 100 MHz clock from the 50 MHz crystal
oscillator, prior to instantiating the phasemeter design.
Clock Generation
The 100 MHz clock was created by using the Altera Megafunction ATLPLL. Megefunctions are ready-made functions which can be easily parameterized with the Quartus II
Megawizard plug-in manager (a tool provided by the Quartus II software). In this case,
the ATLPLL was configured to multiply the 50 MHz crystal oscillator clock by 2, and thus
generating a 100 MHz clock. In addition, a 100 MHz clock with a 180 degree shift is also
generated. As we will see later, this is necessary for the ADC data acquisition.
It is also possible to trigger the FPGA board with an external clock. In this case of course,
the ATLPLL megafunction has the advantage of allowing for a quick implementation with
30
CHAPTER 5. DEVELOPMENT OF A FPGA-BASED DIGITAL PHASEMETER
the desired clock frequency, without requiring additional hardware.
AD/DA Conversion Card Driver
The ADC data sampling has to be performed according to the timing diagram shown in
Figure 5.4. As observed, a pair of differential LVDS clock with an 180 degree phase shift
is required to drive the sample acquisition. Once a data sample becomes valid, the Data
Output Clock (DCO) signals the FPGA for acquisition.
N+2
N+1
N+3
N
N+4
tA
N+8
N+5
N+6
N+7
N–7
N–6
tCLK
CLK+
CLK–
tPD
DATA
N – 13
tS
DCO
N – 12
N – 11
tH
N – 10
N–9
tDCO
N–8
N–5
N–4
tCLK

Figure 5.4.: Data acquisition timing diagram for the AD9254 [3].
In order to perform the data sampling and ADC channel configuration, a design entity
entitled DCC_DRIV ER was introduced. The entity was designed in block symbol file
(.bsf), and the full design is given in the appendix.
Extension of Channels
The extension of channels on the FPGA was done by simply replicating the DPLLs which
were designed for the first prototype. Since each channel require its own DPLL, then
it follows that 8 DPLLs are required. When performing the pilot tone calibration, an
additional DPLL is required for each channel in order to detect the pilot tone. In this case,
a total of 16 DPLLs are required. Essentially the same DPLL design can also be used for
the pilot tone detection, but the center frequency should correspond to the frequency of
the generated pilot tone.
Pilot Tone Generation
The pilot tone can be generated by implementing a Direct Digital Synthesizer (DDS) with
the FPGA board. A DDS is essentially composed by a NCO, a DAC and a reference oscillator (or clock signal). In this case the reference oscillator can be either 50 MHz crystal
oscillator on board, or it can be a higher frequency clock generated with the ATLPLL
5.3. HARDWARE IMPLEMENTATION
31
function. Alternatively, it can also be driven by an external clock. For an easy implementation, the pilot tone was chosen to be implemented with a simple NCO composed of phase
accumulator and a LUT (shared with the DPLLs). The output of the LUT is then driven
to a DAC, which generates the analog sine wave. The block diagram of the implemented
DDS is shown in Figure 5.5.
Figure 5.5.: Block diagram of Direct Digital Synthesizer (DDS).
Additional Features
Once the entire design was complete, a SignalTap II Logic Analyzer (also a tool provided
with Quartus II) file was created for real time inspection if the FPGA hardware. This
allows for the inspection of any register inside the digital FPGA design to be tapped and
acquired according to the desired data format.
Another feature introduced was the use of the LED displays to indicate whenever the ADC
channels are out-of-range. This is a simple and important feature which useful not only for
protecting the ADCs from excessive voltage levels, but also to offer a quick visual indication
in case an ADC chip becomes damaged. It also indicates whenever "clipping" of the input
signals occurs. This occurs when the voltage level slightly exceed the ADC limits. It may
not necessarily damage the chip, but it is undesired during phase measurements.
Additionally, a CLOCK_IN and CLOCK_OU T signal where also introduced. These
can be useful for driving the phasemeter with an external clock (i.e. an USO), or to
synchronize the phasemeter with external devices.
5.3.2. RS232 Interface Card
For the data transfer from the FPGA board to a computer, a RS232 interface is required.
This could also be done with one of the built-in USB interfaces, but it was decided to maintain the data transfer via RS232 in order to preserve the communications protocol (which
had been previously implemented). However, since the Terasic DE3 FPGA development
board does not have a built-in RS232 interface, it was necessary to design and fabricate an
external RS232 interface card which could be connected via the GPIO pins on the FPGA
board.
32
CHAPTER 5. DEVELOPMENT OF A FPGA-BASED DIGITAL PHASEMETER
5.3.3. System Housing
Once the FPGA design was complete, and all the necessary hardware was acquired, the
phasemeter was packaged. The full phasemeter system can be seen in Figures 5.6 and 5.7.
Figure 5.6.: Phasemeter Hardware.
Figure 5.7.: Phasemeter (top view).
The front and back panels of the phasemeter are shown in Figures 5.8 and 5.9. The front
panel contains eight SMA connectors for the eight ADC channels, and six spare connectors
for general purpose (i.e. clock input/output). The back panel contains the RS232 connector
for data transfer and a USB connector to program the FPGA. It also houses a fan to cool
the FPGA board and AD/DA conversion cards.
Figure 5.8.: Phasemeter (front panel).
Figure 5.9.: Phasemeter (back panel).
6. Pilot Tone Calibration for ADC Jitter
Corrections
In parallel with the phasemeter hardware design, investigations were done towards the
implementation of the pilot tone calibration scheme. In this chapter, the effects of ADC
jitter on phase measurements are described, and a method for phase corrections is proposed.
To perform the proposed phase corrections, it was determined that a pilot tone board would
be necessary in order to inject a pilot tone simultaneously into 8 parallel channels. The
design and fabrication of the pilot tone board is also described in this chapter.
6.1. Description
ADC jitter arises form the uncertainty in the aperture latency during the encoding process
of each sample. Consequently, the ADC sampling intervals are irregular, and this leads to
undesired artifacts in the phase measurements. It can be characterized by a quantity known
as aperture uncertainty, τa . The values for aperture uncertainty are generally provided by
the ADC manufacturer in units of RMS.
The effects of ADC jitter are shown in (Figure 6.1). As observed, the actual sampling
intervals will deviate from the ideal sampling interval, ∆T , which is determined by the
clock frequency, fclk . Assuming only the effects of ADC jitter are present, then the amount
of deviation will depend on the random value τa at each sampling point.
The effects of ADC jitter can also be mathematically described as follows:
For a given heterodyne signal Sh with frequency fh , at the input of the ADC channel, the
change in phase over a sampling interval ∆T is given by
∆φh = fh · ∆T.
(6.1)
However, due to an aperture uncertainty τa , the change in phase sampled by the ADC
channel would be
∆φs = fh · (∆T + τa ) .
(6.2)
33
34 CHAPTER 6. PILOT TONE CALIBRATION FOR ADC JITTER CORRECTIONS
Ideal
Actual
τa
fclk
ΔT
Figure 6.1.: The effects of ADC jitter in the sampling process.
The phase noise introduced by ADC jitter can then be expressed as
δφjitter = fh · τa .
(6.3)
For the LISA phasemeter, the measurement of interest is the phase difference between
two heterodyne signals. In this case, for the given heterodyne signals Sh1 and Sh2 with
frequencies fh1 and fh2 , the sampled phase run for both cases would be
∆φs1 = fh1 · ∆T + fh1 · τa1 ,
(6.4)
∆φs2 = fh2 · ∆T + fh2 · τa2 .
(6.5)
and
Thus, the phase run difference would then be given by
∆φs1 − ∆φs2 = (fh1 − fh2 ) · ∆T − fh1 · τa1 − fh2 · τa2 .
(6.6)
Nominally, the frequencies of both heterodyne signals should be equal (differences should
only arise from the path length variations due to an incident gravitational wave). Assuming
fh1 and fh2 are equal, we can then replace both terms with a common frequency value, fh .
In this case, (6.21) can then be rewritten as
35
6.2. PILOT TONE BOARD
∆φs1 − ∆φs2 = fh · (τa1 − τa2 ) .
(6.7)
Ideally, since the frequencies are equal, the measured phase difference should be zero. From
(6.7) however, it can be observed that phase noise residuals due to ADC jitter will remain.
Since the aperture uncertainty τa1 , τa2 are random quantities which vary at every sampling
point, then the phase variation due to jitter is unknown. However, in order eliminate the
phase noise δφjitter , it is necessary to determine the aperture uncertainty at both ADC
channels for every sampling point.
The aperture uncertainty can be determined by injecting a common pilot tone into both
heterodyne signals. Similarly, we can derive the measured phase difference for the pilot
tone as
∆φp1 − ∆φp2 = fp · (τa1 − τa2 ).
(6.8)
We can then solve for the unwanted phase noise residuals due to ADC jitter as
fh · (τa1 − τa2 ) =
fh
· (∆φp1 − ∆φp2 ).
fp
(6.9)
By subtracting this term from the measured phase difference, the phase difference variations
due to jitter is eliminated. Therefore, the phase difference can be determined from
∆φh1 − ∆φh2 = ∆φs1 − ∆φs2 −
fh
· (∆φp1 − ∆φp2 ).
fp
(6.10)
6.2. Pilot Tone Board
In order to perform the proposed pilot tone calibration scheme, it is necessary to inject a
common pilot tone into each of the eight parallel channels. It is important however that,
when performing the analog summation, the integrity of the signals is preserved and no
additional phase noise is introduced. At the very least, any additional phase noise should
not exceed the jitter noise level and/or should not be present in the frequency band of
interest. Furthermore, it also preferable to have the pilot tone generated by the FPGA
board itself. In this way, the phasemeter may act as a stand-alone device and not depend
on additional inputs other than the heterodyne signals. For this purpose, the pilot tone
can be generated by the FPGA board trough the DAC outputs.
36 CHAPTER 6. PILOT TONE CALIBRATION FOR ADC JITTER CORRECTIONS
6.2.1. Symmetric Design
A simple approach would be to implement the pilot tone injection board with a symmetric
8-way resistive power splitter cascaded with 2-way resistive combiners, all matched to 50
Ω. The 8-way splitter would equally split the pilot tone (generated by a DAC) into 8
parallel signals, and the 2-way combiners would perform the analog summation with the
heterodyne signals (detected by QPDs). Each summation would then be directly driven
into each of the 8 parallel ADCs on the FPGA board. The use of resistors only to perform
the power split and summation is optimal in order to preserve the phase integrity since
they are "ultra" wideband passive devices. Impedance matching to 50 Ω is also desired
since the I/Os at the SMA connectors of the FPGA board are matched to that impedance.
Matched impedance allow for maximum power transfer, and minimum signal reflections
which can cause undesired standing waves.
A symmetric 2-way resistive splitter is shown in Figure 6.2.
R
Zin
R
ZL
Zin
ZL
R
Zin
ZL
Figure 6.2.: A 2-Way resistive splitter.
In order to have every port matched, the load impedance ZL must equal the impedance
looking into the the ports, Zin . The resistors R should then be calculated by solving
Zin = R + (R + ZL ) k (R + ZL ),
(6.11)
for Zin = ZL . Given that the load impedance is 50 Ω, then (6.11) becomes
R + (R + 50) k (R + 50) = 50.
(6.12)
Similarly, a general solution of R for a matched N-way resistive power splitter/combiners
can be derived as
R = ZL
(N − 1)
,
(N + 1)
(6.13)
37
6.2. PILOT TONE BOARD
where N is the the number of ports.
By solving (6.13), we can find the resistor values for both the 2-way combiner and 8-way
splitter as 16.67 Ω and 38.89 Ω, respectively. The circuit could then be implemented as
presented in Figure 6.3.
16
39
16
Zin Zin
39
QPD
Zin
50
16
ADC
39
Zin
50
39
39
DAC
50
Zin
39
39
39
39
Figure 6.3.: Circuit diagram for a pilot tone board designed with a symmetric 8-way resistive splitter cascaded with a symmetric 2-way resistive combiner.
As result, in this case, every port in the circuit will also be symmetrically coupled. However,
this is neither necessary nor desired. We are only interested in driving the sum of the
heterodyne signal from the QPD with the pilot tone (generated by the DAC) into the
ADC channels, and not any other way around. In fact, the reverse coupling between
adjacent channels could lead to intolerable effects, since the heterodyne signals at each
channel would appear at every other ADC channel. In this respect, the design can be
improved by increasing the reserve isolation.
6.2.2. Asymmetric Design
The reverse isolation can be increased with an asymmetric circuit design (Figure 6.4). This
circuit can also be seen as a hybrid of a 8-way splitter combined with a 2-way combiner.
38 CHAPTER 6. PILOT TONE CALIBRATION FOR ADC JITTER CORRECTIONS
Rb
Zin
Ra
ZL
Rb
Zin
ZL
ZL
Zin
Zeq
Rb
Zin
Ra
ZL
Rb
Zin
ZL
Figure 6.4.: Hybrid design of an asymmetric N-way resistive splitter combined with an
asymmetric 2-way resistive combiner.
In this case the solution for the resistance values are calculated by solving the following
system of equations:



Rb + (ZL + Ra ) k (ZL + Ra ) = N · ZL
(1)


Ra + (Ra + ZL ) k (Rb + ZL k Zeq ) = ZL .
(2)
(6.14)
For a 8-way circuit design with 50 Ω loads, we can re-write the system of equations (6.14)
as







Rb + (50 + Ra ) k (50 + Ra ) = 400
(1)
(6.15)
Ra + (Ra + 50) k Rb + 50 k
400
7
= 50.
(2)
In reduced form, these equations become





2Rb + Ra − 750 = 0
(1)
(6.16)
2
Ra + (2Rb + 53.34) Ra − 2500 = 0.
(2)
39
6.2. PILOT TONE BOARD
By solving this system of equations, Ra and Rb can be found as 3.1 Ω and 374 Ω, respectively.
The isolation between channels can be even further increased by terminating one of the
2-way branches with a 50 Ω load, and cascading the other branch with another asymmetric
2-way combiner. An asymmetric 2-way combiner, which can provide a high ratio of isolation
between channels, is shown in Figure 6.5.
Ra
PORT 2
ZL
Zin
Rb
PORT 1
Zin
ZL
Ra
PORT 3
ZL
Zin
Rb
Figure 6.5.: Asymmetric 2-way resistive splitter/combiner.
In this case, assuming ZL = 50 Ω, then following system of equation have to be solved:



(Ra + Rb k 50) k (Ra + Rb k 50) = 50


Rb k [Ra + 50 k (Ra + Rb k 50)] = 50.
(1)
(6.17)
(2)
The values for Ra and Rb can then be found as 68 Ω and 100 Ω, respectively.
The asymmetric design of the pilot tone board is presented in Figure 6.6.
6.2.3. Power Loss
One problem with purely resistive splitters is that power losses can be rather high. Since
the output of the DACs are limited to 0.5 Vpp , with the inflicted power losses, it can be
determined that the pilot tone amplitude delivered to the ADCs would be considerably
low. With a 50 Ω load, the DAC output would be 5 mW, or roughly 7 dBm. In order to
determine the power levels arriving at the ADCs, it is necessary to look at the power loss
between the DAC and ADC ports. These values are presented in Table 6.1.
Therefore, the symmetric and asymmetric designs require a gain in the order of 24 dB and
34 dB, respectively. This issue can be resolved by introducing an amplifier in the path from
the DAC to the ADC channels. Even though a design with passive components only is
preferred, an amplifier prior to the signal split may be tolerated. Most important is to have
40 CHAPTER 6. PILOT TONE CALIBRATION FOR ADC JITTER CORRECTIONS
68
QPD
Zin
50
100
ADC
Zin
50
68
3
Zin Zin
100
374
3
Zin
50
DAC
50
Zin
Zeq
3
Zin
374
3
Zin
50
Figure 6.6.: Circuit diagram for a pilot tone board designed with an asymmetric 8-way
resistive splitter cascaded with an asymmetric 2-way resistive combiner.
Table 6.1.: Power loss between the DAC and ADC ports of the proposed pilot tone board
designs
Stage
Power Loss (dB)
Symmetric Asymmetric
8-way splitter
18
24
2-way combiner
6
10
Total
24
34
eight equal signals arriving at each parallel ADC input. In this way, any potential noise
introduced by additional devices, such as a pre-amplifier, can be canceled by common-mode
rejection.
6.2.4. Isolation
A comparison of the isolation between adjacent channels for both design is provided with
Table 6.2. The isolation values are given only for the path between a QP Dn port and a
adjacent ADCm channel. The other paths are not of importance for this design. In this
case, the asymmetric design has a clear advantage as it provides an isolation over 3 times
41
6.2. PILOT TONE BOARD
greater than the symmetric design.
Table 6.2.: Comparison of the isolation between adjacent channels for was of the proposed
design (symmetric and asymmetric)
Stage
Isolation (dB)
Symmetric Asymmetric
8-way splitter
-18
-48
2-way combiner
-6
-19
Total
-24
-77
In order to determine whether these designs are suitable, it is necessary to calculate the
required reverse isolation. This can be done by performing a phasor analysis.
Assume a signal nominal signal S (with amplitude a and frequency ωn ) is summed with a
noise signal Sn (with amplitude an and frequency ωn ), both given in phasor notation as
S = aej(ωt+ϕ)
(6.18)
Sn = an ej(ωn t+ϕn ) ,
(6.19)
and
where a, ω, ϕ and an , ωn , ϕn are the amplitude, angular frequency and phase of the nominal
and noise phasors, respectively. The phasor representation of these signals are shown in
Figure 6.7.
Im
sn
s'
δφ
s
Re
Figure 6.7.: Phasor representation of phase noise introduced by cross-talk from adjacent
channels.
The net vector S 0 can be written as
42 CHAPTER 6. PILOT TONE CALIBRATION FOR ADC JITTER CORRECTIONS
"
#
"
#
cos(ωt + ϕ)
cos(ωn t + ϕn )
S =a
+ an
.
sin(ωt + ϕ)
sin(ωn t + ϕn )
0
(6.20)
Assuming only ϕn varies with time then we should find the phase error, δϕ, introduced by
a cross-talk noise with magnitude an . In this case, the phase error can then be calculated
as
a · sin ϕ + an · sin ϕn
δϕ = arctan
a · cos ϕ + an · cos ϕn
!
!
a · sin ϕ
− arctan
.
a · cos ϕ
(6.21)
Using the trigonometric identity
!
α−β
arctan α − arctan β = arctan
,
1 + αβ
(6.22)
Equation 6.21 then becomes
"
#
sin(ϕn − ϕ)
δϕ = arctan a
.
+ cos(ϕn − ϕ)
an
(6.23)
Clearly, the maximum phase deviation occurs when the noise signal is at a 90 offset w.r.t
to the nominal signal. In this worst case scenario, the phase error can be simply calculated
as
an
δϕ = arctan
.
a
(6.24)
µrad
In order to fulfill the LISA requirements, this phase error should be less than 2π √
.
Hz
Therefore, it should hold that
an
< 10−6 .
a
(6.25)
In units of decibel, this relation becomes
20 · log
an
< −120dB.
a
(6.26)
Therefore, the reverse isolation between adjacent channels should be in the order of less
than -120 dB. To achieve this level of reverse isolation, it would be necessary to introduce
a high isolation device at each branch of the 8-way power splitter. It would be preferable
to maintain the signal split as clean as possible, but the effects of cross-talk would likely
be even worse. Therefore, a high isolation device has to be carefully chosen.
43
6.2. PILOT TONE BOARD
6.2.5. Wideband Amplifiers
In order to further increase the reverse isolation and perform the required amplification,
wideband amplifiers can be used at each branch of the 8-way splitter. Wideband amplifiers
have phase response which remain at unity over large frequency ranges, and therefore it
is the optimal type of amplifier for this implementation. Furthermore, there are wideband
RF amplifiers available which are already internally matched to 50 Ω, and thus eliminating
the need for matching networks. Matching networks would also be undesired since they
are very frequency dependent, or in other words, narrowband.
By implementing a wideband amplifier at each branch, it is necessary to calculate the power
loss according to the gain provided in the path between the DAC output to each ADC
channel (Figure 6.8). Recall that this path defines the power loss of the pilot tone. The
8-way splitter and 2-way combiner stages can be implemented with either the symmetric
or asymmetric design.
Symmetric
PL=18 dB
PL= 6 dB
DAC
ADCn
8-Way
G
2-Way
Asymmetric
PL=24 dB
PL=10 dB
DAC
ADCn
8-Way
G
2-Way
Figure 6.8.: Pilot tone power loss path (DAC → ADC).
Similarly, the isolation between a QPD input port n and an adjacent ADC channel m also
has to be calculated according to the wideband amplifiers to be implemented. In this case,
the amplifier would provide a reserve isolation (I) from the 2-way combiner to the 8-way
splitter. The wideband amplifier of an adjacent branch would then adversely provide a gain
in the forward direction into the 2-way combiner at an adjacent ADC channel (Figure 6.9).
Therefore, in order to achieve the required isolation of -120 dB the wideband amplifier,
would require a net isolation (I+G) in the order of -96 dB and -43 dB for the symmetric
and asymmetric design, respectively.
One alternative which could fulfill the requirements would be the HMC460LC5 wideband
44 CHAPTER 6. PILOT TONE CALIBRATION FOR ADC JITTER CORRECTIONS
Symmetric
I = 6 dB
I = 18 dB
I = 6 dB
QPDn
ADCm
2-Way
I
8-Way
G
2-Way
Asymmetric
I = 19 dB
I = 48 dB
I = 10 dB
QPDn
ADCm
2-Way
I
8-Way
G
2-Way
Figure 6.9.: Adjacent channel isolation path (QP Dn → ADCm ).
amplifiers from Hittite Microwave. These amplifiers are internally matched to 50 Ω and
they can provide 14 dB of gain and up to 60-70 dB of isolation at frequencies down to
DC. Therefore, the requirements could be fulfilled by implementing the pilot tone board
(asymmetric design) with a pre-amplifier before the power split and 8 HMC460LC5 at
each branch of the 8-way splitter. In addition, the HMC920LP5 active bias controller can
be used for power management. The HMC920LP5 can perform the power-up sequence
and stabilize the amplifier gain. Both the HMC460LC5 and HMC920LP5 are shown in
Figures 6.10 and 6.11. Although these devices seem promising for the pilot tone board
implementation, a design with them would be relatively complex and expensive. Also,
their packaging are rather difficult to deal with manually.
Figure 6.10.: HMC460LC5 wideband amplifier from Hittite Microwave [13]
Figure 6.11.: HMC920LC5 active bias controller from Hittite Microwave
[14]
For a simpler and more practical approach, a selection of wideband RF amplifiers from
NXP Semiconductors was chosen for the first pilot tone board implementation 6.12.
The selected models for implementation are presented in Tables 6.3 and 6.4.
6.2. PILOT TONE BOARD
45
Figure 6.12.: Wideband amplifier (SOT363 Package) from NXP Semiconductors [20].
Table 6.3.: Amplifier selection for the assymetric pilot tone board design.
Model
Vs (V) Pin (dBm) P1dB (dBm) Psat (dBm) S12 (dB) S21 (dB) VADC (mVpp )
BGA2771
3
-7.9
12.1
13.2
20
-30
225
BGA2716
5
-14
8
12.5
11.6
-31
280
BGA2776
5
-14.8
7.2
10.5
22
-27
250
Table 6.4.: Amplifier selection for the assymetric pilot tone board design.
Model
Vs (V) Pin (dBm) P1dB (dBm) Psat (dBm) S12 (dB) S21 (dB) VADC (mVpp )
BGM1013
5
-23
12
13
35
-33
445
5
-19.5
10.5
12.5
30
-31
375
BGM1014
Although these devices would not fully fulfill the net isolation requirements with a single
stage, they could still be used to verify the pilot tone board design concept. Up to this stage
of design, it was still unclear whether the wideband amplifiers could defeat the purpose of
the pilot tone calibration by introducing even more phase noise. Therefore, it was decided
to proceed with an experimental approach and inspect the actual phase response of the
complete circuit upon fabrication. Of course, in this case, the simpler approach is preferred
for a quicker implementation. It was then also decided to proceed with the implementation
of both pilot tone board designs (symmetric and asymmetric). This would allow for a more
thorough investigation and characterization of the pilot tone board by using a wider variety
of wideband amplifiers.
6.2.6. Voltage Regulation
In order to supply the amplifiers, a linear voltage regulator should be utilized. Linear
regulators are preferable over switch regulator, because the switching can cause ringing
which may degrade the response of the amplifier. The regulators can be chosen from the
uA78M00 Series of Texas Instruments [26]. The available regulators in this series can
46 CHAPTER 6. PILOT TONE CALIBRATION FOR ADC JITTER CORRECTIONS
regulate a wide range of input voltages down to a fixed 3 V or 5 V which are required by
the selected amplifiers.
6.2.7. Anti-aliasing Filter
Since the pilot tone is to be generated by a DAC, then the pilot tone board should also
include an anti-aliasing filter to eliminate quantization effects. The frequency of the pilot
tone could likely be up to 100 MHz, but should not exceed this value (very high frequencies
may be problematic for both the phasemeter and pilot tone board design). Therefore, a
cutoff frequency of 80 MHz was chosen from the LFCN Ceramic Low Pass Filter series
from Mini-Circuits [18].
6.2.8. PCB Implementation
A block diagram of the final pilot tone board design is shown in Figure 6.13. The final
design includes a LPF at the DAC port, an 8-way splitter, 8 wideband amplifiers and 2way combiners. Either the symmetric or asymmetric design can be used according to the
amplifier model to be used. It is necessary to ensure that the power level requirements are
met.
Pilot Tone Board
8-Way Splitter
2-Way Combiners
QPD1
ADC1
QPD2
ADC2
QPD3
ADC3
QPD4
ADC4
DAC
LPF
QPD5
ADC5
QPD6
ADC6
QPD7
ADC7
QPD8
ADC8
Figure 6.13.: Block diagram of the final pilot tone board design.
6.2. PILOT TONE BOARD
47
Circuit Schematic
The circuit schematics were designed with Eagle Layout Editor. Eagle has a large components library which already contains most of the devices requires for this design. The circuit
schematic for the LPF and 8-way splitter for both symmetric and asymmetric designs are
shown in Figures 6.14 and 6.15.
Figure 6.14.: Circuit schematic: LPF and 8-way splitter (symmetric design).
Figure 6.15.: Circuit schematic: LPF and 8-way splitter (Asymmetric design).
The circuit schematics for the wideband amplifiers (w/biasing circuitry) and 2-way combiners (symmetric and asymmetric) are shown in Figures 6.16 and 6.17. One major advantage
of this design is that the same biasing circuitry can be used for all of the selected amplifier
48 CHAPTER 6. PILOT TONE CALIBRATION FOR ADC JITTER CORRECTIONS
models. Hence, no change is the design layout is necessary when implementing differente
models.
Figure 6.16.: Circuit schematic: Wideband amplifier (w/ biasing circuitry) and 2-way combiner (Symmetric design).
Figure 6.17.: Circuit schematic: Wideband amplifier (w/ biasing circuitry) and 2-way combiner (Asymmetric design).
Figure 6.18 shows the schematic for the linear voltage regulator. The same circuitry can
be used for bot the 3 V and 5 V fixed output regulator. The output level should be chosen
according to the voltage supply required by the selected amplifier model.
Figure 6.18.: Circuit schematic: Linear voltage regulator.
49
6.2. PILOT TONE BOARD
PCB Layout
The following guideline was decided for the Printed Circuit Board (PCB) layout design:
• Equal trace lengths from DAC port to each ADC channel
• 4-layer PCB design to reduce coupling between traces
• Preference for SMD components in order to reduce parasitics
• 50 Ω impedance matching at every channel
• No special RF layout design since frequencies are lower than 100 MHz and the dimensions of the board is small relative to λ/20
The completed PCB layout for both the symmetric and asymmetric designs are shown in
Figures 6.19 and 6.20, respectively.
Figure 6.19.: Pilot tone board layout (Symmetric design)
Figure 6.20.: Pilot tone board layout (Asymmetric design)
50 CHAPTER 6. PILOT TONE CALIBRATION FOR ADC JITTER CORRECTIONS
PCB Fabrication
Upon completion of the design, the PCB layout was delivered for fabrication. The electronic components were individually ordered, and the board was then assembled. The first
fabricated version consisted of the asymmetric design with BGM1014 amplifiers. The top
and bottom sides of the fabricated board is shown in Figures 6.21 and 6.22.
Figure 6.21.: Pilot tone board (top side).
Figure 6.22.: Pilot tone board (bottom side).
The installation of the pilot tone board with the phasemeter hardware is shown in Figure
6.23.For enhanced visualization, this setup is shown with only 4 channels connected.
Figure 6.23.: Close-up view of the 4 AD/DA conversion cards and the pilot tone board.
7. Analysis and Results
Once the hardware was completed, the phasemeter was ready for evaluation. The evaluation was performed by assessing the performance of the phasemeter and comparing it with
the first prototype. An investigation was also performed to determine the dependency of
the phasemeter in respect to the frequency and amplitude of the input signals.
Following this primary evaluation, an investigation towards the pilot tone calibration
scheme was commenced. Although the pilot tone board was already fabricated, it was
not yet ready for full integration with the system. Before doing so, it is necessary to first
inspect the pilot tone generation and detection by the FPGA hardware. Nevertheless, it
was already possible to verify the pilot tone calibration principles by generating the pilot
tone by other means aside from the FPGA hardware and pilot tone board.
7.1. Phasemeter Evaluation
The phasemeter evaluation was performed with an experimental setup which was mainly
composed by a function generator, an 8-way power splitter, and an anti-aliasing filter. The
function generator was used to emulate the science signal in the range of 2 to 20 MHz,
and the power splitter would equally split the signal into the 8 parallel channels. An antialiasing filter was also used to eliminate undesired aliasing effects which could corrupt the
phase measurements. These measurements were also performed overnight for a continuous
period of approximately 16 hours. This is necessary in order to observe the PSD in the
mHz range.
7.1.1. Performance
For the initial evaluation of performance, the function generator was configured to generate
a 5 MHz sine wave with amplitude which would deliver 0.45 Vpp (90% of the dynamic
range of the ADCs) to each ADC input. In order to properly configure the amplitude, it is
necessary to take into account the losses inflicted by the cables, connectors, type of power
splitter, and front-end circuitry of the ADC channels.
51
52
CHAPTER 7. ANALYSIS AND RESULTS
DPLL Frequency Readout
For a first insight, we first look at the input frequencies measured by the DPLLs at channels
1 and 2 (Figure 7.1). For a better visualization, the display of the measured frequencies is
centered at 5 MHz, so that the display actually gives the deviations from the ideal value.
From this plot it can be observed that the frequencies measured at both channels are
highly correlated. The non-idealities in this case can be mainly attributed to imperfections
in the signal provided by the function generator, and by other noise sources which would be
common to both channels (i.e. clock noise and voltage noise). We can also clearly observed
long-term variations which are caused by frequency drifts from the function generator
signal. These frequency drifts are in the order of 1µHz. When taking the frequency
difference, most of the common-mode noise sources are eliminated, but we can see that
other noise sources (i.e. ADC jitter) remains. It is also possible to observe an offset of
approximately 3.7 nHz.
DPLL Frequencies, Channels 1-2, (5 MHz, 0.45 Vpp)
-6
1
x 10
f1
f2
f (Hz)
0.5
0
-0.5
-1
0
0.5
1.5
2
2.5
3
3.5
4
4.5
t (s)
Frequency Difference, Channels 1-2, (5 MHz, 0.45 Vpp)
-8
3
1
x 10
5
4
x 10
f1- f2
f (Hz)
2
1
0
-1
0
0.5
1
1.5
2
2.5
t (s)
3
3.5
4
4.5
5
4
x 10
Figure 7.1.: DPLL frequencies measured by channels 1-2 (Top) and the calculated frequency difference between channels 1-2 (Bottom). As observed in the top
figure, the measured frequency at channel 1, shown in blue, seems to precisely
match that of channel 2, shown in green. That would be the ideal case. However, as observed in the bottom figure, there is residual time-dependent noise
present in the calculated frequency difference.
DPLL Phase Readout
The phases measured by the DPLLs at channels 1 and 2, and the difference between
them are shown in Figure 7.2. Similarly, the measured phases at both channels are highly
correlated. When taking the phase difference we can then observe an offset plus some
varying residuals. In this case the phase offset is of a approximately 3.2 mrad.
53
7.1. PHASEMETER EVALUATION
DPLL Phases, Channels 1-2, (5 MHz, 0.45 Vpp)
12
2
x 10
φ (rad)
1.5
1
φ
1
0.5
φ
2
0
0
0.5
φ (rad)
1.5
2
2.5
t (s)
3
3.5
4
4.5
5
4
x 10
Phase Difference, Channels 1-2, (5 MHz, 0.45 Vpp)
-3
-3.1
1
x 10
-3.2
-3.3
φ1- φ2
-3.4
0
0.5
1
1.5
2
2.5
t (s)
3
3.5
4
4.5
5
4
x 10
Figure 7.2.: DPLL phases measured by channels 1-2 (Top) and the calculated phase difference between channels 1-2 (Bottom). As observed in the top figure, the
measured phase at channel 1, shown in blue, also seems to precisely match
that of channel 2, shown in green. Similarly, as in the frequency readout
case, there is residual time-dependent noise present in the calculated phase
difference. This is expected since the phase was obtained by integrating the
frequency measurements over time.
To assess the phasemeter however, it is more interesting to have any offset or trend removed,
since these can be easily dealt with by proper signal processing. The detrended phase
difference is shown in Figure 7.3. By detrending the data, it becomes easier to recognize
that the varying residuals have a magnitude in the order of approximately 10 µrad.
2
x 10
Detrended Phase Difference, Channels 1-2, (5 MHz, 0.45 Vpp)
-5
φ1- φ2
1.5
1
φ (rad)
0.5
0
-0.5
-1
-1.5
-2
0
0.5
1
1.5
2
2.5
t (s)
3
3.5
4
Figure 7.3.: Detrended phase difference.
4.5
5
x 10
4
54
CHAPTER 7. ANALYSIS AND RESULTS
Similarly, we can also look at the phase difference between other parallel channels. With
8 parallel channels running, the phasemeter will detect 8 frequency and 8 phase values for
each respective channel. The actual input signals would come from a pair of laser beams
detected by a pair of QPDs, and hence 1 frequency and 1 phase value are required per
quadrant (Chapter 3). Since the wavefront of the laser beam has to be spatially resolved,
it is necessary to measure the phase difference between every pair-wise combination of
channels. Therefore, on the processor environment (in this case a PC running Matlab),
28 phase differences should be processed. However, in order to reduce the amount of data
to be processed and displayed in this report, the phase differences were taken pair-wise
between channels 1-2, 3-4, 5-6 and 7-8 (Figure 7.4).
Channels 1-2
φ (rad)
-5
2
x 10
0
-2
0
0.5
1
1.5
2
φ (rad)
x 10
2
0
-2
0
0.5
1
1.5
2
0.5
1
1.5
2
φ (rad)
φ (rad)
3.5
4
4.5
2.5
2.5
x 10
5
4
x 10
3
3.5
4
4.5
5
4
x 10
3
3.5
4
4.5
t (s)
Channels 7-8
-5
2
3
t (s)
Channels 5-6
-5
x 10
2
0
-2
0
2.5
t (s)
Channels 3-4
-5
5
4
x 10
0
-2
0
0.5
1
1.5
2
2.5
t (s)
3
3.5
4
4.5
5
4
x 10
Figure 7.4.: Detected phase differences by 8 parallel channels. Differences are taken pairwise between channels 1-2, 3-4, 5-6 and 7-8.
By observing the measured phase differences in the time domain, we get a good indication
that the performance of the phasemeter is close to the desired µradian precision. However,
is also necessary to observe the frequency domain in order to determine whether the residual
phase noise is within the tolerated limits for the frequency range of interest. To do so, it
is necessary to analyze the PSD of the phase difference. The PSD plots for the pairs of
channels under investigation are shown in Figure 7.5.
From the PSD plots it can be noted that the measured phase differences are also closely
correlated in the frequency domain. Furthermore, it can be clearly observed that with this
experimental setup, the noise in the phase measurements exceed the tolerated levels in the
frequency of from approximately 1 mHz to 20 mHz.
55
7.1. PHASEMETER EVALUATION
10
φ (rad/√Hz)
10
10
10
10
-2
PSD1/2 with ts: 0.083333 s, Win: blackmanharris, Seg: 9 and Ovl: 50 %
Channels 1-2
Channels 3-4
Channels 5-6
Channels 7-8
LISA Requirement
-3
-4
-5
-6
-7
10 -4
10
10
-3
10
-2
10
-1
10
0
10
1
f (Hz)
Figure 7.5.: PSD plot of the detected phase differences (Channels 1-2, 3-4, 5-6 and 7-8).
First vs Second Prototype
The last step in the performance evaluation was to compare the first and second phasemeter
prototypes. This can be done by comparing typical PSD for both prototypes (Figure 7.6).
As expected, the performance of the second prototype is better, since it contains higher
quality ADC chips.
PSD
-2
1/2
with ts: 0.083333 s, Win: blackmanharris, Seg: 9 and Ovl: 50 %
10
First Prototype
Second Prototype
LISA Requirement
-3
φ (rad/√Hz)
10
-4
10
-5
10
-6
10
-7
10 -4
10
-3
10
-2
-1
10
10
0
10
1
10
f (Hz)
Figure 7.6.: Comparison between the first and second phasemeter prototypes.
56
CHAPTER 7. ANALYSIS AND RESULTS
7.1.2. Frequency Dependency
The evaluate the phasemeter in respect to the frequency of the input signal, five sets of
measurements were performed with input frequencies of 2, 5, 10, 25 and 20 MHz. Each
measurement set ran for about 90 minutes. The same experimental setup, as previously
described in this section, was used for this analysis. Only the frequency of the signals
provided by the function generator where changed. The results from this analysis, displayed
in Figure 7.7, indicate that the performance deteriorates as the input frequency increases.
PSD
-4
1/2
with ts: 0.083333 s, Win: blackmanharris, Seg: 9 and Ovl: 50 %
10
2 MHz
5 MHz
10 MHz
15 MHz
20 MHz
-5
φ (rad/√Hz)
10
-6
10
-7
10
-2
10
-1
0
10
10
1
10
f (Hz)
Figure 7.7.: Frequency dependency.
7.1.3. Amplitude Dependency
The phasemeter was also evaluated in respect to the amplitude of the input signal. In
this case, four sets of measurements were performed with amplitudes of 100, 300 400 and
500 mVpp. It can be clearly observed that the performance improves as the amplitude
increases, except when the amplitude is at 500 mVpp. The reason for this is because the
maximum input voltage at the ADC inputs are rated as 512 mVpp. If the amplitude of the
input voltage is too close to the maximum ratings, then small signal fluctuations may cause
clipping. Therefore, it is better to restrict the amplitude of the input signal to roughly
80 − 90% of the maximum ratings, or 400 to 450 mVpp.
7.2. Pilot Tone Calibration
Once the phasemeter was evaluated and verified to be operational, an investigation commenced towards the implementation of the pilot tone calibration scheme. This analysis
57
7.2. PILOT TONE CALIBRATION
PSD
-5
1/2
with ts: 0.083333 s, Win: blackmanharris, Seg: 9 and Ovl: 50 %
10
φ (rad/√Hz)
100 mVpp
300 mVpp
400 mVpp
500 mVpp
-6
10
-7
10 -2
10
-1
0
10
10
1
10
f (Hz)
Figure 7.8.: Amplitude dependency.
was divided into two segments. The first segment was concerned with the generation and
detection of the pilot tone by the FPGA board. The second segment was aimed at verifying
the principles of the pilot tone calibration for ADC jitter corrections.
7.2.1. Pilot Tone Detection
For this analysis, the FPGA board was configured to generate a pilot tone signal via a
DAC output, with a frequency of 4.9805 MHz, and with the maximum achievable output
voltage swing (approximately 0.36 Vpp after losses). An anti-aliasing filter was used at the
DAC output to eliminate digitization effects. The signal was then equally split 2-ways and
sampled at channels 1 and 2 of the phasemeter. The main goal of this analysis segment was
to simply verify the functionality of the pilot tone generation/detection algorithm which
was implemented in the FPGA design. Therefore, the measurements only ran for about
15 minutes.
The detected frequencies and frequency difference of the generated pilot tone is shown in
Figure 7.10. In this case, the detected frequency drifts were in the order of 10 nHz. This
is much lower than drifts experienced by the signals generated by the function generator
which is in the order of 1µHz (see Section 7.1). When taking the frequency difference, we
can observe that the residual variations are also in the order of 10 nHz, and with an offset
of approximately 7.3 nHz.
The detected phases and phase difference of the pilot tone is shown in Figure 7.10. Here it is
also possible to observe clear distinctions when comparing with the signal generated by the
function generator. In this case, the phase difference has characteristics like quantization
effects.
58
CHAPTER 7. ANALYSIS AND RESULTS
DPLL Frequencies, Channels 1-2, (4.9805 MHz, 0.36 Vpp)
-8
1
x 10
f1
f2
f (Hz)
0.5
0
-0.5
-1
0
100
-8
1
x 10
200
300
400
500
600
700
800
t (s)
Frequency Difference, Channels 1-2, (4.9805 MHz, 0.36 Vpp)
f1- f2
f (Hz)
0
-1
-2
-3
0
100
200
300
400
500
600
700
800
t (s)
Figure 7.9.: DPLL frequencies measured by channels 1-2 (Top), and the calculated frequency difference (Bottom) from a pilot tone generated with the FPGA board.
DPLL Phases, Channels 1-2, (4.9805 MHz, 0.36 Vpp)
10
2.5
x 10
φ (rad)
2
1.5
1
φ1
0.5
φ2
0
0
100
300
400
500
600
700
800
t (s)
Phase Difference, Channels 1-2, (4.9805 MHz, 0.36 Vpp)
-3
-1.528
200
x 10
φ (rad)
-1.529
-1.53
-1.531
-1.532
-1.533
0
φ1- φ2
100
200
300
400
500
600
700
800
t (s)
Figure 7.10.: DPLL phases measured by channels 1-2 (Top), and the calculated phase difference (Bottom) from a pilot tone generated with the FPGA board.
These effects can be even more clearly noticed when observing the detrended data (Figure
7.11).
From this analysis, it was possible to verify the FPGA algorithm to generate/detect the
pilot tone. Although the algorithm functioned properly, the generated pilot tone would
not be suitable for the calibration scheme. In order for the calibration scheme to work,
it is necessary for the detected science signal and pilot tone to be correlated. From the
results presented in this section, it can be observed that this is not the case. It could also
be that the pilot tone generation should be modified. A possible alternative is to increase
59
7.2. PILOT TONE CALIBRATION
-7
12
x 10
Detrended Phase Difference, Channels 1-2, (0.49805 MHz, 0.36 Vpp)
φ1- φ2
10
8
6
φ (rad)
4
2
0
-2
-4
-6
-8
0
100
200
300
400
500
600
700
800
t (s)
Figure 7.11.: Detrended phase difference of the detected pilot tone (generated with the
FPGA board).
PSD
-2
1/2
with ts: 0.083333 s, Win: blackmanharris, Seg: 9 and Ovl: 50 %
10
Science Signal (Function Generator)
Pilot Tone (FPGA Board)
LISA Requirement
-3
10
-4
φ (rad/√Hz)
10
-5
10
-6
10
-7
10
-4
10
-3
10
-2
-1
10
10
0
10
1
10
f(Hz)
Figure 7.12.: PSD plot of the detected pilot tone (generated with the FPGA board).
the number of values in the LUT which is used to generate the pilot tone. In this way,
the quantization effects can be reduced, and the pilot tone would then resemble more the
emulated science signals.
On the other hand, it was also possible to observe that under certain conditions (depending on the quality of the detected signal), the phasemeter performance can considerably
increase. However, for the LISA mission, the phasemeter should not be dependent on the
quality of the signal itself, and it shall operate under adverse conditions as well.
60
CHAPTER 7. ANALYSIS AND RESULTS
7.2.2. Phase Corrections
Although the FPGA algorithm and pilot tone board were already implemented and fabricated, they were not yet ready to be fully integrated for the pilot tone calibration. More
investigations are necessary in respect to the pilot tone generated by the FPGA board.
Furthermore, the fabrication of the pilot tone board was only recently completed. Therefore, a battery of testing and verification is still necessary in order to qualify the pilot tone
board.
Nevertheless, the principles of the pilot tone calibration scheme could still be tested by using
a pair of function generator to emulate both the science signal and a nominal pilot tone.
In this case of course, the pilot tone board would be by-passed, and a similar experimental
setup, as presented in the previous section, would be used. As usual an anti-aliasing filter
was used for both signals. A pair of 2-way power splitters/combiners were used to first
add the pilot tone with the science signal, and then to equally split the sum into channels
1 and 2 of the phasemeter.
For this analysis, two sets of measurement were taken. In the first set, the function generators were set to 5 and 5.5 MHz for the nominal pilot tone and science signal, respectively.
In the second set, 2 and 2.5 MHz signals were used. This experimental setup is also useful
for testing the capability of the phasemeter to detect multiple tones.
Each set of measurement ran for a period of about 16 hours. The results are presented in
Figures 7.13 and 7.14. As observed, upon performing the phase corrections, it is possible
to nominally achieve the LISA requirements.
PSD1/2 with t : 0.083333 s, Win: blackmanharris, Seg: 9 and Ovl: 50 %
s
-2
10
Science Signal
Pilot Tone
Corrected
LISA Requirement
-3
10
-4
φ (rad/√Hz)
10
-5
10
-6
10
-7
10
-4
10
-3
10
-2
-1
10
10
0
10
1
10
f (Hz)
Figure 7.13.: Pilot tone corrections. 5 MHz and 5.5 MHz input signals.
Possibly, the performance can still be considerably improved by selecting a more appropriate signal frequency for the pilot tone. In fact, other frequencies should be chosen since the
pilot tone should not be in the same frequency range as the science signals (2-20 MHz). The
61
7.2. PILOT TONE CALIBRATION
PSD
-2
1/2
with ts: 0.083333 s, Win: blackmanharris, Seg: 9 and Ovl: 50 %
10
Science Signal
Pilot Tone
Corrected
LISA Requirement
-3
φ (rad/√Hz)
10
-4
10
-5
10
-6
10
-7
10 -4
10
-3
10
-2
-1
10
10
0
10
1
10
f (Hz)
Figure 7.14.: Pilot tone corrections. 2 MHz and 2.5 MHz input signals.
frequencies used for this evaluation were chosen for practical purposes since the behavior
of the phasemeter was already well understood within the required band. The pilot tone
frequency will likely have to lie above 20 MHz, since in the LISA electronics system, the
low frequency band will be entirely filtered out. Hence, it is likely not possible to have the
pilot tone below 2 MHz. A higher frequency pilot tone however, may be problematic for
the phasemeter since the performance degrades as the frequency increases. One possible
solution for this would be to generate the pilot tone with a few hundreds of kHz above the
sampling frequency of the ADC channels. This would cause the detected pilot tone to be
aliased down to a few hundreds of kHz. In this way, the phasemeter can perform at the
optimal low frequency range.
8. Conclusions
As result of this thesis work, a second prototype for the LISA phasemeter was successfully implemented. This prototype demonstrated a phasemeter with 8 parallel channels
which could be used to measure the phase differences between a pair of QPDs. Under certain conditions, it was also shown that the phasemeter can operate within the stipulated
LISA requirements. In addition to parallel phase measurements, the new prototype implementation also allows for the generation and detection of a pilot tone. However, more
investigation is needed in order to determine the most suitable method to generate the
pilot tone with the phasemeter hardware.
Aside from the phasemeter implementation, a pilot tone board was also designed and
fabricated. The pilot tone board can be used to inject the pilot tone (generated by the
phasemeter hardware) into 8 parallel channels, while providing optimal amplitude levels
and high channel-to-channel isolation. At the current stage of development, the fabrication
process was just completed, and the pilot tone board is now ready for testing and verification. Initial tests should verify the actual isolation between channels, and the phase
response of signals driven though the board. Once the pilot tone board if proven to be
functioning as desired, it can then be fully integrated with the phasemeter hardware.
63
9. Further Work
Following this thesis work, the next step for the further development of this phasemeter
prototype would be to fully characterize the pilot tone board. This should be done by first
evaluating the analog performance of the fabricated board with an oscilloscope, spectrum
analyzer and network analyzer. The oscilloscope can be used for a general evaluation while
the spectrum analyzer can offer a closer look at the spectral character of the phase response
across the pilot tone board. The network analyzer can then be used to assess the coupling
between adjacent channels, to compare then with the designed values.
In parallel, other pilot tone generation methods should also be investigated. This could
include a method in which the number of values in the LUT is increased. Also, a method
to generate a pilot tone with higher frequencies should also be attempted. This could then
allow for the optimal frequency range to be determined.
Upon verification of the pilot tone board and pilot tone generation methods, the phasemeter
system can then be fully integrated. Then a battery of test measurements should be
performed in order to assess the performance even in the most adverse conditions. The
grounds then be prepared for further extension of channels. The next prototype could
perhaps support 16 or 32 channels.
65
Bibliography
[1] A. Einstein. Die grundlage der allgemeinen relativitatstheorie. Annalen Der Physik,
1916.
[2] Altera, 101 Innovation Drive San Jose, CA 95134. Quartus II Handbook, version 10
edition, 2008.
[3] Analog Devices, One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,
U.S.A. AD9254 Datasheet, rev. 0 edition, 2006.
[4] Bernard F. Schutz. A First Course in General Relativity. Cambridge University Press,
Cambridge, UK, 2009.
[5] Bernard F. Schutz. Fundamental physics with lisa. In Classical and Quantum Gravity,
volume 26. IOP Publishing, 2009.
[6] Carl Warren, Dave Wealthy, and Neil Dunbar. Managing disturbance sources on lisa
pathfinder. In 6th International LISA Sysmposium. American Institute of Physics,
2006.
[7] D. Shaddock, B. Ware, P. G. Halverson, R. E. Spero, and B. Klipstein. Overview of
the lisa phasemeter. In 6th International LISA Sysmposium. American Institute of
Physics, 2006.
[8] Daniel Sigg. Gravitational waves. In LIGO. Theoretical Advanced Study Institute in
Elementary Particle Physics, 1998.
[9] Dennis Weise, Claus Braxmeier, Micheal Kersten, Wolfgang Holota, and Ulrich Johann. Optical design of the lisa interferometric metrology system. In 6th International
LISA Sysmposium. American Institute of Physics, 2006.
[10] ESA Science & Technology:
Cosmic
e/www/area/index.cfm?fareaid=100, 2010.
Vision.
http://sci.esa.int/science-
[11] Franziska Kittelmann. Entwicklung eines fpga-basierten ultraprzisen rf-phasemeters.
Technical report, EADS Astrium/Fachhochschule Gelsenkirchen, 2009.
[12] Gerhard Heinzel, Frank Steier, Roland Fleddermann, Benjamin Sheard, and Karsten
Danzmann. Components for the lisa local interferometry. In 6th International LISA
Sysmposium. American Institute of Physics, 2006.
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Bibliography
[13] Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824. HMC460LC5
- GaAs PHEMT MMIC LOW NOISE AMPLIFIER, DC - 20 GHz, v.02 edition, 2008.
[14] Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824. HMC920LP5
- Active Bias Controller, v.02 edition, 2010.
[15] Hume Peabody and Stephen M. Merkowitz. Low frequency thermal performance of
the lisa sciencecraft. In 6th International LISA Sysmposium. American Institute of
Physics, 2006.
[16] LISA Mission Science Office. LISA: Probing the Universe with Gravitational
Waves. National Research Council Beyond Einstein Program Assessment Committee (BEPAC), LISA Mission Science Office, 2009.
[17] M. Sallusti, P. Gath, D. Weise, M. Berger, and H. R. Schulte. Lisa sysmtem design
highlights. In Classical and Quantum Gravity, volume 26. IOP Publishing, 2009.
[18] Mini-Circuits, P.O. Box 350166, Brooklyn, New York. Low Pass Filter LFCN-80+,
2010.
[19] Miroslav Micic, Kelly Holley-Bockelmann, and Steinn Sigurdsson. Lisa observations
of supermassive black hole growth. In 6th International LISA Sysmposium. American
Institute of Physics, 2006.
[20] NXP Semiconductors. RF Manual, 14th edition edition, 2010.
[21] O. Jennrich. Lisa technology and instrumentation. In Classical and Quantum Gravity,
volume 69. IOP Publishing, 2009.
[22] Peter F. Gath, Ulrich Johann, Hans Reiner Schulte, Dennis Weise, and Mark Ayre.
Lisa system design overview. In 6th International LISA Sysmposium. American Institute of Physics, 2006.
[23] R. V. Pound and G. A. Rebka. Apparent weight of photons. Phys. Rev. Lett., 4(7):337–
341, Apr 1960.
[24] Roland Best. Theorie und Anwendungen des Phase-locked Loops. AT Verlag, 1993.
[25] Scott A. Hughes. A brief survey of lisa sources and science. In 6th International LISA
Sysmposium. American Institute of Physics, 2006.
[26] Texas Instruments. uA78M00 SERIES POSITIVE-VOLTAGE REGULATORS, 2010.
[27] Ulrich Johann, Peter F. Gath, Wolfgang Holota, Hans Reiner Schulte, and Dennis
Weise. Novel payload architectures for lisa. In 6th International LISA Sysmposium.
American Institute of Physics, 2006.
[28] Vinzenz Wand, Felipe Guzman, Gerhard Heinzel, and Karsten Danzmann. Lisa
phasemeter development. In 6th International LISA Sysmposium. American Institute
of Physics, 2006.
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[29] Wikipedia The Free Encyclopedia. www.wikipedia.com, 2010.
[30] William Klipstein, Peter G. Halverson, Robert Peters, and Rachel Cruz. Clock noise
removal in lisa. In 6th International LISA Sysmposium. American Institute of Physics,
2006.
A. FPGA Development
A.1. SignalTap II Logic Analyzer
Figure A.1.: Screen shot of the Signal Tap II Logic Analyzer which was used to inspect
the implmentation of the FPGA design. The current screen is displaying the
input signals are 8 parallel ADC channels.
71
72
APPENDIX A. FPGA DEVELOPMENT
A.2. DE3 System Builder
Figure A.2.: Screen shot of the System Builder software tool provided with the Terasic
DE3 development kit. The current screen displays the top-level design configuration of the DE3 Phasemeter.
A.2. DE3 SYSTEM BUILDER
73
Figure A.3.: Second screen shot of the System Builder. This screen displays the necessary
interconnections to integrate the DE3 FPGA motherboard with four AD/DA
conversion cards.
74
APPENDIX A. FPGA DEVELOPMENT
A.3. DCC_Driver
DCC_DRIVER
constants
inputs
clock
clock_n
locked
l
clock
INPUT
VCC
INPUT
VCC
INPUT
VCC
h
VCC
clock_n
locked
GND
clock drivers and lock indicator
clock_n
OUTPUT
pclk0p
OUTPUT
pclk0n
OUTPUT
LED_0
NOT
inst24
locked
NOT
inst26
------------------------------ channel A ------------------------------------analog to digital converter capture and sync
DFF
ada_d[13..0]
ada_dco
INPUT
VCC
INPUT
VCC
DFF
PRN
D
a2d_data_a[13..0]
PRN
Q
clock
D
OUTPUT
Q
h
CLRN
inst31
CLRN
inst32
l
a2d_data_a[13..0]
OUTPUT
ada_spi_cs
OUTPUT
ada_oe
analog to digital converter over run indicator
ada_or
analog_to_digital_over_run_a
INPUT
VCC
NOT
LED_3
OUTPUT
inst29
------------------------------ channel B ------------------------------------analog to digital converter capture and sync
DFF
adb_d[13..0]
adb_dco
INPUT
VCC
INPUT
VCC
DFF
PRN
D
a2d_data_b[13..0]
PRN
Q
clock
D
OUTPUT
Q
l
CLRN
inst33
CLRN
inst34
h
a2d_data_b[13..0]
OUTPUT
adb_oe
OUTPUT
adb_spi_cs
analog to digital converter over run indicator
adb_or
analog_to_digital_over_run_b
INPUT
VCC
NOT
OUTPUT
LED_4
inst30
Figure A.4.: Block symbol file of the DCC_Driver design.
B. PCB Design
B.1. Pilot Tone Board (Symmetric Design)
B.1.1. PCB Layout - Pilot Tone Board (Symmetric Design)
3,2
3,2
R12
C2
R2
C1
U$1
R11
C3 R10
L1
CH1
ADC1
R15
C5
R3
C4
U$2
R14
C6 R13
L2
CH2
ADC2
CH3
R18
C8
R4
C7
U$3
C9 R16
L3
R17
ADC3
CH4
R21
R5
ADC4
ENOT_TOLIP
1
- O
DN G
sV
1R
C26
I
IC1
X1
RETLIF
A15,2mm
C25
C11
C10
U$4
C12R19
L4
R20
CH5
R24
R6
C14
C13
U$5
C15R22
L5
R23
CH6
R27
R7
C17
C16
U$6
C18R25
L6
R26
R30
R8
C20
CH8
R9
C23
C22
U$8
C24R31
L8
ADC7
R33
R32
3,2
ADC6
C19
U$7
C21R28
L7
CH7
R29
ADC5
ADC8
3,2
75
76
Top/Bottom Layers
Ground/Supply Layers
APPENDIX B. PCB DESIGN
D
C
B
1
SMA-142-0701-871/876
PILOT_TONE
C-GRID-02-70543
X1-1
X1-2
1
IN
OUT
2
RFOUT
GND
IC1
5V/3.3V
GND
GNDGND
LFCN-80
RFIN
FILTER
0.33uF
C26
GND
2
A
GND
4
3
0.1uF
C25
39
R1
V+
3
39
R9
39
R8
39
R7
39
R6
39
R5
39
R4
39
R3
39
R2
3
PT8
PT7
PT6
PT5
PT4
PT3
PT2
PT1
10nF
GND
GND
4
5
6
GND1
GND2
4
VS
GND2
RF_IN RF_OUT
4
1
2
3
GND
L1
220nH
GND
C1
22nF
V+
5
C3
5
6
16
16
GND
ADC1
SMA-142-0701-871/876
R12
6
R10
GND
SMA-142-0701-871/876
CH1
R11
2
16
1
D
C
B
A
B.1. PILOT TONE BOARD (SYMMETRIC DESIGN)
77
B.1.2. PCB Schematic - Pilot Tone Board (Symmetric Design)
10nF
C2
78
APPENDIX B. PCB DESIGN
B.2. Pilot Tone Board (Asymmetric Design)
B.2.1. PCB Layout - Pilot Tone Board (Asymmetric Design)
R1
C1
U$1
R13
C2
R11
R14
C3 R12
L1
CH1
ADC1
R10
R2
C4
C5
R19
U$2
R17 R20
C6 R18
L2
R9
CH2
ADC2
R16
R3
C7
C8
R25
U$3
R23 R26
C9 R24
L3
R15
CH3
ADC3
R22
R4
C10
ADC4
ENOT_TOLIP
R28
1
- O
C26
I
IC1
A15,2mm
GND
V+
ADC5
R34
ADC6
R40
R7
C19
R46
R45
C20
R49
U$7
R47
R50
C21R48
L7
R39
CH7
R6
C16
C17
R43
U$6
R41 R44
C18R42
L6
R33
CH6
R5
C13
C14
R37
U$5
R35 R38
C15 R36
L5
CH5
X1
RETLIF
C25
R27
C11
R31
U$4
R29 R32
C12R30
L4
R21
CH4
ADC7
R51
R8
C22
U$8
R55
C23
R53
R56
C24 R54
L8
CH8
R52
ADC8
B.2. PILOT TONE BOARD (ASYMMETRIC DESIGN)
Top/Bottom Layers
Ground/Supply Layers
79
D
C
B
GND
1
SMA-142-0701-871/876
PILOT_TONE
C-GRID-02-70543
X1-1
V+
1
IN
OUT
2
RFOUT
GND
IC1
5V/3.3V
GND
GNDGND
LFCN-80
RFIN
FILTER
0.33uF
C26
3
0.1uF
C25
374
R8
374
R7
374
R6
374
R5
374
R4
374
R3
374
R2
374
R1
VS
PT8
PT7
PT6
PT5
PT4
PT3
PT2
PT1
3
53.1
R9
3
GND
3.1
R10
10nF
GND
GND
4
5
6
4
GND1
GND2
VS
GND2
RF_IN RF_OUT
4
1
2
3
GND
L1
220nH
GND
C1
22nF
Vs
5
C3
5
GND
68
R12
GND
100
GND
R14
SMA-142-0701-871/876
CH1
10nF
X1-2
GND
2
R11
2
R13
A
GND
4
100
6
6
GND
ADC1
SMA-142-0701-871/876
68
1
D
C
B
A
80
APPENDIX B. PCB DESIGN
B.2.2. PCB Schematic - Pilot Tone Board (Asymmetric Design)
C2
B.3. BILL OF MATERIALS (BOM)
B.3. Bill of Materials (BOM)
BOM - Pilot Tone Board (Symmetric Design)
Qty
1
1
1
16
Value
0.1uF
0.33uF
5V/3.3V
10nF
Device
C-EUC0603
C-EUC0603
78XXL
C-EUC0603
Parts
C25
C26
IC1
C2, C3, C5, C6, C8, C9, C11, C12, C14, C15,
C17, C18, C20, C21, C23, C24
24
16
R-EU_R0603
R10, R11, R12, R13, R14, R15, R16, R17, R18,
R19, R20, R21, R22, R23, R24, R25, R26, R27,
R28, R29, R30, R31, R32, R33
8
22nF
C-EUC0603
C1, C4, C7, C10, C13, C16, C19, C22
9
39
R-EU_R0603
R1, R2, R3, R4, R5, R6, R7, R8, R9
8
8
220nH
-
L_L0603
BGA-BGM-XXXX
L1, L2, L3, L4, L5, L6, L7, L8
U$1, U$2, U$3, U$4, U$5, U$6, U$7, U$8
1
-
C-GRID-02-70543 X1
1
4
-
17
-
LFCN-80
MOUNTPADROUND3.2
SMA-142-0701871/876
FILTER
H1, H2, H3, H4
ADC1, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7,
ADC8, CH1, CH2, CH3, CH4, CH5, CH6, CH7,
CH8, PILOT_TONE
BOM - Pilot Tone Board (Asymmetric Design)
Qty
1
1
8
Value
0.1uF
0.33uF
3.1
Device
C-EUC0603
C-EUC0603
R-EU_R0603
Parts
C25
C26
R10, R16, R22, R28, R34, R40, R46, R52
1
16
5V/3.3V
10nF
78XXL
C-EUC0603
IC1
C2, C3, C5, C6, C8, C9, C11, C12, C14, C15,
C17, C18, C20, C21, C23, C24
8
22nF
C-EUC0603
C1, C4, C7, C10, C13, C16, C19, C22
8
53.1
R-EU_R0603
R9, R15, R21, R27, R33, R39, R45, R51
16
68
R-EU_R0603
R12, R13, R18, R19, R24, R25, R30, R31, R36,
R37, R42, R43, R48, R49, R54, R55
16
100
R-EU_R0603
R11, R14, R17, R20, R23, R26, R29, R32, R35,
R38, R41, R44, R47, R50, R53, R56
8
8
220nH
374
L_L0603
R-EU_R0603
L1, L2, L3, L4, L5, L6, L7, L8
R1, R2, R3, R4, R5, R6, R7, R8
8
-
BGA-BGM-XXXX
U$1, U$2, U$3, U$4, U$5, U$6, U$7, U$8
1
-
C-GRID-02-70543 X1
1
4
-
17
-
LFCN-80
MOUNT-PADROUND3.2
SMA-142-0701871/876
FILTER
H1, H2, H3, H4
ADC1, ADC2, ADC3, ADC4, ADC5, ADC6,
ADC7, ADC8, CH1, CH2, CH3, CH4, CH5, CH6,
CH7, CH8, PILOT_TONE
81
82
APPENDIX B. PCB DESIGN
B.4. List of Orders
Pilot Tone Board
Device
PCB SMA Connector
Resistor
Package
Description
SMAEDGE PCB END BLKHD JCK GLD
.062" BOARDS
R0603
16
Resistor
R0603
39
Resistor
R0603
68
Resistor
R0603
100
Resistor
R0603
374
Resistor
R0603
3.6
Resistor
R0603
53.6
Capacitor
C0603
10nF
Capacitor
C0603
22nF
Capcitor
C0603
0.1uF
Capcitor
C0603
0.33uF
Inductor
L0603
220nH
Linear Voltage Regulator
TO220
3.3V
Linear Voltage Regulator
TO220
5V
Wideband Amplifier
SOT363
50 Ohm Matched
Wideband Amplifier
SOT363
50 Ohm Matched
Wideband Amplifier
SOT363
50 Ohm Matched
Wideband Amplifier
SOT363
50 Ohm Matched
Wideband Amplifier
SOT363
50 Ohm Matched
Low Pass Filter
FV1206
80 MHz
RS232 Interface Card
Device
Level Converter
Package
PDIP-16
Description
MAX3232
F09
90 Degrees PCB Mount
Other Components
Device
SMA Cable
Package
Coaxial
Description
30 cm
SMA Cable
Coaxial
50cm
Power Spliiter
R29
8 Way, 50 Ohm, SMA
Gold
DSUB9
Manuf./Part Number
Emerson/Johnson
142-0701-871
VISHAY
MCT 0603D160
VISHAY
MCT 0603D390
VISHAY
MCT 0603D680
VISHAY
MCT 0603D101
Tyco Electronics
RP73D1J374RBTDG
KOA
SG73S1JTTD3R60F
Tyco Electronics
RP73D1J53R6BTDG
AVX
06031C103K4Z2A
AVX
06035C223KAZ2A
AVX
0603YC104K4Z2A
AVX
0603YD334KAT2A
EPCOS
B82496C3221J
Texas Instruments
UA78M33CKCS
Texas Instruments
UA7805CKCS
NXP
BGM1013
NXP
BGM1014
NXP
BGA2771
NXP
BGA2716
NXP
BGA2776
Minicircuits
LFCN-80
Sup./Part Number
Farnell
1019327
Buerklin
07E424
Buerklin
07E460
Buerklin
07E484
Buerklin
07E500
Farnell
1752436
Farnell
1627682
Farnell
1752346
Farnell
1301715
Farnell
1301890
Farnell
1301713
Farnell
1327681
Farnell
3877115
RS Components
6616737
RS Components
6616692
RS Components
6263752P
RS Components
6263768P
RS Components
6263471P
RS Components
6263465P
RS Components
6263493P
Minicircuits
LFCN-80
Qty.
x50
Manuf./Part Number
Maxim
MAX3232
Harting
09 64 113 7802
Sup./Part Number
Conrad Electronic
167108-BP
Farnell
1779283
ADD TO CART
x1
Manuf./Part Number
Chin Nan Precision
Electronics
CH370800320
Chin Nan Precision
Electronics
CH370800520
Minicircuits
ZCSC-8-1
Sup./Part Number
RS Components
5260392
ADD TO CART
x10
RS Components
5260409
x10
Minicircuits
ZCSC-8-1
x1
x80
x30
x60
x60
x10
x10
x10
x60
x30
x5
x10
x30
x5
x5
x10
x10
x10
x10
x10
x5
x10