Download The FEE board requires 4 channels of DAC for the voltage regulator

An integrated front-end electronics with
silicon photomultipliers
Table of key requirements and potential specifications
Dimensions
SiPM
Output connector
Output characteristics
Amplifier risetime
Full scale range
Bias voltage trim range
Bias voltage trim adjustability
Bias voltage stability
Gain stabilization
Bias voltage temperature coefficient
Power input
Power dissipation (amplifier)
Power dissipation (bias regulator)
Controls interface
Power/controls connector
20.5 mm x 20.5 mm x tbd mm
4x Hamamatsu S10931-025P
MMCX
AC coupled, 50 Ω, to drive 50 Ω load, negative
polarity for ease of interface to standard ADC
modules
<5 ns
>15000 pixels fired in one pulse
+/- 10 V
each SiPM independently, resolution <5 mV
<5 mV (at constant temperature)
Temperature compensated bias voltage
Fixed by design, not adjustable
+3.0 V, −2.0 V, −90 V
40 mW
40 mW
1-wire bus protocol
5 pins microminiature wire connector, e.g. Samtec
T1M-05…
Summing amplifier and cable driver
This needs some design work to optimize, but the signal size is fairly large already from the SiPM and it is
expected that a simple 2 or 3 transistor amplifier will give adequate performance at a lower power level
than would be achieved with a design based on an op-amp. A common-base input stage will be used to
handle the SiPM capacitance; an input transistor per SiPM might be considered.
The response of a quick preliminary design to 500 pixel pulses from two (different) of the four SiPM’s
attached to the summing amplifier, is shown in the following figure. The SiPM is here for the moment
modeled in a oversimplified way as a rectangular current source providing a 22 pC charge (SiPM gain
2.75 x 105), in parallel with 320 pF capacitance.
Voltage regulator
This will use an op-amp & transistor current source, load resistor to drop 10-30 V off the externally
supplied bias voltage, a voltage sense resistor and control feedback resistor & capacitor. The sense
resistor or the DAC output will get a temperature coefficient from a thermistor incorporated in the
circuit. This temperature compensation will be a local analog control, not involving the DAC or external
control software.
Control Interface
The FEE board requires 4 channels of DAC for the voltage regulator control, with ≥12 bit resolution.
However, very little area can be devoted to this function. There are many commercially available quad
DAC’s in small packages that may be used. An I2C interface is preferred (see next paragraph), so a good
candidate is LTC2635-12, occupying 3.5 mm x 3.5 mm on the board.
Since there will be no room for dipswitches on the board, a network interface that involves unique
addressing of a large set of boards “out of the box” is strongly preferred. The Maxim/Dallas “1-wire”
technology works very well for this purpose. We will use the DS2413 as a 1-wire slave to I2C master (with
the remote software providing the I2C protocol details). I2C is preferred over other local busses, e.g. SPI,
to minimize the pin count and board area. The DS2413 occupies 3.0 mm x 3.7 mm.
There are a variety of solutions for the 1-wire master attached to a PC/linux for the control system.
Layout feasibility sketch
The black board outline is 20.5 mm square.
The SiPM’s and the light cone 0.7 x 0.7 inch are indicated in purple.
For the moment, no components other than the SiPM’s are on the bottom side of the board, and only a
single pcb is used, not a stack of pcb’s. These things might change for the real design.
The components shown here are expected to correspond roughly with the real circuit design, but this
hasn’t been checked in great detail. The board can use via-in-pad, blind vias, and multiple layers as may
be required until only placement but not routing constrains the overall dimensions. In other words,
ignoring the routing is acceptable for this initial feasibility sketch.