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FACULTY OF ENGINEERING
LAB SHEET
EEE4116 Semiconductor and
Superconductor Devices
TRIMESTER 2 (2013-2014)
SSD 1 – Operating Characteristics of a Junction Field Effect
Transistor (JFET)
*Note: On-the-spot evaluation may be carried out during or at the end of the experiment.
Students are advised to read through this lab sheet before doing experiment. Your
performance, teamwork effort, and learning attitude will count towards the marks.
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Experiment SSD1: Operating Characteristics of a Junction Field-Effect
Transistor (JFET)
Objectives:
1. To analyze the operation of a JFET by using dc measurement.
2. To investigate the effect of bias on the drain current and also on pinch-off voltage.
Background:
The junction field effect transistor (JFET) has three terminals: the source, the
drain, and the gate, as shown in Figure 1. The source is the semiconductor terminal from
which carriers are emitted that travel through a semiconductor channel to be collected by
the drain. In the N-JFET, the N refers to the type of semiconductor of the channel and the
carriers are electrons. This is a unipolar device, where only one type of carrier contributes
to the current. A positive voltage applied from drain to source is used to accelerate the
electrons through the channel. The third terminal, labeled the gate, is used to control the
flow of electrons. In the single gate device, the gate is situated above the channel. In the
two-gate model, an additional gate is shown below the channel with two gates operating
at the same voltage. The gate, a P+ semiconductor in the N-JFET, is of opposite
conductivity to the channel. If the channel is P-type, holes will flow from the source to
the drain, in the same direction as the current flow, and the gate regions will be N+. The
N-channel JFET schematic symbol has the arrow pointing toward the device, and the Pchannel JFET schematic symbol has the arrow pointing away from the device.
P+-type
Source
Gate
N- type
D
Drain
S
(b) N-channel schematic symbol
Gate
(a) N-channel structure
N+-type
Source
G
Gate
P- type
Gate
(c) P-channel structure
D
Drain
G
S
(d) P-channel schematic symbol
Fig.1: N- and P-channel Junction Field Effect Transistors (JFETs)
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An N-channel JFET is properly biased with a positive voltage applied to drain and
a negative voltage applied to the source, as shown in Figure 2. When the gates of an NJFET are short circuited to the source so that the gate voltage, VGS = 0 (Fig.2a), there is
no control voltage and maximum electron current flows from the source, through the
channel, to the drain, and is referred to as drain current, ID. With this condition, the JFET
is called a “normally on” device. When VGS is reverse biased with a negative voltage, the
electrostatic field on the gate causes a depletion region to occur in the channel. As P + >>
N, most of the depletion region appears in the channel and therefore the effective width
of the channel will be restricted, which causes ID to decrease. With a specific value of
VGS, ID will increase when VDS is increased from 0V and the channel acts like a simple
resistor, and the resulting variation of ID with VDS is linear. However, a point is reached
where an increase in VDS causes an increase of the depletion region, especially near the
drain due to relatively larger reverse biased (Fig.2b). As a result, the depletion region
intrudes into the channel near the drain, and ID tends to level off. Continuing to increase
the drain voltage will eventually cause the top and bottom depletion regions to meet near
the drain (Fig.2c). The complete depletion of the channel is an important special
condition and is referred to as “pinch-off”. Beyond pinch-off the current is saturated
approximately as its value at pinch-off. If VDS is made sufficiently high, avalanche
breakdown could occur, where ID increases sharply, and could possibly damage the JFET.
G
G
S
S
D
D
Electrons
G
G
Depletion
regions
(b) VGS < 0 and VDS > 0
(a) VGS = 0, maximum current
G
S
D
G
(c) Pinch-off occurs
Fig.2: Junction Field Effect Transistor Operation.
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A larger negative value of gate bias VGS increases the width of the depletion
regions and shrinks the VD = 0 width of the channel. Consequently, the resistance of the
channel increases at a given VD value and the linear portion of the ID-VD characteristic
exhibits a smaller slope when VG < 0. Secondly, because the channel is narrower at VD =
0, the channel also becomes pinched off at a smaller drain bias. Thus, the saturation
current IDsat and voltage VDsat when VG < 0 are smaller than IDsat and VDsat when VGS = 0.
As VGS is varied, a family of curves is obtained for the I-V characteristic of the channel,
as shown in Fig.3. Note that if VGS is made sufficiently negative, no ID flows and the
JFET is considered off.
ID
VG = 0
-1
-2
-3
VD
Fig.3: Family of current-voltage curves for the channel as VG is varied
The reverse-biased junction of the gate and source has a high resistance, which
account for the main advantage of the JFET, where high-input-impedance circuits are
needed. Forward bias is seldom used, since the high impedance would be destroyed and
the JFET would not operate properly. A P-channel operates the same way, except that the
voltages are reversed and the majority carriers of the channel are holes
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Part A: Operation of a JFET
Introduction:
In this experiment, the gate is short circuited to the source so that the gate voltage,
VGS = 0. The VDS is increased to various voltages given in the data Table 1, as the drain
current, ID, is determined and recorded. These data are then plotted on the graph and the
pinch-off voltage of the JFET device is estimated. When VGS is 0V, the saturation drain
current, ID, is the maximum value a JFET can have under normal operating conditions.
This current is designated as IDSS.
Equipment Required:
1
1
1
1
1
Adjustable dual  15V power supply
Digital Multimeter
100-  resistor at 0.25W (R)
2N5459 FET (Q1) or equivalent
Breadboard for constructing circuit
Procedure:
1. Construct the circuit shown in Figure.4 for a zero biased N-channel JFET.
R 100
D
G
Q1
VDD
S
Fig.4: Zero gate bias test circuit.
2. Adjust VDD (positive variable supply) to 0.5Vdc.
3. Measure the voltage drop of R and calculate the drain to source current, IDS, through
Q1. Record the value in the proper location of the data table.
4. Increase VDS to the next value given in the data table and repeat step 3.
5. Continue this procedure of adjusting VDS, while calculating and recording ID for all
the values given in the data table.
6. When the data table is complete, arrange the data on the graph A to construct the I-V
characteristics curve.
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VDD (Vdc)
IDS (mA)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
7.0
8.0
9.0
10.0
Table 1: IDS versus VDD data table
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Drain to Source Voltage, VDS (Vdc)
GRAPH A
Questions:
1. Analyze the changes of the drain current in your results based on the operation
principle of JFET.
2. Investigate the reasons that the gate bias voltage provided by your test circuit is zero.
3. Analyze the I-V curve and determine the value of the pinch-off voltage.
4. Evaluate the value of IDSS and determine the reason why does the current remain
constant with increasing values of drain voltage, based on the information you
collected from the I-V curve.
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Part B: The Effect of Gate Bias on Pinch-Off
Introduction:
A reverse biased JFET gate does not draw gate current from the external bias
circuit. The gate represents a very high impedance to the external bias circuit. For an Nchannel JFET, a negative gate voltage (with respect to the source) is required to deplete
the channel. The drain current, ID, of the JFET may be reduced to zero by sufficient
negative gate bias and this is referred to as cut-off. This experiment requires a variable
positive voltage for VDS and a negative voltage for VGS. First, VDD is set to a given value;
then VGG is increased to various voltages given in Table 2, as ID is determined and
recorded. This procedure is repeated for various values of VDD until the data table is
complete. Second, VGG is set to a given value; then VDD is increased to various voltages
given in Table 3, as ID is determined and recorded. Similarly, this procedure is repeated
for various values of VGG until the data table is complete. The VDD and IDS data are then
plotted on the graph to give a more visual indication of the effects of VGG on pinch-off
voltage, VP.
Equipment Required:
2
1
1
1
1
1
Adjustable  15V power supply
Digital Multimeter
100-  resistor at 0.25W (R1)
1-M  resistor at 0.25W (R2)
2N5459 FET (Q1) or equivalent
Breadboard for constructing circuit
Procedure:
1. Construct the circuit shown in Figure 5.
R2  1M
G
_
VGG
VG
D
R1 100
Q1
VDD
S
+
Fig.5: Gate bias JFET test circuit.
2. Adjust the negative variable supply (VGG) for a gate-to-source bias (VGS) of 0Vdc.
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3. Adjust the VDD supply to 10Vdc.
4. Using the multimeter, monitor the voltage drop of R1. Calculate and record the
drain current (ID) for each value of gate voltage (VGG) given in Table 2. Perform
this step for both values of drain voltage listed in the table.
VDD = 10 Vdc
VGG (Vdc)
ID (mA)
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
0.0
VDD = 5 Vdc
VGG (Vdc)
ID (mA)
-4.0
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
Table 2: Gate bias control data.
5. Adjust the gate bias voltage (VGG) for –0.5Vdc. Using the VDD values of Table 3,
complete the IDS column.
6. Repeat step 5 by using VGG = -1Vdc and –1.5Vdc. Record the value in the proper
location of the data table.
7. Using the VDD and IDS data in Table 3, plot the three curves on the graph B. Label
each plot for the specific VGG voltage.
VGG = -0.5 Vdc
VGG = -0.1 Vdc
VGG = -1 Vdc
VDD (Vdc)
IDS (mA)
VDD (Vdc)
IDS (mA)
VDD (Vdc)
IDS (mA)
10
10
10
8
8
8
7
7
7
6
6
6
5
5
5
4.5
4.5
4.5
4
4
4
3.5
3.5
3.5
3
3
3
2.5
2.5
2.5
2
2
2
1.5
1.5
1.5
1
1
1
0.5
0.5
0.5
Table 3: Effects of gate bias on pinch-off voltage, VP.
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Drain to Source Voltage, VDS (Vdc)
Graph B
Questions:
1. Based on Table 2 results:
a) Investigate the outcome of the drain current as the gate bias voltage becomes
more negative.
b) Analyze the results and determine what will happen to the drain current if drain
voltage increases.
2. Evaluate the increase in the gate bias voltage with the saturation current of the JFET?
3. Conclude the relationship between the gate bias voltage and the pinch-off saturation
point of the JFET, based on your data and plots on graph B.
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Marking Scheme
Lab
(10%)
Assessment Components
Hands-On & Efforts (2%)
On the Spot Evaluation
(2%)
Lab Report
(6%)
Details
The hands-on capability of the students and their efforts during the
lab sessions will be assessed.
The students will be evaluated on the spot based on the lab
experiments and the observations on the transistor characteristics.
Each student will have to submit his/her lab final report within 7
days of performing the lab experiment. The report should cover the
followings:
1. Introduction, which includes background information on
junction field effect transistor.
2. Experimental section, which includes the general summary
of the lab experiment work.
3. Results and Discussions, which include the measured
results, analysis, and evaluations, with neat graphs/images
of the results and recorded data.
4. Conclusion, which includes a conclusion on the
experimental.
5. List of References, which includes all the technical
references cited throughout the entire lab report.
The report must have references taken from online scientific
journals (e.g. www.sciencedirect.com,
http://ieeexplore.ieee.org/xpl/periodicals.jsp,
http://www.aip.org/pubs/) and/or conference proceedings (e.g.
http://ieeexplore.ieee.org/xpl/conferences.jsp).
Format of references: The references to scientific journals and text
books should follow following standard format:
Examples:
[1] William K, Bunte E, Stiebig H, Knipp D, Influence of low
temperature thermal annealing on the performance of
microcrystalline silicon thin-film transistors, Journal of
Applied Physics, 2007, 101, p. 074503.
[2] Hodges DA, Jackson HG, Analysis and design of digital
integrated circuits, New York, McGraw-Hill Book Company,
1983, p. 76.
Reports must be typed and single-spaced, and adopt a 12-point
Times New Roman font for normal texts in the report.
Any student found plagiarizing their reports will have the
assessment marks for this component (6%) forfeited.
The lab report has to be submitted to the Electronics lab staff.
Please make sure you sign the student list for your submission. No
plagiarism is allowed. Though the electrical characteristics of the
measured transistor from the same group can be similar, the report
write-up cannot be duplicated for group members. The individual
report has to be submitted within 7 days from the date of your lab
session. Late submission is strictly not allowed.
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