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Parul Institute of Engineering & Technology Subject Code : 2131006 Name Of Subject : Electronics Devices & Circuits Name of Unit : JFETs & MOSFETs Introduction • FET – Field Effect Transistor • The FET is a three terminal device used for a variety of a application. 1.Drain(D) 2.Source(S) 3.Gate(G). • Out of this three, gate terminal acts as a controlling terminal. • The field effect transistor is a semiconductor device, which depends for its operation on the control of current by an electric field Voltage v/s Current Control • FET – Voltage Controllable Device • BJT – Current Controllable Device • VGS (Gate – Source Voltage)is used to control the Id (Drain current) and that’s why it is known for Voltage Controllable. • IB (Base Current) is used to control IC (Collector Current) and that’s why it is known for current controllable. Unipolar v/s Bipolar • In Bipolar device current conduction is taken place because of two types of charge carriers i.e. holes and free electrons. Examples: BJTs, PN Junction Diode • In Unipolar device current conduction is taken place because of only one type of charge carriers i.e. either holes or free electrons. Examples: FET Family Advantages of FETs • • • • • • Better Thermal stability Requires less space Relatively immune to radiation High input impedance Less noisy Low power Consumption Disadvantages of FETs • Relatively small gain band width compare to BJT Classification of FET n-Channel JFET JFET FET p-Channel JFET MOSFET (IGFET) Enhancement MOSFET n-Channel EMOSFET p-Channel EMOSFET Depletion MOSFET n-Channel DMOSFET p-Channel DMOSFET Construction of JFET • Consider a sample bar of N-type semiconductor. This is called Nchannel and it is electrically equivalent to a resistance as shown • Ohmic contacts are then added on each side of the channel to bring the external connection. Thus if a voltage is applied across the bar, the current flows through the channel. • The terminal from where the majority carriers (electrons) enter the channel is called source designated by S. The terminal through which majority carriers leaves the channel is called drain and designated by D. For an N-channel device, electrons are the majority carriers. Hence the circuit behaves like a dc voltage VDS applied across a resistance RDS. The resulting current is the drain current ID. If VDS increases, ID increases proportionally. Construction of JFET • Now on both sides of the n-type bar heavily doped regions of p-type impurity have been formed by any method for creating pn junction. These impurity regions are called gates (gate1 and gate2) as shown in figure. • Both the gates are internally connected and they are grounded yielding zero gate source voltage (VGS =0). The word gate is used because the potential applied between gate and source controls the channel width and hence the current. Construction of JFET • • As with all PN junctions, a depletion region is formed on the two sides of the reverse biased PN junction. The current carriers have diffused across the junction, leaving only uncovered positive ions on the n side and negative ions on the p side. The depletion region width increases with the magnitude of reverse bias. The conductivity of this channel is normally zero because of the unavailability of current carriers. The potential at any point along the channel depends on the distance of that point from the drain, points close to the drain are at a higher positive potential, relative to ground, then points close to the source. Both depletion regions are therefore subject to greater reverse voltage near the drain. Therefore the depletion region width increases as we move towards drain. The flow of electrons from source to drain is now restricted to the narrow channel between the no conducting depletion regions. The width of this channel determines the resistance between drain and source. Construction of JFET • Construction of p-channel JFET is same as n-channel JFET except appropriate changes. Operation of JFET • The voltage between the gate and source is such that the gate is reverse biased. This is the normal connection method of JFET’s. • The drain and source terminals are interchangeable, that is either end can be used as a source and the other end as a drain. The source terminal is always connected to that end of the drain voltage supply which provides the necessary charge carriers, that is, in an N-channel JFET source terminal, S is connected to the negative end of the drain voltage supply for obtaining. • Analysis of N channel JFET can be done with following condition. VDD Fix, VGS = 0v VDD Fix, VGS = small negative value VDD Fix, VGS = large negative value VDD variable , VGS = 0v Operation of JFET • The nonconductive depletion region becomes thicker with increased reverse bias. Operation of JFET Drain - N Gate P P + + N Source + Operation of JFET • The value of Drain current corresponding to VGS = 0v is called Source saturation current, IDSS correspondence to maximum drain current • As and when Gate biasing voltage increased, Drain current decreased and at particular VGS at which the Drain current reduced to 0 mA is known as cut off voltage denoted as VGS(off). • JFET must be operated between VGS = 0V and VGS(off). • The pinch off voltage VP is defined as the value of VDS beyond which the Drain current becomes constant. VP is always defined for VGS = 0. • VGS(off) = -VP V-I Characteristic of JFET V-I Characteristic of JFET Parameters of JFET • • • • • Dynamic Drain Resistance (rd) Transconductance (gm) Amplification Factor (µ) Input Resistance (Rin) Input Capacitance (Ciss) • µ = rd * gm Biasing Circuits for JFET • • • • Fixed Bias Gate Bias Self Bias Voltage Divider Fixed Bias Circuits for JFET • Self bias circuit is a way to bias a FET. Only a drain supply is used and no gate supply. The idea is to use the voltage across RS to produce the gate source reverse voltage. • This is a form of a local feedback similar to that used with bipolar transistors. If drain current increases, the voltage drop across RS increases because the ID RS increases. This increases the gate source reverse voltage which makes the channel narrow and reduces the drain current. The overall effect is to partially offset the original increase in drain current. Similarly, if ID decreases, drop across RS decreases, hence reverse bias decreases and ID increases. Fixed Bias Circuits for JFET •Since the gate source junction is reverse biased, negligible gate current flows through RG and so the gate voltage with respect to ground is zero. VG= 0; •The source to ground voltage equals the product of the drain current and the source resistance. VS= ID R S. •The gate source voltage is the difference between the gate voltage and the source voltage. •VGS = VG – VS = 0 – IDRS •VGS = -ID RS. •This means that the gate source voltage equals the negative of the voltage across the source resistor. • The greater the drain current, the more negative the gate source voltage becomes. •Rearranging the equation: ID = -VGS / RS The graph of this equation is called self base line Gate Bias Circuit for JFET Voltage Divider Bias Circuit for JFET MOSFET MOSFET – Metal Oxide Semiconductor Field Effect Transistor Another type of Field Effect Transistor Widely used in design & construction of IC for digital computers MOSFETs are different from construction of JFET. Having Four Terminal: Source, Drain, Gate & Substrate Current always flows through channel, having end points at source and Drain Types of MOSFET Depletion Type MOSFET Enhancement Type MOSFET Power MOSFET Enhancement MOSFET n-Channel E-MOSFET showing channel length L and channel width W The Drain (D) and Source (S) connect to the to n-doped regions These n-doped regions are not connected via an n-channel without an external voltage The Gate (G) connects to the p-doped substrate via a thin insulating layer of SiO2 The n-doped material lies on a p-doped substrate that may have an additional terminal connection called SS Enhancement MOSFET - Operation When VGS – 0 Volt Drain Current - Zero Channel is absent When VGS – Positive Voltage channel will be formed with the help of minority of Substrate @ Particular VGS, called as Theshold Voltage, VT. Effect of Increase in VDS Fix VGS Gate terminal become less & less positive with respect to drain. Channel width will be reduced to a point of pinch off and saturation will be established. EMOSFET – Characteristics & Symbols N Channel E-MOSFET Characteristics is only for N Channel E-MOSFET VGS is always positive IDSS = 0 when VGS < VT P Channel E-MOSFET As VGS increases above VT, ID increases If VGS is kept constant and VDS is increased, then ID saturates (IDSS) The saturation level, VDSsat is reached. P Channel E - MOSFET Depletion - MOSFET The Depletion-mode MOSFET, which is less common than the enhancement types is normally switched "ON" without the application of a gate bias voltage making it a "normally-closed" device. However, a gate to source voltage ( VGS ) will switch the device "OFF". When VGS = 0V Positive VDD voltage is applied and because of this electrons are attracted towards Drain and current start flowing. When VGS negative Gate terminal repel the electrons from channel into substrate and reduce no. of electrons in channel. Hence current passing through channel is reduce with increasing negative VGS. When VGS Positive Depletion - MOSFET The gate , source and substrate terminal are connected together to the ground point thus VGS=0 volt +VGS means more electrons and more current. While a –VGS means less electrons and less current. The opposite is also true for the P-channel types. Then the depletion mode MOSFET is equivalent to a "normally-closed" switch. N Channel D-MOSFET P Channel D-MOSFET MOSFET Application The Enhancement-mode MOSFETs make excellent electronics switches due to their low "ON" resistance and extremely high "OFF" resistance as well as their infinitely high gate resistance. Enhancement-mode MOSFETs are used in integrated circuits to produce CMOS type Logic Gates and power switching circuits in the form of as PMOS (P-channel) and NMOS (Nchannel) gates.