Download Memory Structures

Memory Structures
Ramon Canal
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Slides based on:Introduction to CMOS VLSI Design. D. Harris
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Outline
• Memory Arrays
• SRAM Architecture
– SRAM Cell
– Decoders
– Column Circuitry
– Multiple Ports
• Serial Access Memories
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Memory Arrays
Memory Arrays
Random Access Memory
Read/Write Memory
(RAM)
(Volatile)
Static RAM
(SRAM)
Dynamic RAM
(DRAM)
Mask ROM
Programmable
ROM
(PROM)
Content Addressable Memory
(CAM)
Serial Access Memory
Read Only Memory
(ROM)
(Nonvolatile)
Shift Registers
Serial In
Parallel Out
(SIPO)
Erasable
Programmable
ROM
(EPROM)
Parallel In
Serial Out
(PISO)
Electrically
Erasable
Programmable
ROM
(EEPROM)
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Queues
First In
First Out
(FIFO)
Last In
First Out
(LIFO)
Flash ROM
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Array Architecture
• 2n words of 2m bits each
• If n >> m, fold by 2k into fewer rows of more columns
wordlines
bitline conditioning
bitlines
row decoder
n-k
n
memory cells:
2n-k rows x
2m+k columns
column
circuitry
k
column
decoder
2m bits
• Good regularity – easy to design
• Very high density if good cells are used
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12T SRAM Cell
• Basic building block: SRAM Cell
– Holds one bit of information, like a latch
– Must be read and written
• 12-transistor (12T) SRAM cell
– Use a simple latch connected to bitline
– 46 x 75  unit cell
bit
write
write_b
read
read_b
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6T SRAM Cell
• Cell size accounts for most of array size
– Reduce cell size at expense of complexity
• 6T SRAM Cell
– Used in most commercial chips
– Data stored in cross-coupled inverters
• Read:
– Precharge bit, bit_b
– Raise wordline
bit
bit_b
word
• Write:
– Drive data onto bit, bit_b
– Raise wordline
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SRAM Read
•
•
•
•
Precharge both bitlines high
Then turn on wordline
One of the two bitlines will be pulled down by the cell
Ex: A = 0, A_b = 1
bit
– bit discharges, bit_b stays high
– But A bumps up slightly
• Read stability
– A must not flip
bit_b
word
P1 P2
N2
A_b
A
A_b
N4
N1 N3
bit_b
1.5
1.0
bit
word
0.5
A
0.0
0
100
200
300
time (ps)
400
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500
600
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SRAM Read
•
•
•
•
Precharge both bitlines high
Then turn on wordline
One of the two bitlines will be pulled down by the cell
Ex: A = 0, A_b = 1
bit
– bit discharges, bit_b stays high
– But A bumps up slightly
• Read stability
– A must not flip
– N1 >> N2
bit_b
word
P1 P2
N2
A_b
A
A_b
N4
N1 N3
bit_b
1.5
1.0
bit
word
0.5
A
0.0
0
100
200
300
time (ps)
400
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500
600
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SRAM Write
•
•
•
•
Drive one bitline high, the other low
Then turn on wordline
Bitlines overpower cell with new value
Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
word
P1 P2
N2
A
A_b
A_b
A
1.5
– Must overpower feedback inverter
N4
N1 N3
– Force A_b low, then A rises high
• Writability
bit_b
bit
bit_b
1.0
0.5
word
0.0
0
100
200
300
400
500
600
700
time (ps)
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SRAM Write
•
•
•
•
Drive one bitline high, the other low
Then turn on wordline
Bitlines overpower cell with new value
Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
bit_b
bit
word
P1 P2
N2
N4
A_b
A
N1 N3
– Force A_b low, then A rises high
A_b
• Writability
– Must overpower feedback inverter
– N2 >> P1
A
1.5
bit_b
1.0
0.5
word
0.0
0
100
200
300
400
500
600
time (ps)
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700
SRAM Sizing
• High bitlines must not overpower inverters during reads
• But low bitlines must write new value into cell
bit_b
bit
word
weak
med
med
A_b
A
strong
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SRAM Column Example
Read
Write
Bitline Conditioning
Bitline Conditioning
2
2
More
Cells
More
Cells
word_q1
word_q1
1
H
out_v1r
SRAM Cell
bit_b_v1f
out_b_v1r
bit_v1f
H
bit_b_v1f
bit_v1f
SRAM Cell
write_q1
data_s1
2
word_q1
bit_v1f
out_v1r
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SRAM Layout
• Cell size is critical: 26 x 45  (even smaller in industry)
• Tile cells sharing VDD, GND, bitline contacts
GND
BIT BIT_B GND
VDD
WORD
Cell boundary
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Periphery
 Decoders
 Sense Amplifiers
 Input/Output Buffers
 Control / Timing Circuitry
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Decoders
• n:2n decoder consists of 2n n-input AND gates
– One needed for each row of memory
– Build AND from NAND or NOR gates
Static CMOS
A1
Pseudo-nMOS
A0
1
1
8
A1
1
4
A0
1
A1
A0
word
A0
1/2
4
16
A1
1
1
2
8
word0
word0
word1
word1
word2
word2
word3
word3
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word
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Decoder Layout
• Decoders must be pitch-matched to SRAM cell
– Requires very skinny gates
A3
A3
A2
A2
A1
A1
A0
A0
VDD
word
GND
buffer inverter
NAND gate
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Large Decoders
• For n > 4, NAND gates become slow
– Break large gates into multiple smaller gates
A3
A2
A1
A0
word0
word1
word2
word3
word15
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Predecoding
• Many of these gates are redundant
– Factor out common
gates into predecoder
– Saves area
– Same path effort
A3
A2
A1
A0
predecoders
1 of 4 hot
predecoded lines
word0
word1
word2
word3
word15
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Periphery
 Decoders
 Sense Amplifiers
 Input/Output Buffers
 Control / Timing Circuitry
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Sense Amplifiers
C  V
tp = ---------------Iav
large
make  V as small
as possible
small
Idea: Use Sense Amplifer
small
transition
s.a.
input
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output
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Sense Amplifiers
• Bitlines have many cells attached
– Ex: 32-kbit SRAM has 256 rows x 128 cols
– 128 cells on each bitline
• tpd  (C/I) V
– Even with shared diffusion contacts, 64C of diffusion
capacitance (big C)
– Discharged slowly through small transistors (small I)
• Sense amplifiers are triggered on small voltage swing
(reduce V)
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Differential Pair Amp
• Differential pair requires no clock
• But always dissipates static power
sense_b
bit
P1
P2
N1
N2
sense
bit_b
N3
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Clocked Sense Amp
• Clocked sense amp saves power
• Requires sense_clk after enough bitline swing
• Isolation transistors cut off large bitline capacitance
bit
bit_b
isolation
transistors
sense_clk
regenerative
feedback
sense
sense_b
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Periphery
 Decoders
 Sense Amplifiers
 Input/Output Buffers
 Control / Timing Circuitry
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Column Circuitry
• Some circuitry is required for each column
– Bitline conditioning
– Column multiplexing
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Bitline Conditioning
• Precharge bitlines high before reads

bit
bit_b
• Equalize bitlines to minimize voltage difference when
using sense amplifiers

bit
bit_b
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Twisted Bitlines
• Sense amplifiers also amplify noise
– Coupling noise is severe in modern processes
– Try to couple equally onto bit and bit_b
– Done by twisting bitlines
b0 b0_b b1 b1_b b2 b2_b b3 b3_b
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Column Multiplexing
• Recall that array may be folded for good aspect ratio
• Ex: 2 kword x 16 folded into 256 rows x 128 columns
– Must select 16 output bits from the 128 columns
– Requires 16 8:1 column multiplexers
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Tree Decoder Mux
• Column mux can use pass transistors
– Use nMOS only, precharge outputs
• One design is to use k series transistors for 2k:1 mux
– No external decoder logic needed
B0 B1
B2 B3
B4 B5
B6 B7
B0 B1
B2 B3
B4 B5
B6 B7
A0
A0
A1
A1
A2
A2
Y
to sense amps and write circuits
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Y
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Single Pass-Gate Mux
• Or eliminate series transistors with separate decoder
A1
A0
B0 B1
B2 B3
Y
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Ex: 2-way Muxed SRAM
2
More
Cells
More
Cells
word_q1
A0
A0
write0_q1
2
write1_q1
data_v1
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Memory configuratons
 Multiported memories
 CAM Memories
 Serial Access, Queues
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Multiple Ports
• We have considered single-ported SRAM
– One read or one write on each cycle
• Multiported SRAM are needed for register files
• Examples:
– Multicycle processor must read two sources or write a result on
some cycles
– Pipelined processor must read two sources and write a third
result each cycle
– Superscalar processor must read and write many sources and
results each cycle
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Dual-Ported SRAM
• Simple dual-ported SRAM
– Two independent single-ended reads
– Or one differential write
bit
bit_b
wordA
wordB
• Do two reads and one write by time multiplexing
– Read during ph1, write during ph2
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Multi-Ported SRAM
• Adding more access transistors hurts read stability
• Multiported SRAM isolates reads from state node
• Single-ended design minimizes number of bitlines
bD bE bF bG
bA bB bC
wordA
wordB
wordC
wordD
wordE
wordF
wordG
write
circuits
read
circuits
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Memory configuratons
 Multiported memories
 CAM Memories
 Serial Access, Queues
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Contents-Addressable Memory
Commands
R/W Address (9 bits)
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CAM Array
2 words 3 64 bits
9
Priority Encoder
Mask
Address Decoder
Control Logic
Comparand
29 Validity Bits
I/O Buffers
Data (64 bits)
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Memory configuratons
 Multiported memories
 CAM Memories
 Serial Access, Queues
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Serial Access Memories
• Serial access memories do not use an address
–
–
–
–
–
Shift Registers
Tapped Delay Lines
Serial In Parallel Out (SIPO)
Parallel In Serial Out (PISO)
Queues (FIFO, LIFO)
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Shift Register
• Shift registers store and delay data
• Simple design: cascade of registers
– Watch your hold times!
clk
Din
Dout
8
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Denser Shift Registers
• Flip-flops aren’t very area-efficient
• For large shift registers, keep data in SRAM instead
• Move read/write pointers to RAM rather than data
– Initialize read address to first entry, write to last
– Increment address on each cycle
Din
clk
11...11
reset
counter
counter
00...00
readaddr
writeaddr
dual-ported
SRAM
Dout
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Tapped Delay Line
• A tapped delay line is a shift register with a
programmable number of stages
• Set number of stages with delay controls to mux
– Ex: 0 – 63 stages of delay
clk
delay2
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SR1
delay3
SR2
delay4
SR4
delay5
SR8
SR16
SR32
Din
delay1
Dout
delay0
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Serial In Parallel Out
• 1-bit shift register reads in serial data
– After N steps, presents N-bit parallel output
clk
Sin
P0
P1
P2
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P3
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Parallel In Serial Out
• Load all N bits in parallel when shift = 0
– Then shift one bit out per cycle
P0
P1
P2
P3
shift/load
clk
Sout
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Queues
• Queues allow data to be read and written at different
rates.
• Read and write each use their own clock, data
• Queue indicates whether it is full or empty
• Build with SRAM and read/write counters (pointers)
ReadClk
WriteClk
WriteData
FULL
Queue
ReadData
EMPTY
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FIFO, LIFO Queues
• First In First Out (FIFO)
–
–
–
–
–
Initialize read and write pointers to first element
Queue is EMPTY
On write, increment write pointer
If write almost catches read, Queue is FULL
On read, increment read pointer
• Last In First Out (LIFO)
– Also called a stack
– Use a single stack pointer for read and write
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Other considerations
 Leakage control
 Redundancy
 Flash Memories
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Suppressing Leakage in
SRAM
V DD
V DD
low-threshold transistor
V DDL
sleep
V DD,int
sleep
V DD,int
SRAM
cell
SRAM
cell
sleep
SRAM
cell
SRAM
cell
SRAM
cell
SRAM
cell
V SS,int
Inserting Extra Resistance
Reducing the supply voltage
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Other considerations
 Leakage control
 Redundancy
 Flash Memories
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Redundancy
Row
Address
Redundant
rows
:
Redundant
columns
Fuse
Bank
Memory
Array
Row Decoder
Column Decoder
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Column
Address
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Error-Correcting Codes
Example: Hamming Codes
e.g. B3 Wrong
with
1
1
=3
0
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Redundancy and Error Correction
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Other considerations
 Leakage control
 Redundancy
 Flash Memories
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Flash EEPROM
Control gate
Floating gate
erasure
n 1 source
Thin tunneling oxide
programming
n 1 drain
p-substrate
Many other options …
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Cross-sections of NVM cells
Flash
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Courtesy Intel
EPROM
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Basic Operations in a NOR Flash
Memory―
Erase
cell
BL 0
array
BL 1
G
12 V
S
WL 0
0V
D
12 V
WL 1
0V
open
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open
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Basic Operations in a NOR Flash
Memory―
Write
12 V
G
BL 0
BL 1
6V
WL 0
12 V
S
D
0V
WL 1
0V
6V
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0V
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Basic Operations in a NOR Flash
Memory―
BL 0
BL 1
Read
5V
G
1V
WL 0
5V
S
D
0V
WL 1
0V
1V
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0V
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Conclusions
Memory Structure:
AK
A K1 1
AL2 1
Bit line
Storage cell
Row Decoder
2L 2 K
Word line
M.2K
Sense amplifiers / Drivers
A0
A K2 1
Column decoder
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
Input-Output
(M bits)
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