Download Memory Organization and Interfacing

Memory Organization
and Interfacing
CSE 2312
Maher Al-Khaiyat
Semiconductor Memory

Capacity
• Kbits (Kilobits)
• Mbits (Megabits)

Organization
• Number of locations => Number of
address lines
• Size of a location => Number of data
lines
Semiconductor Memory (cont’d)

Speed
• Access time

Volatility

Programmability
Memory Organization
Number of address lines
Number of locations
2 y
x
Number of data lines
Nonvolatile Memory


Read-Only Memory (ROM)
Programming or Burning
• PROM; one-time programmable
• EPROM; erasable using UV radiation
• EEPROM; electrically erasable
• Flash ROM; erasable in a flash (fast
time)
• Mask ROM; mask technology
Volatile Memory


Random Access Memory (RAM)
Types
• Static RAM (SRAM)


does not require refreshing
up to four transistors per cell
• Dynamic RAM (DRAM)


requires refreshing
one transistor (capacitor) per cell
Address Decoding
A19
A0
0000
1000
0000 0000
………
0000
0000
1111
1111
1111
1111
D7
D0
A0
32Kx8
A15
A16
A17
A18
A19
A14
CS
OE
MEMR
Range of addresses 08000h to 0FFFFh
WR
MEMW
Conventional Memory

640K of RAM
FFFFFh
C0000h
BFFFFh
A0000h
9FFFFh
BIOS temp data
Interrupt vector table
004FFh
003FFh
00000h
ROM 256K
VDR 128K
RAM 640K
Conventional
memory
•MS-DOS OS
•Utilities
•Applications
•Etc…
BIOS Data Area
Start Address
End Address
# Bytes
Description
0000:0000
0000:03FF
1024
Interrupt table
0000:0400
0000:0401
2
Port address COM1
…
…
…
…
0000:0408
0000:0409
2
Port address LPT1
….
….
…
…
0000:0410
0000:0411
2
List of hardware
0000:00412
0000:0412
1
Initialization flag
0000:0413
0000:0414
2
Memory size (KB)
…
…
…
…
…
…
…
…
DRAM Memory Banks
Bank 3
64K x 4
64K x 4
64K x 1
Bank 2
64K x 4
64K x 4
64K x 1
Bank 1
256K x 4
256K x 4
256K x 1
Bank 0
256K x 4
256K x 4
256K x 1
Example configuration of 640KB RAM