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Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six 2.1 (p11) = 248 nm = 0.248 m 2.2 (p11) 1 ns = 1000 ps 2.3 (c) (d) (p11) (60 W)(24 h/day)(60 min/h)(60 s/min) = 5.184 MJ; (60 W)(1 kW/1000 W)(24 h/day)(7 day/wk) (12.5 cents/kWh) = $1.26/week 2.4 (p13) electrons moving left result in a positive current flowing right. Thus, I2 = + 1 mA, and I1 = I2 = 1 mA. 2.5 (p15) v1 = v2 so v2 = v1 = 17 V 2.6 (p17) We have + 4.6 A flowing into the positive reference terminal of a voltage 220 mV. Using the passive sign convention, the absorbed power is Pabs = 4.6 0.220 = 1.012 W. 2.7 (p17) We have a current 1.75 A flowing out of our positive voltage reference terminal, or + 1.75 A flowing into the positive reference terminal. Thus, applying the passive sign convention we find Pabs = 1.75 3.8 = 6.65 W or a generated power of Pabs = + 6.65 W. 2.8 (p17) We see that a current of + 3.2 A flows out of our positive voltage reference terminal, so a current 3.2 A flows into that positive reference terminal. Applying the passive sign convention, Pabs = 8e 100t 3.2 = 25.6 e 100t W Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six Pabs (t 5 ms) (25.6)e100(510 = 15.53 W 2.9 3 ) (p20) Moving from left to right and applying the passive sign convention, Pabs Pabs Pabs Pabs Pabs = = = = = 7 8 = 56 W 2 8 = + 16 W 5 12 = 60 W 8 20 = + 160 W 0.25vx 20 = [0.25 12] 20 = 60 W (Check: 56 + 16 60 + 160 60 = 0 ) 2.10 (p24) v i R so R 2.11 v 6.3 3.938 k i 1.6 103 (p24) v i R, Pabs v i so Pabs v 2 (6.3)2 R 21 = 1.89 W 2.12 (p24) Pabs v i P 0.24 i abs 30 mA v 8 2.13 (p27) R = (4000 ft)(0.1563 /1000 ft) = 0.6252 P = i2R = (100 A)(100 A)(0.6252 ) = 6.252 kW Weight is proportional to mass, and mass is proportional to volume. Hence, new weight = old weight × new volume/old volume Since volume = cross sectional area × length and the length remains unchanged, new weight = old weight (33.6 mm2/ 21.1 mm2) = 1.59 times the old weight. Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved 3.1 Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six (p38) 5 branches 3 nodes Define i18v out of the “+” terminal of the 18 V source; iRA downward through resistor RA. By KCL, i18v iRA ix 13 0 8 iRA 3 13 0 iRA 8 13 3 18 A so By Ohm’s Law, RA 3.2 18V 1 18 A (p39) By KVL, + 3 + 1 + vx = 0 so vx = 4 V By Ohm’s Law, ix 3.3 vx 400 mA 10 (p42) We begin by writing a simple KVL equation: 30 2 8 v10 0 where v10 has a “+” reference on the top terminal of the 10 resistor. v10 30 16 14 V The current down through the 10 resistor is v10 14 1.4 A 10 10 Thus, 2 1.4 = 0.6 A flows left to right through the top 2 resistor. KVL yields v10 2 0.6 vx 0 so vx 14 1.2 12.8 V 3.4 (p43) A single KVL equation yields vs1 R1i vs2 R2i 0 or i vs1 vs2 R1 R2 120 30 2A 30 15 Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six Pabs vs1 2 120 240 W Pabs R1 22 30 120 W pabs vs2 Pabs R2 2 30 60 W 22 15 60 W (Check: 240 + 120 + 60 + 60 = 0) 3.5 (p44) Writing a single KVL equation, with a clockwise current i vx 12 (8 7) i 4vx 0 [1] v and i x [2] 30 leads to vx 24 V and i 4 A 5 25 2 24 1 768 mW 30 5 30 4 Pabs 12v 12 1.92 W 25 2 4 Pabs 8 8 204.8 mW 25 2 4 Pabs 7 7 179.2 mW 25 4 4 24 Pabs 4vx 4vx 4 3.072 W 25 25 5 (Check: 768 + 1920 + 204.8 + 179.2 – 3072 = 0 mW) Pabs 3.6 (p46) Summing the currents entering the top node, 5 v v 1 6 0 10 10 leads to v = 50 V Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved 3.7 Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six (p47) Summing the currents entering the top node, 5.6 vx v 0.1vx x 2 0 18 9 leads to vx = 54 V iA 3.8 vx v 3 A, iB 0.1vx 5.4 A, iC x 6 A 18 9 (p50) (5 1 6) v v 0 leads to v = 50 V 10 10 3.9 (p51) The circuit is valid as drawn. The current from each source adds, so that a total of 8 A flows through the resistor. All three elements are in parallel so each element has the same voltage across it. Since there are no voltage sources present there can be no conflict. However, if the resistor were to be removed, the resulting circuit would be in conflict with Kirchhoff’s current law (KCL). 3.10 (p53) We first simplify the circuit: where Vs = 5 + 5 + 5 =15 V R = 15 + 25 +5 = 45 i i 3.11 Vs 15 333.3 mA R 45 (p55) v (5 1 6)10 //10 10 5 50 V 3.12 (p56) We first simplify the circuit: Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six v where R = 4 // (2 + 2) // (10 + 10) = 4 // 4 // 20 = 1.818 - V = 7R = 7 (1.818) = 12.73 V + 3.13 (p59) Noting that we can combine the two 10 resistors into a single 5 resistor, 2 vx 10 2 V 235 3.14 (p60) (1) The resistors to the right of the 125 resistor combine into R = 50 // [2 + 240 // (40 + 20)] = 25 125 100 mA By current division, i1 120 125 25 (2) The resistors to the right of the 50 resistor combine into Rx = 2 + 240 // (40 + 20) = 50 By current division, i2 i1 (3) 50 50 mA 50 50 The current through the 20 resistor is i2 240 40 mA. Thus, v3 = 20 0.04 = 0.8 V 240 40 20 Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved 4.1 Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six (p83) The bottom node is the obvious choice for a reference node. At the top left node 5 v1 v v 1 2 23 15 [1] and at the top right node, 2 v2 v2 v1 4 15 [2] Simplifying, we obtain -75 = 4v1 v2 and 120 = 4v1 + 19v2 [1] [2] Solving, we obtain v1 = -18.125 V and v2 = 2.5 V 4.2 (p86) we number the top nodes 1, 2 and 3 moving left to right. At node 1, At node 2, At node 3, v1 v3 v1 v2 2 1 v v v v v 0 2 1 2 2 3 1 3 4 v3 v3 v2 v3 v1 7 5 4 2 3 [1] [2] [3] Simplifying, we obtain 6 3v1 2v2 v3 [1] 0 12v1 19v2 3v3 [2] 140 10v1 5v2 19v3 [3] Solving, v1 = 5.235 V and v3 = 11.47 V Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved 4.3 Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six (p88) There are two basic strategies here: (1) insert the quantity for A and solve; or (2) write two general equations in terms of A, then substitute and solve. Here, we’ll go with the second option. Thus, at node 1 we can write 5 v1 v1 v2 or 3v1 2v2 10 2 1 [1]. At node 2, we write A 4.4 v2 v2 v1 or 2v1 3v2 2 A 2 1 [2]. (a) Substitute A = 2i1 into Eqn [2]. We then note that i1 = v1 – v2. So Eqn [1] is unchanged but Eqn [2] becomes 6v1 7v2 0 [2’]. Solving Eqns [1] and [2’], we find that v1 = 70/9 V. (b) Substitute A = 2v1 into Eqn [2], which then becomes 6v1 7v2 0 [2’’]. Solving Eqn [1] and Eqn [2’’] we thus obtain v1 = -10 V. (p90) Define the top left node 1, and the top right node 2. Treating these two nodes as a single supernode, or 4 9 3(v1 v2 ) 3(v2 v1 ) 2v1 6v2 13 2v1 6v2 [1] The remaining equation is simply v1 v2 = 5 Solving, 4.5 v1 = 5.375 V and [1] [2] v2 = 375.0 mV (p91) By inspection, v1 = -3V [1] v2 v1 v2 v3 or -2v1 + 3v2 – v3 = 8 [2] 1 2 v v 2 v3 v 4 At node 3, we can write 5v x 3 . Since vx = v3 – v4, this becomes 2 4 -2v2 - 17v3 + 19v4 = 0 [3] v4 v1 v4 v4 v3 At node 4, 0 or -6v1 - 3v3 + 13v4 = 0 [4] 2 3 4 At node 2, we can write 4 Solving, we find that v1 = -3 V (known), v2 = -0.0270 V, v3 = -2.081 V, and v4 = -1.865 V. Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved 4.6 Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six (p95) mesh 1: 6 14i1 (5 5)i1 (5 5)i2 0 mesh 2: (5 5)i2 (5 5)i1 10i2 5 0 4.7 Simplifying, 24i1 10i2 6 10i1 20i2 5 Solving, i1 = 184.2 mA i2 = 157.9 mA [1] [2] (p96) define clockwise i3 in third mesh. mesh 1: 10 4i1 4i2 3 0 mesh 2: (4 5 9 10)i2 4i1 10i3 0 mesh 3: 3 (10 1 7)i3 10i2 0 4.8 4.9 [1] [2] Simplifying, 4i1 4i2 7 4i1 28i2 10i3 0 10i2 18i3 3 Solving, i1 = 2.220 A and [1] [2] [3] [1] [2] [3] i2 = 469.9 mA (p97) (a) With A = 2i2, we can write two mesh equations: 2 = (2 + 5)i1 – 5i2 – 2i2 or 7i1 – 7i2 = 2 [1] 6 = (4+5+3)i2 – 5i1 or -5i1 + 12i2 = 6 [2] Solving, we obtain i1 = 1.347 A. (b) With A = 2vx = 2(i1 – i2)(5) = 10 i1 – 10 i2, we can write two mesh equations: 2 = (2 + 5)i1 – 5i2 – 10i1 + 10i2 or -3i1 + 5i2 = 2 [1] 6 = (4+5+3)i2 – 5i1 or -5i1 + 12i2 = 6 [2] Solving, we obtain i1 = 545.5 mA. (p99) define clockwise current i2 in top right mesh and clockwise current i3 in bottom right mesh. form supermesh with meshes 1 and 3. Supermesh: 10 4i1 4i2 (10 1 7)i3 10i2 0 Engineering Circuit Analysis, 7th Edition [1] Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six mesh 2: [2] (4 5 9 10)i2 4i1 10i3 0 remaining equation: i3 i1 3 [3] 4.10 Simplifying, 4i1 14i2 18i3 10 4i1 28i2 10i3 0 i1 + i3 = 3 Solving, i1 = 1.933 A [1] [2] [3] (p100) define two clockwise currents: i2 in top right mesh, i3 in bottom right mesh. mesh 1: -80 + 10i1 + 20(i1 – i2) + 30(i1 – i3) = 0 2,3 supermesh: -30 + 40i3 + 30(i3 – i1) + 20(i2 – i1) = 0 Supermesh equation: i3 – i2 = 15i1 [3] Solving, [1] [2] i3 = 2.604 A Thus, v3 40ib 104.2 V Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved 5.1 Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six (p125) Shorting the 3.5-V source, 73 i x 2 800 mA 7 3 15 Open circuiting the 2-A source, ix 1 15 3.5 140 mA 15 3 7 15 ix ix ix 660 mA 5.2 (p127) (1) Shorting the 3-V source, we apply nodal analysis to find: Node 1: 2 v1 v2 v1 15 7 Node 2: 4i [1] v2 v2 v1 5 15 [2] The presence of the dependent source has introduced a new variable, requiring an additional equation: i v2 5 [3] Simplifying and reducing to two equations, 210 22v1 7v2 [4] 0 v11 8v12 [5] Solving, (2) v1=9.180 V and v2 = 1.148 V Open-circuiting the 2-A source, we apply mesh analysis after defining two clockwise mesh currents i1 and i2. mesh 1: 3 (7 15 5)i1 5i2 0 mesh 2: i2 4i where i i1 i2 Engineering Circuit Analysis, 7th Edition [1] [2] [3] Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six Simplifying, 27i1 5i2 3 4i1 3i2 0 [1] [4] Solving, i1 147.5 mA and i2 196.7 mA so, v1 7i1 3 1.967 V and v2 5(i1 i2 ) 245.9 mV Thus, v1 = v1 + v1 = 11.15 V and v2 = v2 + v2 = 1.394 V 5.3 (p135) 5 V in series with 5 k 1 mA in parallel with 5 k (arrow pointing up). 5000 I x 1103 1103 192.3 A 5000 47000 5.4 (p136) 75 A in parallel with 4 M 300 V in series with 4 M (“+” on top). 40 A in parallel with 200 k 8 V in series with 200 k (“+” on right). + V - 6 M 4 M 0.2 M 1 M This circuit may be further reduced to +V300 + 8 – 3 = 10.2 M By voltage division, V 305 * 1 M 1 27.23 V 10.2 1 The circuit could by transformed to have a current source, but no reduction in complexity would result. Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six 5.5 (p118) 5.6 5 A in parallel with 2 10 V in series with 2 (“+” on top) we now have 2 in series with 8 10 10 V in series with 1 1 A in parallel with 10 (arrow pointing up) we now have 10 // 10 = 5 1 A in parallel with 5 This is the Norton equivalent (p142) (1) Removing the 2- resistor and leaving the terminals open-circuited, no current flows through the 5- resistor; hence, there is no voltage drop across it. So, VTH VOC V4 9 (2) 4 2.571 V 446 Shorting the 9-V source with the 2- resistor removed, we see 5 4 //(4 6) 7.857 (3) We may now find I2 by I 2 5.7 VTH 260.8 mA RTH 2 (p145) (1) First, short the 3-V source and open-circuit the 7-mA source. Looking in from the terminals, we see a resistance 1 + 5 // 2 = 2.429 k. (2) Realising that no current flows through the 1-k resistor, we quickly apply nodal analysis to find: 7 103 v3 v 2000 5000 Solving, v = 7.857 V = VTH (3) I SC VTH 3.235 A RTH Engineering Circuit Analysis, 7th Edition (“+” on top) (source oriented with arrow pointing upwards). Copyright 2007 McGraw-Hill, Inc. All Rights Reserved 5.8 Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six (p146) Transform the dependent source to a dependent voltage source: + 20 k 200V1 + V1 - - A simple KVL equation yields 200 V1 100 V1 0 or V1 = 502.5 mV = VTH Shorting the terminals, we then find 0 200V1 20000 I SC 100 0 0 or I SC 5 mA RTH 5.9 VTH 100.5 I SC (p149) There are no independent sources so VTH = 0. install a 1-V test source, “+” on top, across the open terminals. define two clockwise mesh currents iL and iR. left mesh: right mesh: and: 20i1 10iL 30iL 30iR 0 (30 5)iR 30iL 1 0 i1 iL iR [1] [2] [3] Simplifying, 20i1 40iL 30iR 0 [1] 30iL 35iR 1 [2] iL 0 [3] i1 iR Solving, iR 50 mA iR flows out of the 1-V source. The Thévenin equivalent resistance, therefore, is 1 20 iR Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six 5.10 (p152) First find the Thévenin equivalent connected to Rout Removing Rout, we are left with a single mesh. Define a clockwise mesh current i1. Then (2000 + 2000) i1 + 20 + 30 = 0 and i1 = 12.5 mA. VTH 40 30 2000(12.5 103 ) 35 V Shorting the sources, RTH 2 kΩ//2 kΩ=1 kΩ 1 k Rout (a) With Rout 3 k, VRout 35 3 26.25 V 1 3 (26.25) 2 229.7 mW 3000 (35 / 2) 2 306.3 mW 1000 (b) Pmax (c) 20 103 (Vout )2 Rout where Vout 35 Rout 1000 Rout so 20 103 352 Rout (1000 Rout )2 Solving, Rout = 16.88 or 59.23 k Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved 5.11 Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six (p154) convert RV3, RV4, RV5 to a T-network RT1, RT2, RT3. 10 10 3.333 10 10 10 RT3 RT2 RT1 3.333 RT1 RH1 + RT1 = RS1 = 13.33 RS2 = RH2 + RT2 = 13.33 RS3 = RH3 + RT3 = 13.33 convert T-network RS1, RS2, RS3 to a connected network RD1, RD2, RD3 RD1 = 40 RS1 RS2 RS2 RS3 RS3 RS1 RS2 RD3 = RD2 = RD1 = 40 Rin (RV1// RD1) (RV2 // RD3) // RD2 11.43 Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved 6.1 Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six (p177) 6.2 Because Rule #1 states that no current flows into either input terminal, we know that the voltage on either side of resistor Rin is equal to vin. Invoking Rule #2, which states that the voltage at both input pins must be the same, we can conclude that vout = vin (p179) vb v2 1 v2 2 By Rule #2, va vb A KVL equation starting at v1 yields: v1 Ri1 Ri1 vout 0 6.3 R 1 v2 RR 2 [1] [2] (making use of Rule #1). To obtain an expression for vout in terms of the input, we need to eliminate i1. v1 Ri1 va 0 1 v1 v2 v1 va 2 [3] i1 R R 1 v1 2 v2 Substituting into [2], v1 2 R vout 0 R or vout = v2 v1 (p185) As a true design problem, there is no “unique” solution. We need to determine the total weight of the vehicle from the weight measured by four separate scales. This indicates that a summing amplifier might be practical here, since we are also told that each scale provides a voltage signal proportional to the weight measured. Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six Rf v1 v2 v3 . Since we have R four wheel scales, we need to add an additional source v4 in the circuit above. If we set Rf = R, then the output voltage is the negative sum of the input voltages. Thus, if 1 mV = 1 kg at the input, 1 mV = 1 kg at the output as well. However, the negative sign will result in a negative voltage. There are several ways around the problem, but one is to add an inverting amplifier at the output with both resistors set to whatever we choose for Rf above. In this type of amplifier, the output vout is given by vout 6.4 (p. 188) Since the 1N750 Zener diode has a breakdown voltage of approximately 4.7 V, and we need a reference voltage of 6 V, we construct the type of circuit suggested and select Vbat = 9 V: The input voltage to the noninverting amplifier is taken to be 4.7 V (it can vary slightly depending on the current flowing through the diode). The output is simply vout = (1 + Rf/R1)(4.7). Since we want vout = 6 V, somewhat arbitrarily choosing R1 = 1 k leads to Rf = 277 . To complete the design we need to select a value for Rref. We do this based on the current we want to flow through the Zener diode, since no current flows into the input of the op amp. Following the logic of Example 6.4 (p. 188), we design for 50% of the maximum rated diode current, or 37.5 mA, leading to Rref = (Vbat – VZener)/ IZener = (9 – 4.7)/0.0375 = 115 . 6.5 (p190) We base our design on the circuit shown in Fig. 6.22 (p190). Selecting again a 9 V battery in series with a 100 resistor connected to the noninverting input terminal to the op amp, and using a 1N750 Zener diode, we expect approximately 4. 9 V at the op amp input terminals. Selecting 9.8 k for the remaining resistor forces a current of 4.9/9.8 = 0.5 mA to flow through RL, assuming the value of RL does not somehow affect the performance of the op amp. Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six 6.6 (p192) vout vin + - vd Avd + vout Avd 0 [1] vd vin vd vd Avd R1 Ri Rf [2] Simplifying [2] yields vd Ri R f vin Ri R f R1 R f (1 A) R1Ri Using [1], we then obtain A Ri R f vout vin Ri R f R1 R f (1 A) R1 Ri 6.7 (p201) The circuit from Fig. 6.6 (p. 176) cannot be simulated without performing a more sophisticated simulation than we have discussed so far. Replacing the sinusoidal source with a 1-V dc source, however, verifies a gain of 11: Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six The circuit from Fig. 6.8 (p. 177) may be simulated in a similar fashion: As a final example, we simulate the circuit in Fig. 6.9 (p. 178), which is a basic summing amplifier. Choosing all resistors to have equal value and neglecting the output resistor, we expect the output to be the negative of the sum of the three input voltages, or –(1 + 2 + 3) = –6. The simulation agrees to within 3 significant figures. The slightly nonideal behaviour of the op amp in this particular circuit is also evident in comparing the voltages at the input, which are not precisely equal, leading to the observed discrepancy with the ideal op amp prediction. Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved 6.8 Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six (p202) Again, as a traditional design problem, there is no unique solution. We choose to implement our solution using a comparator circuit, with the input voltage signal connected to the noninverting input terminal, and the inverting input grounded. Selecting a –2 V source for the negative power supply ensures an output of -2 V until vsignal exceeds 0 V. Since we want an output voltage of 12 V when vsignal > 0, we select a 12 V source for the positive power supply. Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved