Download AVC Logic Family Technology and Applications

AVC Logic Family
Technology and Applications
SCEA006A
August 1998
1
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Copyright  1998, Texas Instruments Incorporated
2
Contents
Title
Page
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
AVC Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unparalleled Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Novel Output Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mixed-Voltage Mode and Power Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
2
3
Design Issues and AVC Family Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Power (Optimized for 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused and Undriven Inputs (Bus Hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Partial Power-Down and Mixed-Voltage-Mode Data Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
5
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Switching Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Characteristics With DOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Design Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Appendix A – Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
iii
List of Illustrations
Figure
Title
Page
1
Low-Voltage Logic Family Performance Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2
Impedance Changes Through Switching Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
Totem-Pole Input Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4
Typical Bus-Hold Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5
Bus Hold Across VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
Device at 2.5-V VCC With 3.3-V I/Os on One Side and 2.5-V I/Os on the Other, Showing Switching Levels . . . . 6
7
Device at 1.8-V VCC With 2.5-V Inputs or 3.3-V Inputs, Showing Switching Levels . . . . . . . . . . . . . . . . . . . . . . . 6
8
ICC vs Frequency With 1, 8, or 16 Outputs Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
9
ICC vs VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
10
VO vs VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
11
tPHL vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12
tPLH vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
13
tPHL vs Load Capacitance, One Output Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
14
tPLH vs Load Capacitance, One Output Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
15
tPHL vs Load Capacitance, 16 Outputs Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
16
tPLH vs Load Capacitance, 16 Outputs Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
17
Simultaneous-Switching Voltage (VOLP, VOLV) vs Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
18
Simultaneous-Switching Voltage (VOHP, VOHV) vs Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
19
Slow Input-Transition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
20
Pin-to-Pin Skew (tPHL, tPLH) (<100 ps nominal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
21
VOL vs IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
22
VOH vs IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
A-1
AVC Parameter Measurement Information (1.8 V ± 0.15 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
A-2
AVC Parameter Measurement Information (VCC = 2.5 V ± 0.2 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
A-3
AVC Parameter Measurement Information (VCC = 3.3 V ± 0.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
List of Tables
Table
iv
Title
Page
1
Cpd for Various Conditions, One Output Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Selected AVC Family Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Abstract
Texas Instruments (TI) announces the industry’s first logic family to achieve maximum propagation delays of less than 2 ns
at 2.5 V. TI’s next-generation logic is the Advanced Very-low-voltage CMOS (AVC) family. Although optimized for 2.5-V
systems, AVC logic supports mixed-voltage systems because it is compatible with 3.3-V and 1.8-V devices. The AVC family
features TI’s Dynamic Output Control (DOC) circuit (patent pending). The DOC circuit provides enough current to achieve
high signaling speeds, but automatically lowers the output impedance of the circuit during a signal transition and subsequently
increases the impedance to reduce the overshoot and undershoot noise that is often found in high-speed logic. This feature of
AVC logic eliminates the need for series damping resistors. AVC logic also has a power-off feature that disables outputs from
the device when no power is applied.
Introduction
Current trends in advanced digital electronics design continue to include lower power consumption, lower supply voltages,
faster operating speeds, smaller timing budgets, and heavier loads. Many designs are making the transition from 3.3 V to 2.5 V,
and bus speeds are increasing beyond 100 MHz. Encompassing all these goals makes the requirement of signal integrity more
difficult to achieve. For designs that require very-low-voltage logic and bus-interface functions, TI produces a new logic family
that designers of next-generation high-performance workstations, PCs, networking, and telecommunications equipment find
particularly useful.
AVC Family
TI’s next-generation logic family is AVC (see Figure 1). As part of TI’s Widebus and Widebus+ families, these devices
give designers an easy migration path to higher performance and lower voltages. Also offered in the AVC family are a broad
line of logic gates and octal bus-interface functions. The devices in TI’s AVC family are available in multiple JEDEC-standard
advanced packages to provide maximum flexibility in board layout and cost.
DOC, TI, Widebus, and Widebus+ are trademarks of Texas Instruments Incorporated.
1
64
LVT
ALVT
3.3 V
I OL – Drive Current – mA
2.5 V
24
ALB
ALVC
LVC
12
8
LV
AVC
5
10
15
20
Speed – Maximum tpd – ns
Figure 1. Low-Voltage Logic Family Performance Positioning
Unparalleled Performance
TI’s AVC family is the industry’s first logic family to achieve maximum propagation delays of less than 2 ns at 2.5 V. This
premier performance is achieved through a combination of advances. The family was designed for high performance,
incorporating several novel circuit structures and changes to conventional logic-circuit designs. TI’s advanced 0.5-micron
Enhanced-Performance Implanted CMOS (EPIC) fabrication process is used to produce the new devices.
Novel Output Structure
The AVC family features TI’s DOC circuit, which changes output impedance during switching (see Figure 2). The DOC circuit
allows a single device to have the desirable characteristics of reduced noise, similar to damping-resistor outputs during static
conditions, and high drive similar to a low-impedance output during dynamic conditions. The DOC circuit controls overshoots
and undershoots and limits noise, which are inherent in high-speed, high-current devices.
EPIC is a trademark of Texas Instruments Incorporated.
2
2.32
2.01
V O – Output Voltage – V
1.81
High Impedance
1.55
1.29
1.03
0.77
Low Impedance
0.52
0.25
0
High Impedance
20.7
21.4
22.1
22.8
23.5
24.2
24.9
25.6
26.3
Switching Time – ns
Figure 2. Impedance Changes Through Switching Transitions
Mixed-Voltage Mode and Power Off
The AVC family is optimized for low-power 2.5-V systems and effectively supports mixed-voltage systems because it is
compatible with 3.3-V and 1.8-V devices. AVC device inputs and outputs are 3.6-V tolerant at 2.5-V and 1.8-V VCC. This
provides a bidirectional data path between 3.3-V LVTTL and 2.5-V CMOS, and a one-way data path from 3.3-V LVTTL or
2.5-V CMOS to 1.8-V CMOS. AVC logic also has a power-off isolation feature that disables outputs from the device during
system partial power down.
Design Issues and AVC Family Solutions
Low Power (Optimized for 2.5 V)
Perhaps one of the most pervasive trends in advanced digital-electronics design is lower power consumption. Lower power
consumption is especially important to extend battery life of portable equipment. Reduced heat dissipation from lower power
consumption simplifies the measures necessary to remove heat and decrease the necessary packaging area, leading to
production of smaller and less expensive products. One of the most effective ways to reduce power dissipation is to decrease
integrated-circuit operating voltages. The AVC family, designed to operate at 2.5-V VCC, enables high-performance,
low-power, and advanced designs. Not simply a scaled-down 3.3-V family, AVC is the first logic family conceived and
designed for optimized performance at 2.5 V.
Unused and Undriven Inputs (Bus Hold)
A circuit element that must be addressed when designing with a CMOS family, such as AVC, is circuit inputs. With the
totem-pole structure (see Figure 3) that characterizes the inputs of CMOS devices, the input node must be held as close to the
VCC or GND rails as possible.
3
VCC
Qp
VI
Qn
Figure 3. Totem-Pole Input Structure
Precautions should be taken to prevent the input voltage from floating near the threshold voltage because this biases both input
transistors on and creates undesirably high ICC currents at the VCC pin of the device. Under certain conditions, this can damage
the device. One way to address this concern is to place external pullup resistors at any input that might be in a high-impedance,
undriven state. This is costly in terms of component count, reliability, and board area. An alternative solution is to employ the
devices in the AVC family that utilize the optional bus-hold circuit at the inputs (see Figure 4). AVC devices with bus-hold
circuitry are designated as AVCH.
Input
Inverter
Stage
I/O Pin
Bus-Hold
Input Cell
Figure 4. Typical Bus-Hold Cell
The bus-hold circuit consists of two series inverters with the output fed back to the input through a resistor. This provides a
weak positive feedback by sinking or sourcing current to the input node. The bus-hold cell holds the input at its last-known
valid logic state until forcibly changed by a driving circuit. Figure 5 shows the input characteristics of bus hold as the input
voltage is swept from 0 V to 2.5 V. These characteristics are similar to a weak bistable latch. The bus-hold cell sinks current
when the input is low, and sources current when the input is high. When the input voltage is near the threshold, the circuit sinks
or sources maximum current to force the input node toward either the VCC or GND rail.
4
VCC = 3.3 V
TJ = 40°C
Process = Nominal
0.15
VCC = 2.5 V
I I – Input Current – mA
0.10
VCC = 1.8 V
0.05
0
–0.05
–0.10
–0.15
–0.20
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VI – Input Voltage – V
Figure 5. Bus Hold Across VCC
Generally, pullup and pulldown resistors should not be used on the inputs of devices with bus hold. In applications that require
pullup or pulldown resistors to hold the inputs at a specific logic level, the II(hold) maximum specification should be considered.
The resistor value should be chosen to overcome bus hold under worst-case conditions. The resistor must supply enough
current so that the input is pulled through the threshold to the desired logic level. If the current supplied is too weak, the input
node could be held near the threshold, causing a high ICC that could damage the part.
Partial Power-Down and Mixed-Voltage-Mode Data Communication
The inputs and outputs of the AVC family have been designed with all reverse-current paths to VCC blocked. This low IOFF
current feature allows the device to remain electrically connected to a bus during partial power down without loading the
remaining live circuits. This feature also allows the use of this family in a mixed-voltage environment. If the inputs or outputs
are at a voltage greater than the VCC of the device, there is no current sourcing back through the device from the higher voltage
node to the lower-voltage VCC supply.
With a bidirectional AVC transceiver powered with 2.5-V VCC, two-way data communication between 3.3-V LVTTL devices
and 2.5-V CMOS devices can occur (see Figure 6). The inputs of the AVC part are 3.6-V tolerant and accept the LVTTL
switching levels. The outputs of the AVC part, when powered at 2.5-V VCC under worst-case conditions, are accepted as valid
switching levels at the input of a 3.3-V LVTTL device.
With a unidirectional AVC driver powered with 1.8-V VCC, data communication from 2.5-V or 3.3-V signal levels to 1.8-V
devices can occur (see Figure 7). The inputs of the AVC part are tolerant of the higher voltages and accept the higher switching
levels. The outputs of the AVC driver are valid 1.8-V signal levels.
5
2.5 V
VCC
3.3 V
VCC
2.4
2
1.5
VOH
VIH
Vt
0.8
VIL
0.7
Vt
VIL
0.4
0
VOL
GND
0.2
0
VOL
GND
VCC
VOH
VIH
2.5
2.3
1.7
3.3 V
AVC
2.5 V
1.2
Figure 6. Device at 2.5-V VCC With 3.3-V I/Os on One Side and 2.5-V I/Os on the Other,
Showing Switching Levels
1.8 V
VCC
3.3 V
VCC
2.4
2
1.5
VOH
VIH
Vt
0.8
VIL
0.7
Vt
VIL
0.4
0
VOL
GND
0.2
0
VOL
GND
2.5
2.3
1.7
1.2
VCC
VOH
VIH
2.5 V or 3.3 V
AVC
1.8 V
0.63
0.45
VCC
VOH
VIH
Vt
VIL
VOL
0
GND
1.8
1.35
1.17
0.9
Figure 7. Device at 1.8-V VCC With 2.5-V Inputs or 3.3-V Inputs, Showing Switching Levels
Device Characteristics
To facilitate a preliminary analysis of the characteristics of the AVC family, SPICE analysis graphs from TI’s initial
AVC-family device, the SN74AVC16245 16-bit bus transceiver with 3-state outputs are shown in Figures 8 through 22. These
analyses are the outputs of SPICE simulations using standard loads specified in the parameter measurement information
illustrations in Appendix A, unless otherwise noted.
Power Consumption
Figure 8 presents SPICE information about the device dynamic power consumption across the operating frequencies. Table 1
shows modeled values of power dissipation capacitance (Cpd). The Cpd data were obtained using an input edge rate of 1 ns
(0%–100%), open-circuit load on the output, and one output switching with a 48-pin TSSOP (DGG) package.
6
200
Process = Nominal
VCC = 2.5 V
TJ = 40°C
48-pin TSSOP (DGG) Package
180
I CC – Supply Current – mA
160
16 Outputs
Switching
140
120
8 Outputs
Switching
100
80
60
40
1 Output
Switching
20
29
48
67
86
105
124
143
162
181
Operating Frequency – MHz
Figure 8. ICC vs Frequency With 1, 8, or 16 Outputs Switching
Table 1. Cpd for Various Conditions, One Output Switching
PARAMETER
TEST CONDITIONS
CL = 0, f = 10 MHz
VCC = 1.8 V
± 0.15 V TYP
VCC = 2.5 V
± 0.2 V TYP
VCC = 3.3 V
± 0.3 V TYP
Cpd
Outputs enabled
15.9 pF
18.1 pF
21.1 pF
Cpd
Outputs disabled
∼1 pF
∼1 pF
∼1 pF
Input Characteristics
Figures 9 and 10 present SPICE information about the device static behavior. Figure 9 shows the device supply-current
requirements across input voltage and Figure 10 shows the output-voltage versus input-voltage transfer curves.
7
50
TJ = 40°C
Process = Nominal
45
40
I CC – Supply Current – mA
VCC = 3.3 V
35
30
25
20
15
VCC = 2.5 V
10
5
VCC = 1.8 V
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
2.4
2.7
3.0
VI – Input Voltage – V
Figure 9. ICC vs VI
3.2
TJ = 40°C
Process = Nominal
VCC = 3.3 V
2.8
V O – Output Voltage – V
2.4
VCC = 2.5 V
2.0
VCC = 1.8 V
1.6
1.2
0.8
0.4
0.3
0.6
0.9
1.2
1.5
1.8
VI – Input Voltage – V
Figure 10. VO vs VI
8
2.1
Switching Performance
Figures 11 through 16 present SPICE models of the device dynamic behavior. Propagation delay times across various
conditions of ambient temperature, load capacitance with one output switching, and load capacitance with 16 outputs switching
are shown.
1.28
1.26
t PHL – Propagation Delay Time – ns
VCC = 2.3 V
1.24
1.22
1.20
VCC = 2.5 V
1.18
1.16
1.14
VCC = 2.7 V
One Output Switching
Nominal Process
VCC = 2.5 V
RL = 500 Ω, CL = 30 pF
48-pin TSSOP (DGG) Package
1.12
1.10
–26
–12
2
16
30
44
TJ – Junction Temperature – °C
58
72
86
Figure 11. tPHL vs TJ
1.17
VCC = 2.3 V
t PLH – Propagation Delay Time – ns
1.14
1.11
1.08
VCC = 2.5 V
1.05
1.02
VCC = 2.7 V
One Output Switching
Nominal Process
VCC = 2.5 V
RL = 500 Ω, CL = 30 pF
48-pin TSSOP (DGG) Package
0.99
0.96
–26
–12
2
16
30
44
58
72
86
TJ – Junction Temperature – °C
Figure 12. tPLH vs TJ
9
t PHL – Propagation Delay Time – ns
2.4
2.2
Weak: VCC = 2.3 V, Weak Process, TJ = 100°C
Nominal: VCC = 2.5 V, Nominal Process, TJ = 40°C
Strong: VCC = 2.7 V, Strong Process, TJ = –40°C
RL = 500 Ω to GND
48-pin TSSOP (DGG) Package
2.0
1.8
Weak
1.6
Nominal
1.4
Strong
1.2
1.0
0.8
11
21
31
41
51
61
71
81
91
CL – Load Capacitance – pF
Figure 13. tPHL vs Load Capacitance, One Output Switching
t PLH – Propagation Delay Time – ns
3.0
2.7
Weak: VCC = 2.3 V, Weak Process, TJ = 100°C
Nominal: VCC = 2.5 V, Nominal Process, TJ = 40°C
Strong: VCC = 2.7 V, Strong Process, TJ = –40°C
RL = 500 Ω to GND
48-pin TSSOP (DGG) Package
2.4
2.1
Weak
1.8
1.5
Nominal
Strong
1.2
0.9
0.6
11
21
31
41
51
61
71
81
CL – Load Capacitance – pF
Figure 14. tPLH vs Load Capacitance, One Output Switching
10
91
t PHL – Propagation Delay Time – ns
2.6
2.4
2.2
Weak: VCC = 2.3 V, Weak Process, TJ = 100°C
Nominal: VCC = 2.5 V, Nominal Process, TJ = 40°C
Strong: VCC = 2.7 V, Strong Process, TJ = –40°C
RL = 500 Ω to GND
48-pin TSSOP (DGG) Package
2.0
Weak
1.8
Nominal
1.6
Strong
1.4
1.2
1.0
0.8
11
21
31
41
51
61
71
81
91
CL – Load Capacitance – pF
Figure 15. tPHL vs Load Capacitance, 16 Outputs Switching
t PLH – Propagation Delay Time – ns
3.2
2.8
Weak: VCC = 2.3 V, Weak Process, TJ = 100°C
Nominal: VCC = 2.5 V, Nominal Process, TJ = 40°C
Strong: VCC = 2.7 V, Strong Process, TJ = –40°C
RL = 500 Ω to GND
48-pin TSSOP (DGG) Package
2.4
Weak
2.0
Strong
Nominal
1.6
1.2
0.8
0.4
11
21
31
41
51
61
71
81
91
CL – Load Capacitance – pF
Figure 16. tPLH vs Load Capacitance, 16 Outputs Switching
11
Signal Integrity
Perhaps the most important measure of a device’s performance in the dynamic domain is the effect of varying conditions upon
signal integrity. Figures 17 through 20 show SPICE simulations of the device dynamic behavior. The effect of multiple outputs
switching simultaneously on one that is held at a valid logic level is shown (see Figures 17 and 18). The effects of slow
input-transition time (see Figure 19), and pin-to-pin skew (see Figure 20) are shown.
3.2
15 Outputs Switching
1 Quiet Low
Process = Nominal
TJ = 40°C
RL = 500 Ω
CL = 30 pF
VCC = 3.3 V
V O – Output Voltage – V
2.8
2.4
2.0
1.6
VCC = 2.5 V
1.2
0.8
VOLP at 2.5 V
VOLP at 3.3 V
VOLV Are Approximately Equal
0.4
0
41
43
42
44
45
46
47
48
49
Time – ns
Figure 17. Simultaneous-Switching Voltage (VOLP , VOLV) vs Time
3.2
VCC = 3.3 V
V O – Output Voltage – V
2.8
2.4
VCC = 2.5 V
2.0
1.6
1.2
15 Outputs Switching
1 Quiet High
Process = Nominal
TJ = 40°C
RL = 500 Ω
CL = 30 pF
0.8
0.4
0
19
20
21
22
23
24
25
26
27
28
29
Time – ns
Figure 18. Simultaneous-Switching Voltage (VOHP , VOHV) vs Time
12
2.4
VCC = 2.5 V
Process = Nominal
TJ = 40°C
RL = 500 Ω
CL = 30 pF
V O – Output Voltage – V
2.1
1.8
1.5
1.2
0.9
0.6
16 Outputs Switching
0.3
0
53
61
69
77
85
93
101
109
117
Time – ns
Figure 19. Slow Input-Transition Time
2.4
VCC = 2.5 V
Process = Nominal
TJ = 40°C
16 Outputs Switching
V O – Output Voltage – V
2.1
1.8
1.5
1.2
<100 ps Nominal
0.9
0.6
0.3
0
22
26
30
34
38
42
46
50
Time – ns
Figure 20. Pin-to-Pin Skew (tPHL, tPLH) (<100 ps nominal)
13
Output Characteristics With DOC
Selecting a component with improved output drive characteristics simplifies the design engineer’s job of ensuring signal
integrity and meeting timing requirements. For signal integrity, the output must have an output impedance that minimizes
overshoots and undershoots. A component with 26-Ω series damping resistors on the output ports was sometimes necessary
to improve the match of the impedance with the transmission-line load on the output of the buffer. The opposing characteristic
that must be considered is having sufficient drive to meet the timing requirements. The AVC family features TI’s DOC circuit
that automatically lowers the output impedance of the circuit during a signal transition and subsequently raises the impedance
to reduce overshoot and undershoot. Figures 21 and 22 contain typical voltage and current curves that illustrate the operation
of the circuit as it transitions from one state to another.
3.2
TJ = 40°C
Process = Nominal
V OL– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
VCC = 1.8 V
0.8
0.4
0
17
34
51
68
85
102
IOL – Output Current – mA
Figure 21. VOL vs IOL
14
119
136
153
170
2.8
TJ = 40°C
Process = Nominal
V OH – Output Voltage – V
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
–160
VCC = 1.8 V
–144
–128
–112
–96
–80
–64
–48
–32
–16
0
IOH – Output Current – mA
Figure 22. VOH vs IOH
The DOC circuitry provides enough drive current to achieve faster slew rates and meet timing requirements, but quickly
switches the impedance level to reduce the overshoot and undershoot noise that is often found in high-speed logic. This feature
of AVC logic eliminates the need for damping resistors in the output circuit, which are often used in series, and sometimes
integrated with logic devices, to limit electrical noise. Damping resistors reduce the noise, but increase propagation delay due
to the decreased drive current.
Because of the excellent signal integrity characteristics of the DOC output, transmission-line termination typically is
unnecessary. Due to the high-impedance drive characteristics of the output in the static state, the use of dc termination is
specifically discouraged. The output current that is required to bias a dc termination network could exceed the static-state
output-drive capabilities of the device. AVC with DOC circuitry is ideally suited for any high-speed, point-to-point application
or unterminated distributed load, such as high-speed memory interfacing.
Design Support
Examination of the characteristics of the device is a critical portion of a successful design. To aid the design engineer in analysis
of device characteristics, the latest versions of IBIS models can be obtained from TI’s website at http://www.ti.com. SPICE
models are also available from TI. Please contact your local TI field sales representative for more information.
15
Features and Benefits
Table 2 provides selected AVC family features and benefits.
Table 2. Selected AVC Family Features and Benefits
FEATURES
BENEFITS
Optimized for 2.5-V VCC
Enables low-power designs
Broad product offerings
Simplifies component choice
Advanced EPIC fabrication process; turbo-circuit design
Sub-2-ns (maximum) speeds at 2.5 V.
Easier to meet timing windows
in advanced high-speed designs
DOC outputs do not require series damping resistors internally or externally
Reduced ringing without series output resistors,
increased performance and cost savings
Bus-hold option
Eliminates pullup or pulldown resistors on inputs
IOFF – reverse-current paths to VCC blocked on the inputs and outputs
Outputs disabled during power off for use in
partial power down and mixed-voltage designs
Conclusion
For designs that require 1.8-V, 2.5-V, and 3.3-V logic functions with the highest performance, the AVC family provides the
fastest, quietest logic devices optimized for 2.5-V and unterminated load conditions. AVC offers a broad line of Widebus and
Widebus+ functions, logic gates, and octal bus-interface functions.
Acknowledgment
The authors of this application report are Stephen M. Nolan and Tim Ten Eyck.
16
Glossary
A
AVC
Advanced very-low-voltage CMOS
C
CMOS
Complementary metal-oxide semiconductor
D
DOC
Dynamic output control (patent pending)
E
EPIC
Enhanced-performance implanted CMOS
I
IBIS
I/O buffer information specification
II
Input current
II(hold)
Input current (bus hold)
IOH
High-level output current
IOL
Low-level output current
L
LVTTL
Low-voltage TTL (3.3-V power supply and interface levels)
P
PC
Personal computer
S
SPICE
Simulation program with integrated-circuit emphasis
17
T
tpd
Propagation delay time
tPHL
Propagation delay time, high- to low-level output
tPLH
Propagation delay time, low- to high-level output
TSSOP
Thin shrink small-outline package
TTL
Transistor-transistor logic
V
VOH
High-level output voltage
VOL
Low-level output voltage
VOHP
High-level output voltage peak
VOHV
High-level output voltage valley
VOLP
Low-level output voltage peak
VOLV
Low-level output voltage valley
18
Appendix A – Parameter Measurement Information
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure A–1. AVC Parameter Measurement Information (1.8 V ± 0.15 V)
A–1
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure A–2. AVC Parameter Measurement Information (VCC = 2.5 V ± 0.2 V)
A–2
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC
Timing
Input
VCC/2
VCC/2
0V
0V
tsu
Data
Input
VCC/2
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
Output
Control
(low-level
enabling)
VCC/2
VCC/2
0V
tPLZ
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
VOH – 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure A–3. AVC Parameter Measurement Information (VCC = 3.3 V ± 0.3 V)
A–3
A–4