Download Noise Modeling - Design Automation Laboratory

EE 201A
Noise Modeling
Jeff Wong and Dan Vasquez
Electrical Engineering Department
University of California, Los Angeles
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Efficient Coupled Noise Estimation
for On-Chip Interconnects
Anirudh Devgan
Austin Research Laboratory
IBM Research Division, Austin TX
MEMS Research Laboratory
Joe Zendejas and Jack W. Judy
Motivation
• Noise failure can be more severe than
timing failure
– Difficult to control from chip terminals
– Expensive to correct (refabrication)
• Circuit or timing simulation (like SPICE)
can be used
– Linear reduction techniques can be applied for
linearly modeled circuits
• i.e. moment matching methods
– Inefficient for noise verification and avoidance
applications
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Noise Estimation
• The paper presents an electrical metric for
efficiently estimating coupled noise for
on-chip interconnects
• Capacitive coupling between an aggressor
net and a victim net leads to coupled
noise
– Aggressor net: switches states; source of
noise for victim net
– Victim net: maintains present state; affected by
coupled noise from aggressor net
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Circuit Schematic
Coupling
capacitors
CC = [CC,ii]
V2,1
V2,n
C2 = [C2,ii]
V1,1
V1,n
Switching
signal
Vs(t)
C1 = [C1,ii]
• Let’s analyze the case for one aggressor
net and one victim net
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Circuit Equations
• Coupled equation for circuit:
CC   dtd v1  t    A11
d


C2   dt v2  t    A21
A12   v1  t    B1 

    vs  t 

A22  v2  t    B2 
• In Laplace domain:
 C1 CC   sV1  s    A11


C

 C C2   sV2  s    A21
A12  V1  s    B1 

    Vs  s 

A22  V2  s    B2 
 C1
C
 C
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Circuit Equations
• Aggressor net:
sC1V1  sCCV2  A11V1  A12V2  BV
1 s

 V1   sC1  A11   A12  sCC V2  BV
1 s
1
• Victim net:
sCCV1  sC2V2  A21V1  A22V2  B2Vs
 V2   sC2  A22   A21  sCC V1  B2Vs 
1
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Transfer Function
• Transfer function:
1
A21  sCC  sC1  A11  B1  B2

V2
H s  
Vs  sC2  A22    A21  sCC  sC1  A11 1  A12  sCC 
• Simplifications (details later):
A12  0, A21  0, B2  0
• Simplified transfer function:
1
 sCC  sC1  A11  B1
V2
H s  
Vs  sC2  A22    sCC 2  sC1  A11 1
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Simplifications
• A12 = 0
– No resistive (or DC) path exists from the
aggressor net to the victim net
• A21 = 0
– No resistive (or DC) path exists from the victim
net to the aggressor net
• B2 = 0
– No resistive (or DC) path exists from the
voltage/noise source to the victim net
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Maximum Induced Noise
• H(s=0) = 0
– Coupling between aggressor and victim
net is purely capacitive
– Maximum induced noise can be
computed
• Assume Vs is a finite or infinite ramp
– lim  dtd V2   0  V2max is finite
t 
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Maximum Induced Noise
• Final value theorem:
v2  t   lim  sV2  s  
– V2max  lim
t 
s 0
• Ramp input u(s):
– V2max  lim sH  s  u  s   lim sH  s  u2
s 0
s 0
– V2max  lim
s 0
s
1
CC  sC1  A11  B1
 lim
s 0
 sC2  A22    sCC   sC1  A11 
2
H s
1
s
u
u
– V2max   A221CC A111B1u
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Circuit Interpretation
V1ss
max
2
V
1
22

1
11 1

 A CC  A B u
IC
EE 201A Modeling and Optimization for VLSI Layout
Switching
slope
Jeff Wong and Dan Vasquez
Circuit Computations
(matrix method)
1
11 1
• Step 1: Compute V   A B u
ss
1
– Requires circuit analysis of the
aggressor net
• Step 2: Compute IC  C V
ss
C 1
– Requires a matrix multiplication
• Step 3: Compute V
max
2
1
22 C
A I
– Requires circuit analysis of the victim
net
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Circuit Computations
(by inspection)
1
11 1
• Step 1: Compute V   A B u
ss
1
– Aggressor circuit transformation:
• Replace input source with it’s derivative
• Replace aggressor net’s capacitors with
open circuits
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Circuit Computations
(by inspection)
1
11 1
• Step 1: Compute V   A B u
ss
1
– Typical interconnects:
• Negligible loss: no resistive path to ground
•
V  Vs
ss
1
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Circuit Computations
(by inspection)
• Step 2: Compute I C  CCV1ss
– Convert steady state derivative on the
aggressor net to a current on the victim
net
– IC   Ii    CC ,ijV1ssj 

j

– i : index of node on the victim net
– j : index of node on the aggressor net
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Circuit Computations
(by inspection)
• Step 3: Compute N
max
V
max
2
1
22 C
A I
– Victim circuit transformation:
• Replace capacitors with coupling currents
• The voltage at each node corresponds to
that node’s maximum induced noise
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Circuit Computations
(by inspection)
• Step 3: Compute N
max
V
max
2
1
22 C
A I
– Typical interconnects:
• Compute by inspection in linear time
max
C
• V
 Vi
max


max
   Ri  I j  N i 1 
 Li

EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Circuit Computations
(by inspection)
• Step 3: Compute N
max
V
max
2
1
22 C
A I
– 3RC Circuit example:
Nimax  Ri  I j  Nimax
1
Li
N1max  R1  I1  I 2  I3 
N2max  R1  I1  I 2  I3   R2 I 2
N1max  R1  I1  I 2  I3   R3 I3
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Computation Costs
• Step 1: V1ss  Vs
– No computation required
• Step 2:
I i   CC ,ijV1ssj
j
– Simple multiplications
• Step 3:
Nimax  Ri  I j  Nimax
1
Li
– Simple multiplications
• Multiple aggressor nets:
– Coupling currents from step 2
determined from a linear superposition
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Experiment
• Typical small RC interconnect
structure
– Rise time of 200 ps or 100 ps
– Power supply voltage of 1.8 V
– Conventional circuit simulation vs.
proposed metric
– Run-time comparisons for various
circuit sizes
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Accuracy Results
Node Circuit Simulation Proposed Metric
1
0.0084
0.0084
2
0.016
0.016
3
0.0227
0.0227
4
0.0286
0.0286
5
0.0336
0.0336
6
0.0378
0.0379
7
0.0412
0.0412
8
0.0437
0.0438
9
0.0454
0.0454
10
0.0462
0.0463
% Error
0.00%
0.00%
0.00%
0.00%
0.00%
0.26%
0.00%
0.23%
0.00%
0.22%
• 10 nodes, 200 ps rise time
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Accuracy Results
Node Circuit Simulation Proposed Metric
1
0.0147
0.0168
2
0.0277
0.0319
3
0.0392
0.0454
4
0.0492
0.0572
5
0.0578
0.0673
6
0.0651
0.0757
7
0.0709
0.0824
8
0.0752
0.0875
9
0.0782
0.0908
10
0.0797
0.0925
% Error
7.73%
13.10%
13.65%
13.98%
14.11%
14.00%
13.95%
14.05%
13.87%
13.83%
• 10 nodes, 100 ps rise time
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Accuracy Results
• Metric accuracy degrades with reduction
in rise times
• Metric estimation is more conservative
than circuit model’s
– Fast rise times don’t allow circuit to reach
ramp steady state noise
• Loading of interconnect normally does not
allow for very small rise times
– Metric accuracy should be acceptable for
many applications
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Run-time Results
Circuit
Number
Number of
Elements
1
2
3
4
500
5,000
50,000
500,000
Arnoldi Model Proposed
Reduction Metric (Matrix
Method)
.2s
5.86s
145s
-
.00s
.07s
3.44s
360.55s
Proposed
Metric (By
Inspection)
.00s
.01s
.05s
.35s
• Arnoldi-based model reduction used a
matrix solution to compute circuit
response
– Requires repeated factorizations, eigenvalue
calculations, and time exponential evaluations
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Conclusions
• The proposed metric determines an
upper bound on coupled noise for
RC and over-damped RLC
interconnects
– Metric becomes less accurate as rise
time decreases
• The proposed metric is much more
run-time efficient than circuit
modeling methods
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Improved Crosstalk Modeling for Noise
Constrained Interconnect Optimization
Jason Cong, David Zhigang Pan &
Prasanna V. Srinivas
Department of Computer Science, UCLA
Magma Design Automation, Inc.
2 Results Way, Cupertino, CA 95014
MEMS Research Laboratory
Joe Zendejas and Jack W. Judy
Motivation
• Deep sub-micron net designs have higher
aspect ratio (h/w)
– Increased coupling capacitance between nets
• Longer propagation delay
• Increased logic errors --- Noise
• Reduced noise margins
– Lower supply voltages
– Dynamic Logic
• Crosstalk cannot be ignored
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Aggressor / Victim Network
Aggressor
Victim
• Assuming idle victim net
– Ls: Interconnect length before coupling
– Lc: Interconnect length of coupling
– Le: Interconnect length after coupling
• Aggressor has clock slew tr
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
2- Model
• Victim net is modeled as 2 -RC circuits
• Rd: Victim drive resistance
• Cx is assumed to be in middle of Lc
Rise time
victim / aggressor
coupling capacitance
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
2- Model Parameters
Aggressor
Victim
C1 
Cs
2
C2 
C s  Ce
2
EE 201A Modeling and Optimization for VLSI Layout
CL 
Ce
 Cl
2
Jeff Wong and Dan Vasquez
Analytical Solution
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Analytical Solution part 2
• s-domain output voltage
• Transform function H(s)
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Analytical Solution part 3
• Aggressor input signal
• Output voltage
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Simplification of Closed Form Solution
• Closed form solution complicated
• Non-intuitive
– Noise peak amplitude, noise width?
• Dominant-pole simplification
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Dominant-Pole Simplification
RC delay from upstream resistance of coupling element
Elmore delay of victim net
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Intuition of Dominant Pole Simplification
• vout rises until tr and
decays after
• vmax evaluated at tr
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Extension to RC Trees
• Similar to previous model with addition of
lumped capacitances
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Results
• Average errors of 4%
• 95% of nets have errors less than 10%
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Spice Comparison
peak noise
EE 201A Modeling and Optimization for VLSI Layout
noise width
Jeff Wong and Dan Vasquez
Effect of Aggressor Location
• As aggressor is moved close to receiver,
peak noise is increased
Ls varies from 0 to 1mm
Lc has length of 1mm
Le varies from 1mm to 0
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Optimization Rules
• Rule 1:
– If RsC1 < ReCL
• Sizing up victim driver will reduce peak
noise
– If RsC1 > ReCL and tr << tv
• Driver sizing will not reduce peak noise
• Rule 2:
– Noise-sensitive victims should avoid
near-receiver coupling
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Optimization Rules part 2
• Rule 3:
– Preferred position for shield insertion is near a
noise sensitive receiver
• Rule 4:
– Wire spacing is an effective way to reduce
noise
• Rule 5:
– Noise amplitude-width product has lower
bound
– And upper bound
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
Conclusions
• 2- model achieves results within
6% error of HSPICE simulation
• Dominant node simplification gives
intuition to important parameters
• Design rules established to reduce
noise
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez
References
• Anirudh Devgan, “Efficient Coupled Noise
Estimation for On-chip Interconnects”, ICCAD,
1997.
• J. Cong, Z. Pan and P. V. Srinivas, “Improved
Crosstalk Modeling for Noise Constrained
Interconnect Optimization”, Proc. Asia South
Pacific Design Automation Conference
(ASPDAC), Jan. 30 - Feb. 2, 2001, Pacifico
Yokohama, Japan.
EE 201A Modeling and Optimization for VLSI Layout
Jeff Wong and Dan Vasquez