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Transcript
Integrated Circuit Devices
Professor Ali Javey
Summer 2009
MOS Capacitors
Reading: Chapter 16
MOS Capacitors
MOS: Metal-Oxide-Semiconductor
Vg
Vg
gate
metal
gate
SiO 2
SiO 2
N+
N+
P-body
Si body
MOS transistor
MOS capacitor
EE143 – Ali Javey
Ideal MOS Capacitor
– Oxide has zero charge, and no current can pass through it.
– No charge centers are present in the oxide or at the oxidesemiconductor interface.
– Semiconductor is uniformly doped
– M = S =  + (EC – EF)FB
Ideal MOS Capacitor
At Equilibrium:
Ideal MOS Capacitor
Under Bias
– Let us ground the semiconductor and start applying
different voltages, VG, to the gate
– VG can be positive, negative or zero with respect to the
semiconductor
– EF,metal – EF,semiconductor = – q VG
– Since oxide has no charge (it’s an insulator with no
available carriers or dopants), d Eoxide / dx = / = 0;
meaning that the E-field inside the oxide is constant.
Inversion condition
If we continue to increase the positive gate voltage, the bands
at the semiconductor bends more strongly. At sufficiently high
voltage, Ei can be below EF indicating large concentration of
electrons in the conduction band.
We say the material near the surface is “inverted”. The
“inverted” layer is not gotten by chemical doping, but by
applying E-field. Where did we get the electrons from?
When Ei(surface) – Ei(bulk) = 2 [EF – Ei(bulk)], the condition is
start of “inversion”, and the voltage VG applied to gate is called
VT (threshold voltage). For VG > VT, the Si surface is inverted.
Ideal MOS
Capacitor –
n-type Si
Electrostatic potential, (x)
Define a new term, (x) taken to be the potential inside the semiconductor at
a given point x. [The symbol  instead of V used in MOS work to avoid
confusion with externally applied voltage, V]
1
( x)  [ Ei (bulk)  Ei ( x)]
q
Potential at any point x
1
S  [ Ei (bulk)  Ei (surface)]
q
Surface potential
1
F  [ Ei (bulk)  EF ]
q
F > 0 means p-type
| F | related to doping
concentration
F < 0 means n-type
Electrostatic potential
S is positive if the
bands bend\ …….?
S = 2F at the
depletion-inversion
transition point
(threshold voltage)
Charge Density - Accumulation
MO
p-type silicon
accumulation condition V < 0
G
The accumulation charges in the
semiconductor are ……. , and appear
close to the surface and fall-off
rapidly as x increases.
One can assume that the free carrier
concentration at the oxide-semiconductor
interface is a -function.
S
p-Si
Accumulation of holes
x
Charge on metal = QM
Charge on semiconductor =  (charge on metal)
|QAccumulation| = |QM|
Charge Density - Depletion
p-type Si,
depletion condition
The depletion charges in Si are
immobile ions - results in depletion
layer similar to that in pn
VG > 0
junction or Schottky diode.
|q NA A W| = |QM|
()
(+)
If surface potential is s, then the
depletion layer width W will be
2 Si
W
S
qN A
QM
MO
S
p-Si
w
Depletion of
holes
Charge Density - Inversion
MO
p-type Si,
strong inversion
S
p-Si
VG>>0
Once inversion charges
appear, they remain close to the
surface since they are
…….. Any additional voltage to the
gate results in extra QM in gate and
get compensated by extra inversion
electrons in
semiconductor.
QM
w
Depletion of
holes
Inversion electrons:
-function-like
So, the depletion width does not change during inversion. Electrons appear as function near the surface. Maximum depletion layer width W = WT
MOS C-V characteristics
•The measured MOS capacitance (called gate capacitance)
varies with the applied gate voltage
– A very powerful diagnostic tool for identifying
threshold voltage, oxide thickness, substrate doping
concentration, and flat band voltage.
– It also tells you how close to an ideal MOSC your
structure is.
•Measurement of C-V characteristics
– Apply any dc bias, and superimpose a small (15 mV) ac
signal (typically 1 kHz – 1 MHz)
C-V: under accumulation
MO
Consider p-type Si under
accumulation.
VG < 0.
Looks similar to parallel
plate capacitor.
S
p-Si
VG < 0
Accumulation of holes
CG = Cox
where Cox = (ox A) / xox
x
CG is constant as a function of VG
C-V: under depletion
MO
Depletion condition:
VG > 0
S
p-type Si
VG > 0
CG is Cox in series with Cs
where Cs can be defined as
“semiconductor capacitance”
QM
W
Co
Cs
x
Cox=ox A / xox
Cs = Si A / W
CG = Cox Cs / (Cox + CS)
2Si
W
s
qN A
where s is surface potential
CG decreases with increasing VG
Depletion of
holes
C-V: under inversion (high frequency)
VG = VT and VG > VT
Inversion condition s = 2 F
W  WT 
2 Si
2F
q NA
At high frequency, inversion
electrons are not able to respond
to ac voltage.
MO
S
p-Si
VG >>0
QM
W
Depletion of
holes
Cox= ox A / xox
Cs = Si A / WT
CG ( ) = Cox Cs / (Cox + CS)
Inversion electrons
- function
Co
x
CG will be constant for VG  VT
Cs
C-V: under inversion (low frequency)
At low frequency, the inversion electrons will be able to respond to the ac
voltage. So, the gate capacitance will be equal to the “oxide capacitance”
(similar to a parallel plate capacitance).
CG (  0) = Cox
= ox A / xox
Cox
C
low frequency
high frequency
accumulation Vfb depletion Vt inversion
Ideal MOSC (p-type Si)
CG increases for VG  VT until it reaches Cox
Vg