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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 5, NO. 5, SEPTEMBER 2006
Increased Logic Functionality of Clocked
Series-Connected RTDS
María J. Avedillo, José M. Quintana, and Héctor Pettenghi Roldán
Abstract—The augmentation of transistor technologies with
resonant tunnelling diodes (RTDs) has demonstrated improved
circuit performance. The negative differential resistance exhibited
by these devices can be exploited to increase the functionality
implemented by a single gate in comparison to transistor-only
technologies. Complex threshold gates (TGs) are efficiently realized by resorting to the operation principle of the clocked series
connection of a pair of RTDs (MOBILE). This paper focuses the
implementation of logic blocks using RTDs and transistors which
further increase the functionality of previously reported topologies. Multithreshold–threshold gates (MTTGs) is the logic concept
underlying the proposed realizations. The MOBILE principle
is extended to three or more RTDs in series which allows us to
implement MTTGs. Novel and extremely compact realizations of
programmable gates using the MTTG topology are presented. A
number of logic blocks useful for digital design are shown and
their operation is verified through simulation with extensively
validated models for actual devices.
Index Terms—Logic circuits, MOnostable-BIstable Logic Element (MOBILE), resonant tunnel diode (RTD), threshold gate.
I. INTRODUCTION
ESONANT tunnelling diodes (RTDs) are very fast nonlinear circuit elements which have been integrated with
transistors to create novel quantum devices and circuits. This
incorporation of tunnel diodes into transistor technologies has
demonstrated improved circuit performance: higher circuit
speed, reduced component count, and/or lowered power consumption [1]–[5]. Most of the reported working circuits have
been fabricated in III/V materials while Si-based tunnelling
diodes compatible to standard CMOS fabs are currently an
area of active research [6]. In fact, it has been claimed that
augmenting CMOS with RTDs could be the way to extend
the lifetime of CMOS and fully exploit its huge economical
investments [7]. Thus, the research on circuit topologies using
RTDs and transistors is of critical importance for these emergent technologies. This paper focuses on the implementation
of complex RTD-based logic blocks which further increase the
functionality of previously reported topologies.
R
Manuscript received May 12, 2006. The review of this paper was arranged by
Associate Editor W. Porod. This work was supported by the Spanish Government under Project TEC2004-02948/MIC.
M. J. Avedillo and J. M. Quintana are with the Instituto de Microelectrónica
de Sevilla, Centro Nacional de Microelectrónica, Spain. They are also with the
Departamento de Electrónica de Sevilla, University of Sevilla, Spain (e-mail:
[email protected]; [email protected]).
H. Pettenghi Roldán is with the Instituto de Microelectrónica de Sevilla,
Centro Nacional de Microelectrónica, Spain (e-mail: [email protected]).
Digital Object Identifier 10.1109/TNANO.2006.880889
Fig. 1. (a) RTD symbol and I–V characteristic. (b) Basic MOBILE.
RTDs exhibit a negative differential resistance (NDR) region
in their current–voltage characteristics which can be exploited to
significantly increase the functionality implemented by a single
gate in comparison to conventional MOS and bipolar technologies, thus reducing circuit complexity. Fig. 1(a) depicts the circuit symbol used for RTDs and their typical I–V curve showing
key parameters for circuit design: peak current and voltage,
and , and valley current and voltage, and . Many RTDbased logic blocks rely on utilizing the latching property of
the clocked series connection of a pair of RTDs (MOBILE)
[8] arising from their NDR characteristic. In general, MOBILE
logic families combine the basic pair of series-connected RTDs
with different three-terminal devices to achieve input–output
isolation and functionality. The operating principle of MOBILE
is extremely well suited to implement the arithmetic operation
on which threshold gates1 (TGs) are based [9]. MOBILE TGs
have been experimentally demonstrated [12], [13].
A series connection of RTDs has been also employed to implement more complex gates than TGs. In particular, a two-input
EXOR gate using three RTDs connected in series has been reported [14]. An EXOR gate is, in fact, a multithreshold–threshold
gate2 (MTTG).
In [16], we established the conceptual link between the
MTTG concept and the series connection of RTDs by designing
1A
threshold gate is defined as a logic gate with n binary input variables, x ,
(i = 1; . . . ; n), one binary output y , and for which there is a set of (n + 1) real
numbers: threshold T and weights w ; w ; . . . ; w , such that its input–output
relationship is defined as y = 1 if f
w x
T and y = 0, otherwise.
Conventional boolean gates AND, OR, NAND, and NOR are threshold gates. See
[10] and [11].
2Multithreshold–threshold gates are a generalization of the conventional TGs
in which k thresholds (k = 1; 2; . . .) rather than the usual single threshold are
used; see [15].
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AVEDILLO et al.: INCREASED LOGIC FUNCTIONALITY OF CLOCKED SERIES-CONNECTED RTDS
607
a MOBILE-based implementation of the Boolean function
which is not a TG but an MTTG.
This link is further explored in this paper in order to take full
advantage of the functionality that can be implemented with
this kind of circuits. We describe circuit structures implementing complex logic blocks including gates which can be
programmed to implement different functions. The proposed
novel circuit structures are validated through extensive simulations carried out using experimentally validated HSPICE
models for InP-based RTD and HFET devices for fabricated
devices.
The rest of the paper is organized as follows. In Section II,
the operation principle of clocked series-connected RTDs
as well as previously reported circuit structures working on
its basis are described with special emphasis on the MTTG
topology. Section III explores the functional capabilities of the
circuit topology implementing MTTGs and describes several
case study circuits. Section IV focuses on the application of the
MTTG topology to the design of programmable gates. Finally,
Section V gives some conclusions.
II. BACKGROUND
A number of high-speed logic circuit applications of RTDs
based on the MOnostable-BIstable Logic Element (MOBILE)
[8] have been reported [2], [4], [9], [12], [17], [18]. The MOBILE [Fig. 1(b)] is a rising edge-triggered current controlled
gate which consists of two RTDs connected in series and driven
. When
is low, both
by a switching bias voltage
RTDs are in the on-state (or low resistance state) and the cirto an appropriate maximum
cuit is monostable. Increasing
value ensures that only the device with the lowest peak current switches (quenches) from the on-state to the off-state (the
high resistance state). Output is high if the driver RTD is the
one which switches and it is low if the load switches. Assuming
equal current densities for both RTDs, peak currents are proportional to RTD areas, that is, the smallest RTD switches. Logic
functionality is achieved by embedding an input stage which
modifies the peak current of one of the RTDs. In the configuration for an inverter MOBILE shown in Fig. 2(a), the peak current of the driver NDR can be modulated using the external input
. During a critical period when
rises, the voltage
signal
goes to one of the two stable states (low
at the output node
or high), corresponding to “0” and “1” in binary logic. RTDs’
peak currents and current through input stage are selected such
that the value of the output depends on whether the external
is “1” or “0,” since this determines (through
input signal
current modulation) which NDR device has the lowest current.
high, the output node maintains its value even if the
For
input changes. That is, this circuit structure is self-latching, allowing us to implement pipeline at the gate level without any
area overhead associated to the addition of the latches, which
allows very high throughput. Very recently, a CAD algorithm to
synthesize nanopipelined networks has been developed [19].
A number of MOBILE-based logic families have been proposed which differ in the input stage used. Both HFET and
HBT transistors have been cointegrated with RTDs to implement them. Two reported input stages are depicted in Fig. 2.
Fig. 2(a) depicts the original inverter MOBILE from [17]. An
Fig. 2. MOBILE circuits. (a) Inverter with transistor as input stage,
(b) inverter with RTD-transistor as input stage, and (c) TG defined by
[w ; w ; w ; w ; T ] .
0
0
HEMT transistor is placed in parallel to the driver RTD. This
parallel combination behaves like a voltage-controlled RTD. In
Fig. 2(b), an alternative topology for the MOBILE inverter proposed in [12] is shown. The transistor has been substituted by
the series combination of an RTD with a transistor. The transistor is sized such that it behaves like a switch that is, but it
does not limit the current flowing through the RTD when a high
voltage is applied to its gate. In this way, the circuit is less sensitive to transistor parameter variations and the design is simplified since it reduces to determine RTD areas in order to obtain
the required relationship between the peak currents of the driver
and load NDRs.
The circuit topologies in Fig. 2(a) and (b) have been extended
to systematically implement threshold gates. Fig. 2(c) shows the
RTD/HFET implementation of a generic TG defined as
, and 0, otherwise.3 [12]
The RTD areas determine the weights ,
and
the threshold . Input stages controlled by external inputs are
placed in parallel to RTD or RTD , depending on whether the
associated weight is positive or negative, allowing the control of
the peak currents of both NDRs.
The concept of RTD-based MOBILE can be extended to a circuit consisting of three or more RTDs in series. The switching
sequence in series-connected RTDs begins also with the RTD
with the smallest peak current. Thus, controlling the peak currents by external inputs, this sequence can be varied and functionality can be obtained at the output node. Multiple-valued
3Such a
1; . . . ; 4).
threshold gate is denoted by [w
;w ;
0
w ;
0
w
; T ], w
>
0, (i =
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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 5, NO. 5, SEPTEMBER 2006
Fig. 3. Proposed circuit topology for generic MTTG defined by
[w ; w ; w ; T ; T ] .
circuits, such as literals and quantizers, have been implemented
on this basis by selecting a maximum voltage level for the bias
which allows the switching of multiple RTDs [20], [21].
Fig. 3 depicts the circuit topology we have proposed [16]
for a generic three-input two-threshold MTTG defined as
, and 0, otherwise.4
The specific function implemented by such a circuit depends on
the areas of the RTDs. For each input combination, the effecfor NDR ,
tive areas for each NDR are:
for NDR , and
for
. For each input combination the NDR
NDR with
with the smallest effective area switches. Areas are chosen so
that NDR is the smallest one for input combinations satisfying
(and thus a logic “0” is obtained
at the output), NDR is the smallest one for those input combi(and thus
nations satisfying
a logic “1” is obtained at the output), and NDR is the smallest
(and thus a logic “0” is
one for
,
obtained at the output). Note that the relationship among
, and
,
determines the weights.
III. LOGIC FUNCTIONALITY IMPLEMENTABLE
WITH MTTG TOPOLOGY
This section explores the functional capabilities of the MTTG
topology. Additionally, the validity of the MTTG approach has
been asserted by the design of a logic block which simultaneously implements two functions on its basis.
The proposed topology can implement any threshold function
as well as any two-threshold multiple threshold function with
positive weights. We have evaluated how many distinct two- and
three-input functions are implementable with the new circuit
structure.
4Such
an MTTG is denoted by [w
(i = 1; . . . ; 3).
;w ;w
;T
;T
],
w
>
0,
For two-input functions, the only functionality which cannot
be implemented with the proposed topology is the EXNOR.
EXNOR cannot be realized in node
since in order to produce
a low output for input combinations
or , NDR
should be quenched; that is, it should have the smallest peak
current for those input combinations. Clearly, if this holds,
NDR would be also the quenched RTD for the input combination
since NDR would exhibit the smallest peak
current. That means a logic zero is produced for input combination 11, while a logic one is required for the EXNOR function.
It cannot be realized in node . In this case, the low-voltage
output corresponding to input combinations 01 or 10 could be
achieved quenching NDR or NDR . The first option would
also produce a logic zero for input combination 11. The second
one is not possible either since it requires NDR to have the
smallest peak current for input combinations 00 and 11 but not
for 01 and 10, which is not consistent with circuit structure.
For three input variables, 143 functions can be implemented
with the MTTG circuit structure with three series-connected
RTDs. This means there are 39 more functions than with a
TG structure with two series-connected RTDs. Clearly, the
MTTG topology described can be generalized in order to
realize functions with a larger number of thresholds. This
requires connecting more NDR devices in series. In particular,
three-threshold MTTGs are realizable with four RTDs in series
and allow us to implement the 16 two-input functions and 213
out of the 256 of three inputs.
The logic functionality of the MTTG topology in Fig. 3 can be
further increased by taking advantage of the fact that with three
RTDs there are two nodes which can be used to simultaneously
implement different logic functions. Using this improvement a
useful building block for digital design which simultaneously
implements a two-input EXOR and a two-input NAND has been
designed. We have called it a two-input universal logic block
since any two-input function can be implemented by a single
such block and inverters. In addition, such a block has been used
in the design of ripple carry adders [23]. Fig. 4(a) shows the
circuit schematic for the proposed block. The associated table
depicts which NDR stage quenches for each input combination
and the voltage levels in each of the output nodes. As it can be
easily seen, node implements the EXOR function, while node
implements the NAND function.
The design of a universal block has been carried out in a
noncommercial university InP technology in which RTD and
is 0.21 V,
transistors can be cointegrated. For this RTD,
the peak current density 21 KA/cm , the peak-to-valley current
ratio is about 6.25 at room temperature, and the capacitance is
4 fF/ mm . The transistor is a depletion HFET with threshold
voltage 0.2 V and minimum gate-length 0.7 m. The unit
has been selected as 2 m . The design has been verarea
ified with HSPICE, using models experimentally validated and
which were supplied by the foundry. The RTD is modelled by
the parallel connection of a capacitance and a voltage-controlled
current source representing the nonlinear dc RTD current, in series with two resistances. For the voltage-controlled current, an
expression made up of exponential functions and developed to
fit the actual NDR characteristic of fabricated RTDs is used. The
RTD capacitor is constant and its value is proportional to the
AVEDILLO et al.: INCREASED LOGIC FUNCTIONALITY OF CLOCKED SERIES-CONNECTED RTDS
609
Fig. 5. Generic topology for n-input programmable gate.
TABLE I
EXAMPLES OF DESIGNED PROGRAMMABLE GATES
Fig. 4. Two-input universal block. (a) Circuit and functionality. (b) Monte
Carlo simulation results.
RTD area. The transistor is modelled using the HSPICE level 3
JFET model. Transistor capacitors are modelled as diode-like
capacitances. To evaluate robustness, we have run 30 Monte
Carlo simulations of the circuit with each output loaded with
four MOBILE inverters. The analysis has been carried out assigning Gaussian distributions with a relative variation of 10%
to the most relevant device and circuit parameters: bias
at
voltage, current density, peak voltage, area of each of the RTDs,
and threshold voltage of transistors. Fig. 4(b) plots the obtained
for
waveforms. Traces depict the clocked supply signals,
the universal block and
for the inverters in the second
and , outputs of the universal block
and
stage, inputs,
, and outputs of the inverters driven by the universal block
and . Low and high voltage values for bias signals are 0 and
0.75 V, respectively. Note that there are four phases in the operation of MOBILE gates: evaluation (clocked bias rises), hold
(clocked bias high), reset (clocked bias falls), and wait (clocked
by
bias low) and that Vbias_2 is delayed with respect to
with as the bias period. The input combination processed
pulse is indicated. Correct operation is observed
by each
for every input combination.
In order to carry out a comparison with previously reported
MOBILE based gates, the functionality implemented by the universal block, i.e., the two-input EXOR and NAND functions, has
been realized using threshold gates with the topology in Fig. 2(c)
from [12]. Note than since the EXOR is not a threshold function,
a network of threshold gates is required to realize it. Both designs, the proposed MTTG and the network of TGs, have been
simulated using the same technology and with identical loads
(four MOBILE inverters). Maximum operating speed is slightly
higher in the network of TGs (minimum rise time for clocked
bias signal 70 ps) than in the MTTG (minimum rise time 90 ps).
However, the latency is 35% smaller in the MTTG (90 ps, one
stage to evaluate) than in the TG network (140 ps, two stages
to evaluate EXOR). In addition, the MTTG solution requires significantly less devices than the TG network. The MTTG comprises seven RTDs and five transistors and the TG network is
19 RTDs and nine transistors. Also, the power consumption is
significantly smaller in the MTTG which consumes one-third of
the power consumed by the TG network.
IV. PROGRAMMABLE GATES
It is worthwhile to explore the implementation of programmable gates on the basis of the MTTG circuit topology
since, as it was shown in the previous section, it implements
many different functions just changing RTDs’ areas. The idea
is controlling the effective areas of the RTDs not associated
with functional inputs. This is done by adding control branches
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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 5, NO. 5, SEPTEMBER 2006
presented. The employed circuit topologies extend even more
the functionality of the structures based on the MOBILE principle and allow us to systematize the efficient design of complex
functions with RTDs on the basis of the MTTG concept. Simulation results show significant advantages in terms of latency,
device count, and power consumption of the MTTGs with respect to TGs. Interesting programmable gate realizations have
been described.
REFERENCES
Fig. 6. Two-input two-control programmable gate realizing four functions.
(a) Circuit topology. (b) Simulation results.
consisting of the series connection of an RTD and a transistor
driven by a control input. In this way, the RTD areas are
modified by the control inputs. That is, the function implemented is selected by the values applied to the control inputs.
Fig. 5 depicts the generic circuit topology we propose for an
-input programmable gate. Clearly, depending on the values
, this circuit can
applied to the control inputs
implement different functions. Compared to other RTD-based
programmable gates previously reported, the design we propose
here presents advantages over each of them. It avoids the use of
series connected transistors in the input stages of [22], which
limits speed. The programmability is digital instead of analog,
as it is in [14], simplifying design and increasing robustness.
Some interesting case studies which have been designed and
validated are summarized in Table I. Design 1 is depicted in
Fig. 6. It implements four functions: AND, EXOR, OR, and NOR.
Simulations shown have been carried out with the setup described in the previous section, including the use of four inverters as load.
V. CONCLUSION
Novel implementations of logic blocks based on the concept
of controlled switching of series-connected RTDs have been
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María J. Avedillo received the Ph.D. degree (summa
cum laude) in electronics and electromagnetism from
the University of Seville, Seville, Spain, in 1992.
Since 1995, she has been an Associate Professor
in the Department of Electronics and Electromagnetism, University of Seville. In 1989, she was a
Researcher at the Department of Analog Design
of the National Microelectronics Center (CNM),
now Institute of Microelectronics, Seville (IMSE).
She has participated in several research projects
financed by the Spanish CICYT and in ESPRIT
Projects. She has authored over 60 technical papers in international journals
and conferences. Her current research interests include design of threshold
logic circuits, design and applications of RTD circuits, and development of
CAD tools logic synthesis.
Dr. Avedillo won the KELVIN Premium of the Council of the Institution of
Electrical Engineers, for two articles published in 1994.
611
José M. Quintana received the Ph.D. degree (summa
cum laude) in electronics and electromagnetism from
the University of Seville, Seville, Spain, in 1987.
Since 1990, he has been an Associate Professor
in the Department of Electronics and Electromagnetism, University of Seville. In 1989, he was a
Researcher at the Department of Analog Design
of the National Microelectronics Center (CNM),
now Institute of Microelectronics at Seville (IMSE).
He has lead and participated in several research
projects financed by the Spanish CICYT and in the
ESPRIT Projects. He has authored over 90 technical papers in international
journals and conferences. His current research interests include the design
and applications of RTD circuits, threshold logic, nonlinear signal processing,
computer arithmetic, and development of CAD tools logic synthesis.
Dr. Quintana won the KELVIN Premium of the Council of the Institution of
Electrical Engineers, in 1994.
Héctor Pettenghi Roldán received the B.S. degree
in electronic physics and M.S. degree in microelectronics from the University of Seville, Seville, Spain,
in 2002 and 2005, respectively. He is currently pursuing the Ph.D. degree at the same university.