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EE141
EE141-Fall 2004
Digital Integrated
Circuits
Administrative Stuff
‰ Homework
#7 due today
ƒ No new homework this week
‰ Project
phase 1 due on Monday
ƒ Report template posted on the web
‰ Project
Lecture 18
PassPass-Transistor Logic
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phase 2 posted
ƒ In lab next week
ƒ Reports due after Spring break
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Class Material
‰ Last
lecture
ƒ SRAM design
ƒ Ratioed logic
‰ Today’s
lecture
Decoders
ƒ Decoder design
ƒ Pass-transistor logic
‰ Reading
ƒ Chapter 6, 12
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ArrayArray-Structured Memory Architecture
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Memory Architecture: Decoders
M bits
S0
S1
S2
M bits
S0
Word 0
Word 1
Word 2
Storage
cell
Word 0
A0
Word 1
A1
Word 2
Storage
cell
w o
rd s
N
SN⫺2
SN⫺1
AK⫺1
Word N⫺2
D eco d re
Word N⫺2
Word N⫺1
Word N⫺1
K ⫽ log2N
Input-Output
(M bits)
Intuitive architecture for N x M memory
Too many select signals:
N words == N select signals
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Input-Output
(M bits)
Decoder reduces the number of select signals
K = log2N
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Hierarchical Decoders
Row Decoders
Multi-stage implementation improves performance
Collection of 2M complex logic gates
Organized in regular and dense fashion
•••
WL 1
(N)AND Decoder
WL 0
A 0A 1 A 0A 1 A 0A 1 A 0A 1
A 2A 3 A 2A 3 A 2A 3 A 2A 3
NOR Decoder
•••
NAND decoder using
2-input prepre-decoders
A1 A0
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A0
A1
A3 A2
A2
A3
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Project Phase 2
WL0
WL1
Pass-Transistor
Logic
SRAM Array
WL63
a5 a4 a3 a5 a4 a3
a2 a1 a0
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Pass-Transistor Logic
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Example: AND Gate
B
Inputs
B
Out
Switch
A
Out
B
Network
A
B
B
F = AB
• N transistors
0
• No static consumption
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NMOS-only Switch
NMOS-Only Logic
C = 2.5 V
C = 2.5V
M2
3.0
In
In
x
0.5 μ m/0.25μ m
1.5μ m/0.25 μm
Voltage [V]
VDD
Out
0.5μ m/0.25 μm
A = 2.5 V
A = 2.5 V
B
Out
2.0
x
B
Mn
M1
CL
1.0
0.0
0
0.5
1
1.5
VB does not pull up to 2.5V, but 2.5V -VTN
2
Time [ns]
Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
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NMOS Only Logic:
Level Restoring Transistor
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Restorer Sizing
VDD
VDD
Level Restorer
3.0
•Upper limit on restorer size
•Pass-transistor pull-down
can have several transistors in
stack
Mr
B
X
Mn
A
Voltage [V]
M2
Out
M1
2.0
W/Lr =1.75/0.25
W/L r =1.50/0.25
1.0
W/Lr =1.0/0.25
0.0
0
100
200
• Advantage: Full Swing
• Restorer adds capacitance, takes away pull down current at X
• Ratio problem
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Complementary Pass Transistor Logic
W/L r =1.25/0.25
300
400
Time [ps]
500
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Solution 2: Transmission Gate
C
A
A
B
B
F
Network
A
(a)
A
A
B
B
B
B
F=AB
A
F=AB
AND/NAND
C
B
C = 2.5 V
B
A = 2.5 V
A
F=A+B
A
B
F=A⊕ΒÝ
F=A+B
B
OR/NOR
A
CL
(b)
A
A
B
B
C
B
B
A
B
F
A
B
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Inverse
Pass-Transistor
Network
B
A
C
Pass-Transistor
C=0V
F=A⊕ΒÝ
EXOR/NEXOR
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Resistance of Transmission Gate
PassPass-Transistor Based Multiplexer
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2. 5 V
Rn
Resistance, ohms
S
S
S
S
VDD
Rp
20
2.5 V
VDD
S
Rn
Vou t
A
Rp
M2
F
S
0V
10
M1
R n || R p
B
S
0
0.0
1.0
GND
2.0
Vou t , V
In1
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Transmission Gate XOR
In2
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Delay in Transmission Gate Networks
2.5
2.5
V1
In
B
C
0
2.5
2.5
Vi
Vi-1
C
0
Vn-1
Vi+1
C
0
Vn
C
C
0
(a)
B
Req
M2
Req
V1
In
Req
Vi
C
Vn-1
Vi+1
C
C
Req
Vn
C
C
A
A
F
(b)
m
M1
M3/M4
Req
B
Req
Req
Req
Req
Req
In
CC
C
C
C
CC
C
B
(c)
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Delay Optimization
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Transmission Gate Full Adder
P
VDD
A
A
P
P
A
B
VDD
Ci
A
P
Ci
VDD
Ci
S Sum Generation
Ci
P
B
VDD
A
P
Co Carry Generation
Ci
A
Setup
P
Similar delays for sum and carry
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Next Lecture
‰ Dynamic
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logic
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