Download 1 Identification and significance of the opportunity

High Temperature (N05-012)
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Identification and significance of the opportunity
The current generation of air vehicle and propulsion systems can be characterized
as centralized control systems in which a (redundant) central computer and
centrally located analog signal interfacing circuitry is used to interface with sensors
and actuators located throughout the aircraft and the propulsion system. A block
diagram of this centralized architecture is shown in fig. 1.0-1. In most instances, the
digital computer implements the “control laws” while the analog circuitry is used for
conditioning the inputs, outputs and for performing actuator loop closures etc. The
types and quantities of sensors and actuators are unique to each system and
therefore lead to an implementation that is new and unique for each new aircraft
and engine. The cost of designing and maintaining these new systems is enormous.
Numerous studies and concept papers {x-x} have shown the advantages of
distributed open system architectures in which centralized computers
communicate via standardized serial data buses with “smart” boxes, which are colocated with the sensors and actuators. The studies also suggest that such a
distributed architecture would greatly reduce not only the total ownership cost (i.e.
development costs plus acquisition and maintenance cost) but also significantly
reduce the weight and fault diagnosis (i.e. detection and isolation) cost associated
due to the simplification and standardization of the wire harnesses. Furthermore,
the “smart” boxes would provide for an open architecture and “standardized” bus
oriented method for interfacing by the host computer regardless of the signal
conditioning and loop closure electronics specific to the actuator or sensor involved.
Furthermore, new systems could then be easily and affordably assembled around a
central processor by re-using these “smart” boxes. These benefits would be greatly
enhanced if these “smart” boxes were somehow reconfigurable or more “generic”
and can therefore reused for multiple sets of actuators and sensors.
Figure 1.0-1 Centralized Architecture with Custom Elements
There are two obstacles to the realization of such open and distributed air vehicle
and propulsion system architectures containing “generic” Electronic Interface
Modules for actuators. First, this open and distributed solution requires the
“Generic” Electronic Modules (GEM) to co-locate and operate in harsher
environments including the high temperature environments (~ 200 deg. C)
associated with actuators. The thermal environment of future super-cruise air
vehicle propulsion systems and flight control actuators is likely to be even more
demanding. However, most electronic components, even industrial grade ones, only
operate up to 125 deg. C. The lack of high temperature (~200 deg. C) parts was a
major driver for the DARPA HiTeC (High Temperature Cooooo) program {x}, to be
launched in 1998, and has led to the development of Silicon on Insulator (SoI)
technology. The HiTeC program has led to the commercial development of several
High Temperature component families (http://www.hiten.com ??) with a basic set of
analog and digital components that can continuously operate at High Temperatures
(225 deg. C). Prominent among them is the HTMOS family from Honeywell
(http://www.ssec.honeywell.com/hightemp/) which offers several basic essential
building blocks, such as microprocessors, memories for program, data and
parameter storage, as well as Gate Arrays and Op. Amps., all of which are essential
for building a generic electronic module. However the HTMOS family from
Honeywell does lack, at least at this point, some key components such as an A/D
converter.
The second obstacle to the realization of “generic” electronic modules is the
diversity of the quantity and types of sensors (position, speed, pressure difference,
temperature etc.) which makes it difficult to develop a “one size fits all” generic
analog signal conditioning interfaces that can be “reused”. In the absence of such a
capability, each electronic module would be custom to its specific actuator and
sensors it was designed for. Even if such a custom electronic box was “open” with
standards based interfaces, the cost of developing, procuring and maintaining it
would once again be significant. The proliferation and lack of reuse for such custom
boxes would make the distributed open architecture approach very unattractive.
Therefore, cost of ownership benefit of open systems architectures has created an
urgent need for Generic Electronic Modules (GEM) which can operate in High
Temperature and which can be reused for multiple applications.
The key innovation in the proposed solution is the maximal digital
implementation of the GEM, wherein all possible analog functions are digitally
implemented making the functions reconfigurable. This emphasis on digital
implementation is driven by two factors. First, digital implementations, especially
software driven digital implementations are more re-usable because the software
permits the same hardware, without changes to be re-used for performing different
functions (e.g. interfacing with different signal types). Second, it easier to make High
temperature digital components than analog components because they require
larger die sizes and higher control of accuracy and leackage currents etc. The
proposed GEM therefore has the minimal but necessary analog “front ends”
consisting basically of Op. amps, that can be reused for interfacing with a diverse
group of analog sensor signals.
A key feature of the proposed solution is that the Generic Electronic Module (GEM)
does not require any as-yet–not-developed new High Temperature devices. The
GEM can be fully implemented by using the available suite of high temperature
electronic components as building blocks. For instance, the 12 bit, accurate, A/D
converter, very difficult to implement as a monolithic device in high temperature, is
constructed by using digital glue logic around a 1 bit A/D converter, i.e., an op.
amps, and a comparator both of which are readily available from the HTMOS family.
Similarly, the generation of A/C excitation and demodulation needed for LVDT
position sensors is done digitally involving only an op. amp. and the A/D converter.
High speed data buses such as Mil-Std-1553 requiring bus transformers are
replaced by simple serial buses such as RS-485 requiring op. amps and digital
logic. Finally, software algorithms are used for digitally demodulating LVDT position
signals thereby permitting the same analog “front end” to be re-used for interfacing
with DC or AC analog signals. Similarly, combinations of op amps. and glue logic
are used to create reusable interfaces for frequency and speed signals.
Reconfiguration of the GEM thus only involves changing the algorithms to be used
for interfacing with LVDT sensors, pressure sensors, temperature sensors and so
on. The basic elements of this concept are sketched in fig. 1.0-2 in which the
custom hardware components shown in fig. 1.0-1 are replaced with standard data
buses and digitally reconfigurable interfaces.
Figure 1.0-2 Reconfigurable GEM Architecture
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Phase I Technical Objectives
The stated technical objectives of the Phase I program is to develop and
demonstrate the feasibility and capabilities of an open systems solution to the
general problem of lack of generic electronic interfaces for actuators in extreme
environments in air vehicles and propulsion systems.
The concept of reconfigurable Smart Terminals, minus the High Temperature
aspects, has been explored in the past, particularly, in the context of distributed
flight control systems. The hardware and software design of the Smart Terminal is
described in Section 4.0. The proposed program builds on the expertise and
lessons learned from this work. The Smart Terminal was designed as a
reconfigurable module for implementing the closed loop control of hydraulic
actuators under the command of a host processor via a serial bus. This project
successfully demonstrated, in the laboratory, the feasibility of digital demodulation
of LVDT signals and digital generation of very accurate AC excitation needed by the
LVDT actuator position sensors. The actuator commands were received over a RS232 serial bus at 80 Hz and the position loop was digitally closed. The primary
difference between that implementation and the requirements of the present topic is
the High Temperature environment. Because the earlier project had no High
Temperature requirements, it was built using industrial grade ICs. As such there
was no need to construct basic building blocks such as an A/D or UART and or Bus
Transceivers needed by the serial bus. Since these building blocks are not available
in the library of HTMOS parts, they will have to be built using available components
from the library of HTMOS and other families. The building blocks needed for this
project will also have to include additional interfaces for frequency and pulse type
input signals associated with pressure and temperature sensors, or torque motor
position signals. However, a review of the HTMOS parts library give us confidence
that these necessary interfaces can also be built using the HTMOS family to meet
the requirements of the High Temperature GEM.
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Phase I Work Plan
In view of this past experience base with the Smart Terminal, the program
objectives will be appropriately tailored to focus on the building of these building
blocks before integrating them into the design of the GEM.
3.1 Interface Definition:
This task involves defining the interface characteristics, including electrical
characteristics, accuracy and resolution etc. for a representative Generic Electronic
Module (GEM). These interfaces will include selected classes of, inputs signals from
actuator position sensors and associated equipment, output signals for actuators
drives and associated equipment, along with interfaces for a data bus and for power
received from the host. The input signal class will include the following signals:
1.
2.
3.
4.
DC and AC actuator position signals from hydraulic and/or EM actuators
Frequency signals from pressure and temperature sensors
Speed and frequency signals from torque motors and EM actuators ???
Analog or discrete switch position signals from contactors and solenoids
The output signal class will consist of the following signals:
1. Current drive signals for hydraulic actuators
2. H Bridge signals (with or without PWM) for torque motors and EM actuators
3. Shutoff and engage discrete signals for solenoids and switches
It should be pointed out that the proposed GEM does not include the final power
drive stages for high power actuator drives for several reasons. First, these drive
tend to consume a lot of power and generate lots of heat, which can adversely
affect the temperature inside a GEM enclosure. Second, the interfaces tend to be
quite specific to the type of actuator and including them in a GEM would not be
consistent with its “generic” nature. Finally, the EMI treatment needed for some of
these power stages tends to be quite elaborate (e.g. Tranzorbs) and tailored to the
type of drive involved. It is believed that the actuator housing is therefore the best
possible location for these power stages because the large mass and relatively
steady temperature profiles at these sites provide significant reliability benefits for
the electronics in spite of their high temperature environment. The best example of
this reliability benefit is the FADEC engine controller which has an excellent
reliability in spite of their harsh environment because it is fuel cooled. In any case,
the output(s) built into the GEM will be generic in design so that they can directly be
connected to the power drive stages located at the actuators.
The serial data bus for the GEM will be the ubiquitous RS-232. This choice is
primarily driven by the constraints of the HTMOS High Temperature chipsets
available for implementation at this time. However, the choice is not much of a
performance constraint because the commands to be sent over this bus from the
host control computer are generated at no more than 100 Hz. This update rate is
not likely to go up for super-cruise air vehicles because of inherent mechanical
considerations. This update rate is distinctly different from the actuator inner loop
closure rates which can be much higher (> 1000 Hz) especially for DDV actuators
and the newer EM actuators on newer aircrafts such as JSF. In any case the RS232 bandwidth achievable will depend on the speed and functions available from
the High Temperature chips in the market. It is anticipated that the available
chipsets will support development of a 9600 Baud RS-232 which can easily support
the above command update rates.
This task will also define the aircraft power requirements for the GEM. The power
requirements of the actuator power drive stages are too specific to the type of
actuators involved and will not be addressed in this section.
3.2 High Temperature Electronics Building Blocks:
This task will focus on building and testing the following major new building blocks
in a standalone fashion:
1. A/D Converter: Typical actuator positional accuracy requirements are
adequately met by a 12 bit A/D converter. The Honeywell HTMOS library
does not offer any A/D converter. A 10 bit A/D converter is under
development at cissoid which is a fables High Temperature SoI development
company (http://www.cissoid.com/). Hence the 12 bit A/D converter will have
to be built up from the library of parts that are available. An A/D converter
can be constructed in one of several ways. An A/D based on the Successive
Approximation Register (SAR) method can be constructed (see fig. 3.2-1)
using an Op amp., plus a comparator, precision D/A converter and a
precision capacitor. Each ADC conversion is divided into two distinct phases
as defined by the position of the switches shown in Fig. 3.2-1. During the
sampling phase (with SW1 and SW2 in the “track” position), a charge
proportional to the voltage on the analog input is developed across the input
sampling capacitor. During the conversion phase (with both switches in the
“hold” position), the capacitor DAC is adjusted via the SAR logic until the
voltage on node A is zero, indicating that the sampled charge on the input
capacitor is balanced out by the charge being output by the capacitor DAC.
The digital value finally contained in the SAR is then latched out as the result
of the ADC conversion. Control of the SAR, and timing of acquisition and
sampling modes, is handled by the ADC control logic. Clearly the acquisition
and conversion times of the SAR method will require fine tuning in order to
meet the rapid sampling requirements of the A/D within the limitations of the
HTMOS family.
Figure 3.2-1 Precision Capacitor based Successive Approximation A/D
A second method for implementing an A/D converter involves a simple latter
network which is driven by the processor and whose output is compared with
the external analog voltage (see fig. 3.2-2). The final selection of the method
used for implementing the A/D will be made during the design process. In
any case the complete A/D design will be built and tested in a stand-alone
fashion to ensure that it meets the performance requirements (sampling time,
accuracy, Sample and Hold times etc.) before proceeding to task 3.2.
Figure 3.2-2 Ladder Network based Successive Approximation A/D
2. RS-232 UART and Transceivers: In the simplest form, the RS-232
transceivers are voltage level translators that convert signals from UART
(Universal Asynchronous Receiver/ Transmitter) at TTL to the serial bus
levels (5V to 15 V). As such they can be constructed using the op. amps.
available from the High Temperature parts library. The HTMOS micro
controller (HT83C51) contains a UART for communication between the
processor and a remote host. The documentation for the device states that it
is capable of half duplex (either transmit or receive but not both at the same
time) communication, which is acceptable for our application. If the speed of
the UART is not adequate to support our bandwidth needs, an external
UART can be built. This design of a UART is well documented in the
literature {x}and can be implemented using the High Temperature chipsets
available. In this design, the incoming signal is sampled by the UART at up to
6 times the signal baud rate to detect a logic “1” or “0” which is then shifted
into a register. When 8 continuous bits are recognized and received into the
shift register, they are moved into a buffer and monitoring of the bus for new
bits is started. The host processor is notified via an interrupt when the buffer
is full. On the output side, a byte of data is continuously shifted out at the
prescribed rate from the shift register loaded by the host processor. In any
case the complete RS-232 design, including the UART and the transceivers,
will be built and tested in a stand alone fashion to ensure that it meets the
performance requirements (data bandwidth, error rates etc.) before
proceeding to task 3.2.
3. Frequency and Pulse signal Conditioning: These type of signals usually
associated with pressure sensors and sometimes even temperature sensors.
Regardless, in most such instances, the value of the signal is proportional to
the number of signal pulses received in a fixed time duration. The
implementation of the interface for such signal is shown is shown in fig. 3.2-3
and is quite straight forward and consists of counting the number of pulses
from the signal as well from an accurate time reference signal such as a
clock. In most instances, the ratio of the two counts is proportional to the
pressure or temperature. The digital portion of this implementation is
anticipated to fit in one Gate Array in the HTMOS family.
Figure 3.2-3 Generic Frequency and Pulse Conditioning Interface
3.3 Prototype Development:
This task will involve the development and integration/testing of a complete GEM
prototype. This task will utilize the basic design of the Smart Terminal as a starting
point for hardware and software. The hardware design will substitute the
components in the design described in Section 4.0 with ICs from the HTMOS or any
other families as necessary. The A/D and RS-232 building blocks developed in task
3.2 will be integrated into the design and the entire GEM design will be fabricated
and tested.
The software design for the GEM will begin with the proven software code for the
ADC812 micro-converter which uses the Intel 8051 core. Since the HTMOS micro
processor (HT83C51) also uses the same Intel 8051 core, most of the code will be
directly applicable. The new external A/D converter and the new RS-232 interface
will drive the majority of the changes. Additional code will be required for interfacing
with the additional Input and Output interfaces described in section 3.1.
The hardware and software for the GEM will be integrated and tested in the Lab
using simulated interfaces. Tools such as LabView will be used to cost effectively
and rapidly develop or procure these representative simulated actuators and
sensors and connected to the GEM Hardware for end-to-end testing of selected
configurations. Testing with real actuators and sensors will be postponed until Phase
II.
3.4 Laboratory Demonstration and Testing:
This final task will utilize the GEM and its simulated interfaces for testing and
demonstrating, in the laboratory, the operation, performance characteristics and
bandwidth etc. for a selected representative actuator configuration. Specifically, the
following parameters or characteristics will be measured and approaches for
refinements will be investigated:
1. A/D sampling rate and accuracy.
2. LVDT, Pressure, Temperature and other sensor digital processing (e.g.
demodulation) accuracy and time.
3. Loop closure calculations timing.
The characterization data collected during this task will form the basis for further
refinements in Phase II. The High Temperature characteristics of the design will be
tested only in Phase II.
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Related Work
1. Smart Terminal Design: A block diagram of the Smart I/O Terminal hardware is
shown in fig. 4.0-1. The design shows connections for one LVDT (Coils A and B)
connected to one of the input Multiplexer channels. Two of the analog inputs are
configured for bipolar signals with a range of 0 to 5Volts. Each analog input
channel is configured with a two pole low pass filter. The Built In Test (BIT)
circuitry is provided to calibrate the input channels using two known voltages. An
additional analog input channel is used as a wrap-around to sense the current
through the MOSFET solenoid driver. Port 2 of the micro-converter is used for
digital outputs. The internal D/A converter (DAC 1) is used to drive a torque
motor requiring 0 to 4mA current. A second D/A converter (DAC 0) is used to
digitally provide the LVDT excitation. The Analog Devices AduC812 microconverter has an internal RS-422 serial which is used to download the software
code from a PC into its 8KB flash memory and to receive the actuator
commands from the PC (i.e. Host computer). The 2.25” x 2.5” size printed circuit
board and its layout are shown in fig. 4.0-2.
Figure 4.0-1 Block Diagram of Smart Terminal Hardware
Figure 4.0-2 Smart Terminal PC Board and Layout
The software for the Smart Terminal consists on an infinite loop that performs the
following functions.
 Acquire the modulated LVDT position feedback data
 Demodulate the LVDT data
 Perform the LVDT difference over sum calculation
 Receive the host actuator position command
 Generate an error signal from the command and feedback signals
 Perform compensation
 Output a new actuation position
The time critical code sections (i.e. sampling and ISRs) are written in Intel 8051
Assembly language while the non-critical computations are written in C using the
Keil compiler. The total size of the code is less than 1000 lines.
The LVDT coil A and B are sampled at high rate (2000 Hz) are processed to
obtain their RMS values. A ratio metric calculation (A-B)/(A+B) is performed to
eliminate the effects of the excitation voltage, reject common mode noise and
obtain the actuator LVDT position signal. The actuator command is then
generated as shown in fig. 4.0-3 by using the command received over the RS232 and filtering the error signal. The actuator command signal is then output
through a DAC to a voltage to current drive circuit. These control loop
calculations are performed at 80Hz as shown in fig. 4.0-4.
Figure 4.0-3 Actuator Closed Loop Control
Figure 4.0-4 Software Tasks and Execution Timing
The sinusoidal LVDT excitation is also generated by the same computational
loop shown in fig. 4.0-5 and out put via a D/A (DAC 0). A programmable 12.5
msec. timer runs the entire computational loop to ensure system operation at 80
Hz.
Figure 4.0-5 Digitally Generated LVDT Excitation
The Laboratory setup for the Smart Terminal is shown in fig. 4.0-6. The Smart
Terminal was integrated with a hydraulic actuator in the lab and driven by a 8 Hz
sinusoidal command the results of which are shown in the video of fig. 4.0-7.
Figure 4.0-6 Laboratory Setup for Smart Terminal Testing.
Figure 4.0-7 Hydraulic Actuator under Test
2. HiTeC Prgram Experience:
3. Describe UM expertise ???
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Relationship with Future Research or R&D
An important benefit of a GEM based distributed system architecture is the
replacement of very heavy and unreliable wire harnesses with reliable, intelligent
serial data buses and power lines. These wire harness savings are accrued
because of two factors. First, the large number of wires between the host computer
(FADEC or Flight Control Computer) and the remote actuators are replaced with 4
wires (RS-232 + Power). Second, the weight of material and components required
for shielding, filtering and EMI protecting is greatly reduced or eliminated due to the
proximity of the GEM to the actuators. These savings in maintainability and fault
isolation can contribute significantly to the overall availability of future air vehicles.
Further savings in wire weight beyond those accrued by the distributed GEM
architecture are possible by use several technologies. A first candidate technology
would be Power-Over-Wire (PoW) where power for the GEM electronics would be
supplied over the serial bus. This is a feasible expansion of the capabilities of the
GEM and can be implemented using the available HTMOS chips. Furher weight
reduction may be possible by using wireless technology. However, the impact of
wireless communication on the deterministic command bandwidth of the actuator
loop would have to be further studied before this technology can be deployed.
Additionally, the lack of High Temperature parts, including batteries, and the
marginal nature of the weight savings may make this technology unattractive.
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A more promising area worthy of further work is the miniaturization of the GEM
electronics. The number of components in the Smart Terminal module were so few
that the the entire module could have been fitted inside the connector to the
actuator, thereby providing the electronics a perfect faraday cage and a thermal
sink (via the actuator). It should be possible to apply this concept to the GEM
electronics by further miniaturization. The implementation of a reliable,
reconfigurable, High Temperature GEM small enough to fit in a connector would
significantly impact the ownership cost and maintainability/ availability of future air
vehicles and should therefore be the aim of the Phase II program.
Commercialization Plan
Aerospace market,………????
Key Personnel
Dr. Bhal Tulpule, has worked for United Technologies for the past 25 years. He is
retiring from United Technologies Corporation in early 2005 and will thereafter be
associated with Techno Sciences Inc. During the last 4 years Dr. Tulpule, has
worked as Program Manager and Principal Investigator responsible for multiple
Government contract R&D and internal programs primarily focused on Sikorsky
Aircraft Div. of UTC. These programs, valued at more than $ 2 Million, were aimed
at developing next generation, distributed architectures and products for control and
on-board diagnostics systems. In particular, he was responsible for evaluating
wireless technologies and products for rotorcraft communication and diagnostic
strain sensors. During this period he also investigated distributed architectures,
Smart Terminals, wireless nodes and fault tolerant network topologies. Prior
responsibilities at Hamilton Sundstrand division of UTC involved the architecture,
design and validation testing of Flight Control Computer Systems for Sikorsky Hawk
series of helicopters as well as production development of the Flight control
systems for the Apache Longbow and the JSF demonstrator prototype. Dr. Tulpule
received his M.S. and Ph.D. in Electrical Engineering from the University of
Connecticut. He has published 5 papers and holds 20+ patents on various aspects
of fault tolerant computer architectures.
Mr. Steve Raccio is the owner SAR Industrial Electronics, an electronic product
development Company based in Oxford, CT. Steve is an experienced high
technology product development and R&D manager with substantial experience in
pressure & temperature sensors, and MEMS devices. For a major part of his career,
Steve was the Operations/Engineering Manager at the Dresser Equipment Div of
Halliburton Corp. in Stratford, CT, where he was responsible for development and
production of Sensors that operate in the Harsh Environments of Oil Wells. He has
two patents on Pressure sensor and MEMS. Steve’s hands on expertise in
development of stable “low noise” front-end circuitry for sensors operating in High
Temperature environments will be a significant asset to this program. Steve’s recent
Business leadership role at Standard MEMS Inc. will also be useful for transitioning
the prototype GEM into a production ready device in Phase II.
TSI (UM>>> Neil ?)
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Facilities/Equipment
TSi labs.
Consultants
Dr. George Foyt will provide assistance in the design and use of High Temperature
components. Dr. Foyt has had a distinguished career at the UTC Research Center
(UTRC) and the MIT Lincoln Laboratory. While at UTRC, Dr. Foyt was the Program
Manager of the DARPA sponsored 16 Million $ consortium program for High
Temperature Electronics (HiTeC). Dr. Foyt has enjoyed a rich technical career,
largely in the fields of semiconductors and microelectronics. His work has included
high-speed transistors (at the Bell Telephone Laboratories), Gunn Effect devices,
ion implantation, infra-red detectors, avalanche photodiodes, long-lifetime diode
lasers, opto-electronic devices (at the MIT Lincoln Laboratories), and hightemperature electronics, precision pressure sensors and accelerometers, low noise
oscillators, and high-density microelectronic packaging (at the United Technologies
Research Center).
10 Prior, Current or Pending Support
11 Cost Proposal
12 References
1. Distributed arch paper 1
2. Distributed arch paper 2
3. DARPA HiTeC Program:
4. Design of a UART
5. ….
6. [[[[