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® RT7207D USB PD Type-C Controller for SMPS General Description Features The RT7207D is a secondary-side USB Power Delivery (USB PD) Type-C controller for high-efficiency off-line ACDC converters with slim form factor. The RT7207D integrates an MCU as a policy engine to handle USB PD protocol, and also integrates a built-in Biphase Mark Coding (BMC) transceiver for USB PD or other proprietary protocols. An internal synchronous rectifier controller (SRC) can operate in both continuous-conduction mode (CCM) and discontinuous-conduction mode (DCM) even in the condition of a wide output voltage range of 3.3V to 20V. Dual operational amplifiers with respectively programmable reference voltages are included for voltage-loop and currentloop regulation to provide programmable constant-voltage (CV) and constant-current (CC) regulation in high precision. RT7207D Customized Firmware Part For Example : AABBX AA = Firmware Application Code BB = Hardware Model Code X = Firmware Version Code Package Type QW : WQFN-24L 4x4 (W-Type) (Exposed Pad-Option 2) Lead Plating System G : Green (Halogen Free and Pb Free) RT7207D Version (Refer to Version Table) Note : Richtek products are : RoHS compliant and compatible with the current require- Pin Configuration (TOP VIEW) BLD PGND VG V9 VCP V5 Ordering Information 24 23 22 21 20 19 V_TR CS+ CSDD+ CC_GND 1 18 2 17 3 16 GND 4 15 25 5 6 14 13 7 8 V2 AGND VDD VDD USBP OVP 9 10 11 12 CC1 CC2 RT IFB VFB OPTO USB PD Type-C Chargers/Adapters for Smart Phones, NBs, Tablets and All Other Electronics. USB PD Extension Cores with Offline AC-DC Converters. USB PD 2.0 and 3.0 Other Proprietary Protocols Highly Integrated Embedded MCU with an OTP-ROM of 32kB and an SRAM of 1.5kB Embedded BMC Transceiver Built-in Synchronous Rectifier Driver and Controller Built-in Charge Pump for a Wide VDD Operatio Range of 3.3V to 20V Built-in Shunt Regulator for Constant-Voltage and Constant-Current Control Programmable Cable Compensation BLD Pin for Quick Discharge of Output Capacitor USBP Pin for Direct Drive of External Blocking P-MOSFET Power-Saving Mode in Standby Mode Protection Adaptive Output Over-Voltage Protection Adaptive Under-Voltage Protection Firmware-Programmable Over-Current Protection Firmware-Programmable Over-Temperature Protection Applications Protocols Supported WQFN-24L 4x4 ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS7207D-00 January 2017 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT7207D Marking Information AB= : Product Code AB=YM DNNAA BBX YMDNN : Date Code AABBX : Firmware Code Simplified Application Circuit VBUS + RFB1 RFB2 GND RVDS1 V_TR VG VDD CS- Synchronous Rectifier Controller CS+ BLD OPTO CS Amp IFB USBP VFB CC_CV Shunt Regulator OTPROM D+ D- DAC I/O Interface SRAM Protection MCU TMR CC1 ADC CC2 IO Bias WDT PHY RT7207D USB Type-C Connector RT7207D Version Table Version RT7207D RT7207DL Maximum Output Voltage 20V 12V SR MOSFET VDS Scaling Factor [RVDS2 / (RVDS1 + RVDS2) ] 1/42 1/26 VOUT Scaling Factor [RFB2 / (RFB1 + RFB2) ] 1/8 1/5 Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS7207D-00 January 2017 RT7207D Functional Pin Description Pin No. Pin Name Type Pin Function 1 V_TR AI Transformer voltage sense node. 2 CS+ AI Positive input of a current-sense amplifier for output current sensing. 3 CS- AI Negative input of a current-sense amplifier for output current sensing. 4 D- A/D IO USB D- channel. 5 D+ A/D IO USB D+ channel. 6 CC_GND GND 7 CC1 A/D IO Type-C connector Configuration Channel (CC) 1, used to detect a cable plug event and determine the cable orientation. 8 CC2 A/D IO Type-C connector Configuration Channel (CC) 2, used to detect a cable plug event and determine the cable orientation. 9 RT A/D I 10 IFB AI Feedback input for the constant-current loop. 11 VFB AI Feedback input for the constant-voltage loop. 12 OPTO AO Current sink output for optocoupler connection. 13 OVP AO Over-voltage fault indication output, used to pull low an optocoupler. 14 USBP D IO Control signal of the blocking P-MOSFET. 15, 16 VDD PWR Supply input voltage. 17 AGND GND Analog ground. 18 V2 PWR Regulated DC bias to supply for the MCU. 19 V5 PWR Regulated DC bias to supply for internal circuitry. 20 VCP AO 21 V9 PWR 22 VG AO 23 PGND GND Power ground. 24 BLD D IO Bleeder connection node to provide another path to discharge the output capacitor. 25 GND GND Power ground. The exposed pad must be connected to GND and well soldered to a large PCB copper area for maximum power dissipation. Alternative ground for CC1 and CC2. Remote thermal sensor connection node for over-temperature protection. Charge pump driver output. Regulated DC bias to supply for the synchronous rectifier driver. Gate driver output for the SR MOSFET. Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS7207D-00 January 2017 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT7207D Functional Block Diagram VREF_CC OPTO VFB CC_CV Shunt Regulator VREF_CV V_TR DAC RT ADC IFB CS Amp CS+ CS- RT VDD D+ OTP-ROM DP DM D- BLD BLD SRAM V_TR Synchronous Rectifier Controller MCU 2 I C TMR VG IO PROG/TST WDT V9 Charge Pump USBP USBP OVP OVP CC1 CC2 CC1 VCP V5 Power V2 Green Alarm OSC Protection PHY PGND CC2 AGND VDD Operation The RT7207D is a highly integrated secondary-side USB PD Type-C controller with various functions and protections for off-line AC-DC converters. Power Structure Biased by the VDD pin, the RT7207D has two regulated DC output voltages, V5 and V2, to supply the internal circuit and the internal microprocessor (MCU). The bypass capacitors at the V2 and V5 pins are required to improve stability of the internal LDO and to minimize regulated ripple voltages. The RT7207D also integrates a charge pump to generate a boost voltage V9 from V5 with VCP pin for capacitor connection so that the V9 voltage can be nearly 2 times of the V5 voltage and the VG pin can directly drive the SR MOSFET. Besides, the charge pump allows the controller to operate under low supply voltage condition as long as the output voltage is not below the programmed UVP level. Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 Constant-Voltage and Constant-Current (CV/CC) Regulators Two regulators are paralleled and connected to an opendrain output, OPTO pin. The operation of each feedback loop is similar to that of the traditional TL431 shunt regulator except that VOPTO operating range is wider, from 0.3V to 25V, which enables easy design of converters with a wider output range. The OPTO pin will be in high-impedance state, if the VDD voltage is still below a UVLO threshold VVDD_ON, which ensures a smooth power-on sequence. The reference voltages, VREF_CV and VREF_CC, for the voltage and current feedback loops, respectively, are analog output voltages from the embedded DAC, and their digital counterparts are from the MCU. The analog output range of the 9-bit DAC is from 0 to VDAC_MAX (typical 2.7V), which makes output voltage resolution as small as 42mV and 26mV for the RT7207D and RT7207DL, respectively, to achieve high-precision CV regulation. is a registered trademark of Richtek Technology Corporation. DS7207D-00 January 2017 RT7207D VFB OPTO IFB + + - - VREF_CV DAC VREF_CC UVLO CS+ + CS- - A Io_signal Figure 1. CV and CC Loops Current-Sense Amplifier Interface of D+ and D- To minimize power loss of the current sense resistor in The D+ and D- pins are used for BC1.2 compliance or for the converter, the RT7207D has an amplifier with virtually zero input offset voltage and with a register-programmable voltage gain of 20 or 40. The sensed output current is amplified by the current-sense amplifier, shown as “Io_signal” in Figure 1, which is then sent to the currentloop regulator for constant-current regulation and also sent to the MCU, by way of an ADC for analog-to-digital conversion, to update the output current status for the MCU. communication with other proprietary protocols. The D+ and D- pins, connected to the MCU via an ADC, can be reprogrammed for other purposes since they can be used as an analog/digital input or output, as shown in Figure 3. 1.8V DPMDO_LEV ADC External Temperature Sensing The RT7207D provides the RT pin, as a registerprogrammable current source to bias a remote thermal sensor, such as a thermistor (NTC), as shown in Figure 2. If the RT voltage is below an over-temperature protection (OTP) threshold and the condition sustains for a programmed time delay, the OTP will be triggered. 3V 4.2V AIN RH_DPDM DPOE DPO MCU D+/D- DPPE DPPO DPI RL_DPDM IO of DP/DM Parameter Table OTP[9:0] 3.6V sDPM_SHORT SHORT SWITCH RT_BIAS[1:0] RT[9:0] MCU ADC DI Figure 3. Interface of D+ and DRT DOL NTC Figure 2. External Temperature Sensing Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS7207D-00 January 2017 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT7207D Interface of CC1 and CC2 The CC1 and CC2 are used for compliance with USB PD Type-C specification. When configured as a Downstream Facing Port (DFP), three current capabilities of 80μA, 180μA, and 330μA, provided by each of the CC pins, will be advertised to an Upstream Facing Port (UFP) as default USB current, 1.5A, and 3.0A, respectively, as shown in Figure 4. The OVP pin is pulled low when output over-voltage condition (register-programmable : 120%, 125%, 130%) occurs. By way of an optocoupler, it can shut down the primary-side controller (for example, RT7786). DIEN DOL BLD/ USBP/ OVP DI 1.125V 5V CC1I ADC MCU Figure 5. Interface of the BLD, USBP and OVP Pins AIN CC1OE CC1O CCI_LO CC1/ CC2 CCI_HI USB_PD Figure 4. Interface of CC1 and CC2 Open-Drain Drivers for BLD, USBP and OVP Pins The BLD, USBP and OVP pins with their specific functions are driven by open-drain drivers, as shown in Figure 5 and explained below. The BLD pin is used as a bleeder to help discharge the output capacitor to Vsafe5V upon the detachment of a connected device, or to a lower desired output voltage level upon a UFP request, such as from 20V to 12V. A resistor is connected between VOUT and the BLD pin and a power resistor can be used for better power dissipation capability. SR Control To improve the AC-DC converters efficiency, the RT7207D includes a SR controller, which has proprietary autotracking function to minimize dead time between the conduction intervals of the SR MOSFET and the main switch MOSFET, while it can still ensure safe operation in both DCM and CCM conditions and even in a wide output range. To prevent the on-time overlap of the main switch MOSFET and the SR MOSFET, the SR controller will be temporarily turned off under conditions of load transition, output voltage transition, output short circuit, or low output or input voltages with programmable thresholds. At light load or no load condition, the SR controller will also be disabled to reduce power consumption. The USBP pin provides an active-low enable control for an external blocking P-MOSFET for VBUS isolation, as shown in Typical Application Circuit. If no UFP is attached or any fault condition, such as over-voltage, under-voltage, overtemperature, or short-circuit, occurs, the USBP pin will be pulled high to disable the P-MOSFET for VBUS isolation. Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS7207D-00 January 2017 RT7207D Absolute Maximum Ratings (Note 1) VDD, OPTO, BLD, OVP, USBP to GND ---------------------------------------------------------------------------CC1, CC2 to GND -------------------------------------------------------------------------------------------------------V9, VG to GND ----------------------------------------------------------------------------------------------------------V5, VCP, VFB, IFB, V_TR, RT, D+, D-, CS+, CS- to GND -----------------------------------------------------V2 to GND ----------------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WQFN-24L 4x4 ----------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN-24L 4x4, θJA ----------------------------------------------------------------------------------------------------WQFN-24L 4x4, θJC ----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------------Junction Temperature --------------------------------------------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Model) -------------------------------------------------------------------------------------------- Recommended Operating Conditions −0.3V to 25V −0.3V to 22V −0.3V to 12V −0.3V to 6.5V −0.3V to 2.5V 3.57W 28°C/W 7.1°C/W 260°C 150°C −65°C to 150°C 2kV (Note 4) Supply Input Voltage, VDD --------------------------------------------------------------------------------------------- 3.3V to 22V Junction Temperature Range ------------------------------------------------------------------------------------------ −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------------------------ −40°C to 85°C Electrical Characteristics (TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit VDD Turn-On Threshold Voltage VVDD_ON 3.25 3.35 3.45 V VDD Turn-Off Threshold Voltage VVDD_OFF 3.05 3.15 3.25 V VDD Start-Up Current IDD_START VDD = 5V -- 100 200 A VDD Operating Current IDD_OP SR driver is disabled -- 10 -- mA VDD Sleep-Mode Current IDD_SLEEP In sleep mode -- 750 -- A VDD Over-Voltage Protection Threshold Voltage VVDD_OVP 23 24 25 V VDD Over-Voltage Protection Deglitch Time tD_VDDOVP -- 50 -- s MCU Operating Frequency fOSC_MCU VDD = 5V 20.5 21.6 22.7 MHz VBIAS_V5 6V < VDD < 25V 4.75 5 5.25 V -- -- 150 mV 60 90 120 mA VDD Section Internal Bias V5 Load Regulation V5 Output Short-Circuit Current 1mA < IBIAS_V5 < 30mA IV5_SC Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS7207D-00 January 2017 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT7207D Parameter V2 Symbol VBIAS_V2 Load Regulation V2 Output Short-Circuit Current Test Conditions 3.3V < VDD < 25V 1mA < IBIAS_V2 < 20mA IV2_SC Min Typ Max Unit 1.71 1.8 1.89 V -- -- 20 mV 30 50 70 mA 2.67 2.7 2.73 V Regulators Section Maximum DAC Output Voltage for CC and CV Regulators VDAC_MAX 9-bit D/A conversion Ratio of Change in Reference Input Voltage to Change in OPTO Voltage VREF VOPTO VOPTO = 25V to VREF (Note 5) -- 1.2 2.4 mV/V Reference Input Current IREF (Note 5) -- 0.1 -- A Off-State OPTO Current IOPTO_OFF OPTO pin is open-circuited -- 230 500 nA VOPTO = VREF, IOPTO = 1mA, f < 1kHz (Note 5) -- 0.22 0.5 IOPTO_SINK = 10mA (Note 5) -- -- 150 2 -- 20 mA 0 -- 20 -- 1 -- 40 -- Dynamic Impedance ZOPTO OPTO Turn-On Impedance RON_OPTO Maximum OPTO Sinking Current IOPTO_MAX Current-Sense Amplifier Register-Programmable Current-Sense Voltage Gain V/V Unit Gain Bandwidth (Note 5) 1000 -- -- kHz Output Current (Note 5) -- 0.1 -- mA 150 170 190 kHz Charge Pump Section Charge Pump Operating Frequency f CP Rise Time tR_CP CL = 6nF, V5 = 5V, from 20% to 80% 70 140 210 ns Fall Time tF_CP CL = 6nF, V5 = 5V, from 80% to 20% 60 110 160 ns (Note 5) -- -- 10 Charge Pump Driver Impedance ROUT_CP SR Driver Turn-On Threshold VV9_SRON 4.9 5.1 5.3 V SR Driver Turn-Off Threshold VV9_SROFF 4.3 4.5 4.7 V Debounce Time tD_V9 -- 50 -- s V9 Turn-On Threshold Voltage VV9_ON 3.1 3.3 3.5 V V9 Turn-Off Threshold Voltage VV9_OFF 2.9 3.1 3.3 V 3.2 3.6 4 V 00 90 100 110 01 18 20 22 10 3.6 4 4.4 (Note 5) RT Section Open-Loop Voltage VRT_OP Register-Programmable Internal IBIAS_RT Bias Current Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 VDD = 5V A is a registered trademark of Richtek Technology Corporation. DS7207D-00 January 2017 RT7207D Parameter Symbol Test Conditions Min Typ Max Unit 2 -- 20 mA -- -- 150 00 114 120 126 01 118.75 125 131.25 10 123.5 130 136.5 -- 50 -- s OVP Pin Section Maximum OVP Sinking Current IOVP_MAX Pull-Low Impedance RL_OVP (Note 5) Register-Programmable Over-Voltage Protection Threshold VVOUT_OVP With respect to VREF_CV Debounce Time tD_VOUTOVP OVP pin is latched till VDD is below VVDD_OFF Maximum BLD Sinking Current IBLD_MAX In 300ms 0.5 -- 0.6 A Pull-Low Impedance RL_BLD (Note 5) -- 10 15 15 20 25 k 11 3.78 4.2 4.62 01 2.7 3 3.3 10 1.62 1.8 1.98 -- -- 0.2 00 1 1.1 1.2 01 1.1 1.2 1.3 10 1.2 1.3 1.4 11 1.3 1.4 1.5 00 0.7 0.8 0.9 01 0.8 0.9 1 10 0.9 1 1.1 11 1 1.1 1.2 -- -- 40 % BLD Section D+, D-Section Pull-High/-Low Resistance RH_DPDM, RL_DPDM VOH_4.2V Register-Programmable Output High Voltage VOH_3.0V VDD = 5V, RLOAD = 15k VOH_1.8V V VOL_4.2V Output Low Voltage VOL_3.0V RLOAD = 15k V VOL_1.8V Register-Programmable Input High Trip Voltage Register-Programmable Input Low Trip Voltage DPDM Switch On-Resistance VIH_DPDM VIL_ DPDM RON_DPDM V V CC1, CC2 Section Output High Voltage VOH_CC 1.05 1.125 1.2 V Output Low Voltage VOL_CC 0 0.0375 0.075 V 00 0.7 0.8 0.9 01 0.6 0.7 0.8 10 0.5 0.6 0.7 11 0.4 0.5 0.6 Register-Programmable Input High Trip Voltage VIH_CC Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS7207D-00 January 2017 V is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT7207D Parameter Register-Programmable Input Low Trip Voltage Rise Time/Fall Time Register-Programmable Sourcing Current Symbol Test Conditions VIL_CC tR_CC, tF_CC Min Typ Max 00 0.4 0.5 0.6 01 0.3 0.4 0.5 10 0.2 0.3 0.4 11 0.1 0.2 0.3 300 -- -- 01 72 80 88 10 166 180 194 11 304 330 356 2 -- 20 mA CLOAD = 600pF ICC_SRC Unit V ns A USBP Section Maximum USBP Sinking Current IUSBP_MAX Pull-Low Impedance RL_USBP (Note 5) -- -- 150 Rise Time tR_VG CL = 6nF, V9 = 9V, from 20% to 80% -- 75 125 ns Fall Time tF_VG CL = 6nF, V9 = 9V, from 80% to 20% -- 35 85 ns 00 180 280 380 tDELAY Delay and debounce time of V_TR falling tDELAY = tV_TR_FALLING + tP 01 130 230 330 10 80 180 280 11 30 130 230 -- 100 -- ns -- 20 -- k 000 0.35 0.45 0.55 001 0.3 0.4 0.5 010 0.25 0.35 0.45 011 0.2 0.3 0.4 100 0.15 0.25 0.35 101 0.1 0.2 0.3 110 0.05 0.15 0.25 111 0 0.1 0.2 0.025 0.125 0.2 0 -- 0.1 -- 1 -- 0.05 -- SR Driver Section OTP-Programmable Turn-On Delay Propagation Delay tP Internal Pull-Low Resistor (Note 5) ns V_TR Section OTP-Programmable V_TR Under V TH_VTR_UV Voltage Threshold V_TR Falling Edge Threshold Voltage VTH_VTR_F Register-Programmable Dead Time Comparator Threshold VTH_VTR_DT Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 If VV_TR_SH – (VOUT x KVDS_SR) > VTH_VTR_UV, SR driver is active SR turn-on trip point V V V is a registered trademark of Richtek Technology Corporation. DS7207D-00 January 2017 RT7207D Parameter Symbol Test Conditions Min Typ Max Unit -- -- 40 ns 3.8 4 4.2 V RVDS2 / (RVDS1 + RVDS2) (For RT7207D) (Note 5) -- 1/42 -- RVDS2 / (RVDS1 + RVDS2) (For RT7207DL) (Note 5) -- 1/26 -- 4.56 4.8 5.04 k -- 1.06 -- -- 00 -- 0.3 -- 01 -- 0.5 -- 10 -- 0.7 -- 11 -- 0.9 -- tPERIOD_MIN Interval limit from V_TR rising edge to VG falling edge The clock period is based on fOSC_MCU and can be set by the 12-bit register (Note 5) -- 190 -- s tINHIBIT_SR Interval limit from VG rising edge to next VG rising edge The clock period is based on fOSC_MCU and can be set by the 9-bit register (Note 5) -- 24 -- s 00 -- 2100 -- 01 -- 1600 -- tDEAD_PLL If VG falling edge to VTH_VTR_DT interval < tDEAD_PLL, VG will skipped two cycles and reset automatic tracking counter (Note 5) 10 -- 1100 -- 11 -- 600 -- If tPW M[n] > KFAULT_PLL x tPW M[n-1], reset automatic tracking counter (Note 5) -- 1.5 -- Dead Time Comparator Delay V_TR Over-Voltage Threshold (Note 5) VTH_VTR_OV SR Control Section SR MOSFET VDS Scaling Factor V_TR Internal Resistance Maximum Ratio of VG On-Time OTP-Programmable V_TR Pulse Width Expansion/Shrink Limit Register-Programmable Minimum Period Register-Programmable SR Gate Inhibit Time KVDS_SR RVDS2 KSRON_MAX If tSR_ON[n] > tSR_ON[n-1] x KSRON_MAX, tSR_ON[n] will limited to tSR_ON[n-1] x KSRON_MAX and stop automatic tracking counter (Note 5) tPWLMT_VTR If tV_TR[n] > tV_TR[n-1] + tPWLMT_VTR or tV_TR[n] < tV_TR[n-1] tPWLMT_VTR, reset automatic tracking counter (Note 5) -- s PLL Function Section Register-Programmable PLL Dead Time Fault PLL Ratio KFAULT_PLL Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS7207D-00 January 2017 ns -- is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT7207D Parameter Symbol Test Conditions Min Typ Max 00 -- 2500 -- 01 -- 2000 -- 10 -- 1500 -- 11 -- 1000 -- -- 1 -- Unit Automatic Tracking Section Register-Programmable Auto-Tracking Dead Time tDEAD_TRACK Maximum Step Time for Tracking Up/Down VG falling edge to VTH_VTR_DT interval (Note 5) With respect to VREF_CV (Note 5) ns % Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effectivethermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design. Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 is a registered trademark of Richtek Technology Corporation. DS7207D-00 January 2017 RT7207D CC1 CC2 8 CC1 7 D+ 5 D4 V9 21 RT7207D option OPTO 1 V_TR OPTO 12 IFB 10 22 VG + VCP 20 CC_GND / VFB AGND V5 11 6, 17 19 15, 16 3 VDD CS- 2 CS+ 18 V2 9 24 23 13 RT BLD PGND OVP 14 USBP CC2 GND VBUS Typical Application Circuit GND COMP AC Mains HV DMAG VDD RT7786 GATE option + CS/OTP + Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS7207D-00 January 2017 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT7207D Typical Operating Characteristics VVDD_OFF vs. Temperature 3.19 3.37 3.17 VVDD_OFF (V) VVDD_ON (V) VVDD_ON vs. Temperature 3.39 3.35 3.33 3.15 3.13 3.31 3.11 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (°C) 50 75 100 125 IDD_SLEEP vs. Temperature 10.0 700 9.8 650 I DD_SLEEP ( μ A) I DD_OP (mA) IDD_OP vs. Temperature 9.6 600 550 9.4 500 9.2 -50 -25 0 25 50 75 100 -50 125 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) VVDD_OVP vs. Temperature fOSC_MCU vs. Temperature 25.0 23.00 24.5 22.25 f OSC_MSU (MHz) VVDD_OVP (V) 25 Temperature (°C) 24.0 23.5 125 21.50 20.75 23.0 20.00 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 125 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. DS7207D-00 January 2017 RT7207D VBIAS_V2 vs. Temperature 1.90 5.1 1.85 VBIAS_V2 (V) VBIAS_V5 (V) VBIAS_V5 vs. Temperature 5.2 5.0 4.9 1.80 1.75 4.8 1.70 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (°C) VDAC_MAX vs. Temperature 50 75 100 125 IOPTO_OFF vs. Temperature 2.74 50.0 2.72 37.5 I OPTO_OFF (nA) VDAC_MAX (V) 25 Temperature (°C) 2.70 2.68 25.0 12.5 2.66 0.0 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (°C) 25 50 75 100 125 Temperature (°C) CS Gain vs. Temperature IOPTO_MAX vs. Temperature 100.0 50 87.5 40 CS Gain I OPTO_MAX (mA) 1 : CS Gain_40 75.0 30 0 : CS Gain_20 62.5 20 50.0 10 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS7207D-00 January 2017 125 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT7207D VV9_SRON vs. Temperature 5.3 170 5.2 VV9_SRON (V) f CP (kHz) fCP vs. Temperature 175 165 5.1 5.0 160 4.9 155 -50 -25 0 25 50 75 100 -50 125 -25 0 Temperature (°C) VV9_SROFF vs. Temperature 50 75 100 125 100 125 VV9_ON vs. Temperature 4.7 3.5 4.6 3.4 VV9_ON (V) VV9_SROFF (V) 25 Temperature (°C) 4.5 4.4 3.3 3.2 4.3 3.1 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 Temperature (°C) Temperature (°C) VV9_OFF vs. Temperature IBIAS_RT vs. Temperature 120 3.3 100 00 : 100μA I BIAS_RT ( μA) VV9_OFF (V) 3.2 3.1 80 60 40 3.0 01 : 20μA 20 10 : 4μA 2.9 0 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 125 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. DS7207D-00 January 2017 RT7207D IOVP_MAX vs. Temperature VVOUT_OVP vs. Temperature 50 135 10 : 130% 130 VVOUT_OVP (%) I OVP_MAX (mA) 45 40 35 01 : 125% 125 00 : 120% 120 30 115 -50 -25 0 25 50 75 100 125 -50 25 50 75 100 IBLD_MAX vs. Temperature RH_DPDM & RL_DPDM vs. Temperature 125 RH_DPDM & RL_DPDM (k Ω) 22 0.7 I BLD_MAX (A) 0 Temperature (°C) 0.8 0.6 0.5 0.4 21 20 19 18 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) VOH_DPDM vs. Temperature VOL_DPDM vs. Temperature 5.0 125 40.0 4.5 11 : 4.2V 37.5 VOL_DPDM (mV) 4.0 VOH_DPDM (V) -25 Temperature (°C) 3.5 01 : 3.0V 3.0 2.5 4.2V 3.0V 1.8V 35.0 32.5 10 : 1.8V 2.0 1.5 30.0 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS7207D-00 January 2017 125 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT7207D VIL_DPDM vs. Temperature VIH_DPDM vs. Temperature 1.5 1.2 11 : 1.4V 11 : 1.1V 1.1 10 : 1.3V VIL_DPDM (V) VIH_DPDM (V) 1.4 1.3 01 : 1.2V 1.2 10 : 1.0V 1.0 01 : 0.9V 0.9 00 : 1.1V 00 : 0.8V 1.1 0.8 0.7 1.0 -50 -25 0 25 50 75 100 -50 125 -25 0 RON_DPDM vs. Temperature 50 75 100 125 100 125 VOH_CC vs. Temperature 26.0 1.175 25.5 1.150 VOH_CC (V) RON_DPDM (Ω) 25 Temperature (°C) Temperature (°C) 25.0 24.5 1.125 1.100 24.0 1.075 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (°C) 25 50 75 Temperature (°C) VOL_CC vs. Temperature VIH_CC vs. Temperature 0.9 0.00250 00 : 0.8V 0.8 VIH_CC (V) VOL_CC (V) 0.00125 0.00000 01 : 0.7V 0.7 10 : 0.6V 0.6 11 : 0.5V -0.00125 0.5 0.4 -0.00250 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 125 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. DS7207D-00 January 2017 RT7207D tR_CC & tF_CC vs. Temperature VIL_CC vs. Temperature 440 0.6 00 : 0.5V 01 : 0.4V 0.4 10 : 0.3V 0.3 430 tR_CC & tF_CC (ns) VIL_CC (V) 0.5 tF_CC 420 tR_CC 410 11 : 0.2V 0.2 400 0.1 -50 -25 0 25 50 75 100 -50 125 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) ICC_SRC vs. Temperature IUSBP_MAX vs. Temperature 50 360 11 : 330μA 300 I USBP_MAX (mA) I CC_SRC ( μA) 40 240 10 : 180μA 180 30 20 120 01 : 80μA 60 10 -25 0 25 50 75 100 -50 125 -25 0 25 50 75 Temperature (°C) Temperature (°C) tR_VG vs. Temperature tF_VG vs. Temperature 100 50.0 90 47.5 tF_VG (ns) tR_VG (ns) -50 80 70 100 125 100 125 45.0 42.5 60 40.0 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS7207D-00 January 2017 125 -50 -25 0 25 50 75 Temperature (°C) is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT7207D VTH_VTR_UV vs. Temperature tDELAY vs. Temperature 380 500 330 VTH_VTR_UV (mV) 00 : 280ns tDEALY (ns) 000 : 0.45V 450 280 01 : 230ns 230 10 : 180ns 180 001 : 0.4V 400 010 : 0.35V 350 011 : 0.3V 300 100 : 0.25V 250 101 : 0.2V 200 11 : 130ns 130 110 : 0.15V 150 80 111 : 0.1V 100 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (°C) 25 50 75 100 125 Temperature (°C) VTH_VTR_F vs. Temperature VTH_VTR_DT vs. Temperature 112.5 125 0 : 0.1V VTH_VTR_DT (mV) VTH_VTR_F (mV) 110.0 107.5 105.0 100 75 1 : 0.05V 50 102.5 25 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (°C) VTH_VTR_OV vs. Temperature 50 75 100 125 100 125 RVDS2 vs. Temperature 4.05 5.00 4.00 4.90 RVDS2 (k Ω) VTH_VTR_OV (V) 25 Temperature (°C) 3.95 4.80 4.70 3.90 4.60 3.85 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 125 -50 -25 0 25 50 75 Temperature (°C) is a registered trademark of Richtek Technology Corporation. DS7207D-00 January 2017 RT7207D Application Information Constant-Voltage (CV) Loop CTR : Current transfer ratio of the optocoupler As shown in Figure 6, the RT7207D incorporates 2 error amplifiers (EA) inside to regulate the output voltage and current, respectively. The output voltage is determined as : VF : Forward voltage of the optocoupler R VOUT 1 FB1 VREF_CV R FB2 For the RT7207D : The ratio of RFB1 / RFB2 is set as 7, and it is recommended to use 91kΩ and 13kΩ for minimizing power loss in the resistor divider. 0.3V : The minimum OPTO voltage for the OPTO driver to sink 2mA. ICOMP_MAX : The maximum COMP sourcing current of a traditional PWM controller in the primary side. It is a current sourced from an internal bias through a built-in pull-high resistor connected the COMP pin in the PWM controller. VDD (VOUT) RD For the RT7207DL : The ratio of RFB1 / RFB2 is set as 4, and it is recommended to use 30kΩ and 7.5kΩ for better resolution of CV regulation. The RT7207D integrates a virtually-zero input-offset-voltage current-sense amplifier with differential-mode inputs to minimize noise interference. The voltage gain of 20 or 40 can be set by the internal register. The amplified output current sense signal, sent to an ADC for A/D conversion, is monitored and processed by the MCU, and is also sent to the CC loop. The reference voltage of the CC loop is determined by V REF_CC (from the DAC), which is programmed by chargers' requirements. Both the constantvoltage and constant-current compensation loops are connected together at the OPTO pin. The OPTO driver sinks current through an optocoupler and an external resistor RD from output voltage, and the optocoupler isolates the secondary side from the primary side and also provide the feedback compensation signal for the primary side. Note that for better linearity of the loop compensation range, RD should be designed to cover for operation at the minimum output voltage. (VOUT _MIN VF 0.3V) RD RV VFB + - + - IFB RFB1 CV OPTO Therefore, the VOUT is determined by VREF_CV, the analog output from the DAC, and its digital counterpart, which is controlled by the MCU, as shown in Functional Block Diagram. Constant-Current (CC) Loop and Current-Sense Amplifier CC RC RFB2 VREF_CV DAC VREF_CC CS+ UVLO + CCS - A Io_signal CS- Figure 6. CC and CV Loops and Current-Sense Amplifier Power-Up Sequence Figure 7 shows the timing diagram for the power-up sequence. When start-up, the default output is set at 5V. Once a Type-C cable is attached, the UFP will deliver voltage and current settings to the RT7207D for the MCU to decode and to program reference voltages, VREF_CV and VREF_CC, for the CV and CC loops, which are the analog outputs converted by the DAC. If the Type-C cable is detached, or the output current is lower than the powersaving mode threshold, which is typically programmed as 200mA, the RT7207D will enter power-saving mode, under which the RT7207D operates at ultra-low operating current and thus the total input power can be saved. If the output current increases and exceeds the power-saving mode threshold, or any input/output signal is toggled, the RT7207D will exit power-saving mode. CTR ICOMP _MAX Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS7207D-00 January 2017 is a registered trademark of Richtek Technology Corporation. www.richtek.com 21 RT7207D 5V CV5 DCP1 DCP2 CV9 VVDD_ON VDD V5 Power-saving mode threshold IOUT CCP VCP IV9 V9 ROUT_CP V5 VG V2 V9 Power-Saving Mode Figure 8. Charge Pump Circuit Debounce time to enter power-saving mode Figure 7. The Waveforms of the Bias Voltages during Start-Up Internal Biases and Charge Pump The RT7207D provides three regulated bias voltages, V5, V2, and V9. The V5 bias voltage is the output of a linear regulator powered by VDD, and supplies the internal analog circuit and the charge pump driver. The V2 bias voltage is the output of a linear regulator powered by V5, and supplies the MCU. As shown in Figure 8, the RT7207D also integrates a charge pump circuit to generate V9 to supply for the SR driver when VDD is at lower levels, such as 3.3V to 5V. If the RT7207D enters power-saving mode, the charge pump driver will be disabled. The minimum source/sink capability of charge pump driver is around 10mA at 170kHz of charge pump operating frequency fCP. Bypass capacitor on the V5, V2 and V9 pins are required to minimize output ripples of the biases. Output Voltage Rises and Falls When the protocol is detected, the reference voltage VREF_CV can be set by the request of the UFP. Both the rise time and fall time of output voltages should be less than 275ms in accordance with the USB PD Specification, as shown in Figure 9. During the time of VOUT falling, as shown in Figure 10, the BLD driver will be turned on as a dummy load to provide an extra discharging path for the output capacitor so that VOUT can be settled in a shorter duration. The designed RDUMMY is as : COUT x (RDUMMY + RL_BLD) x 2 < 275ms During the time of VOUT rising or falling, the SR driver will be turned off. After a firmware programmable delay time 300ms, the RT7207D will sense the load condition and may reactivate the SR driver. V9 = V5 x 2 − VF_DCP1 − VF_DCP2 − IV9 x ROUT_CP When output voltage is set at lower levels (<5V), V5 will be lower, following VDD by a voltage drop of a dropout voltage of the LDO. For higher V9, a lower forward voltage for the Schottky diodes, DCP1 and DCP2, is required. 20V VOUT 5V <275ms 5ms 2.5V The RT7207D provides V5 short-circuit protection against the condition that the V5, V2, or VCP pin is shorted to GND, and also provides under-voltage protection for V9. If the V9 voltage is below VV9_SRON (typical 4.5V), the SR driver will be turned off, that is, VG will be inactivated. VREF_CV 0.625V Slope 1.875V / 275ms 5mV/750µs SR_EN (a) Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 22 is a registered trademark of Richtek Technology Corporation. DS7207D-00 January 2017 RT7207D VOUT 20V 5V VREF_CV <275ms to 100°C can be improved. The RT7207D can deliver the sensed RT voltage data back to the UFP via the protocol (Vendor Defined Message), if necessary. Figure 11 shows the RT voltages vary with temperature at three different bias currents with an NTC thermistor TTC104 as an example. 2.5V Slope -1.875V / 275ms -5mV/750µs 2.5V 200µs SR_EN 2V 4µA 100µA VRT 300ms (programmable) VBLD 20µA 1V (b) 0.4V Figure 9. (a) VOUT Rises. (b) VOUT Falls. 0°C 50°C 100°C Temperature + COUT RDUMMY Figure 11. The RT Voltages vs. Temperature at Three Bias Currents USBP Control DIEN DOL BLD DI Figure 10. Application Circuit of an Active Dummy Load Temperature Sensing and Thermal Protection The RT7207D provides the RT pin for over-temperature protection or thermal monitoring. As shown in Figure 2, the RT pin sources a constant bias current for a remote thermal sensor of an NTC thermistor, connected from the RT pin to GND, for temperature sensing. If the RT voltage is below a programmable threshold voltage and the condition sustains for a programmable deglitch time, overtemperature protection will be triggered. The bias current through the RT pin can be programmed as 100μA, 20μA, or 4μA by setting the internal register. With the appropriate bias current setting, linearity of temperature sensing over the temperature range of 25°C Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS7207D-00 January 2017 The RT7207D provides an open-drain driver for controlling an external blocking P-MOSFET. Once the communication is set up with an UFP, or a 5.1kΩ resistor at the CC1/CC2 pin of a Type-C connector of the UFP is detected, the PMOSFET will be turned on. If VOUT over-voltage condition occurs, the blocking P-MOSFET will be turned off to prevent the UFP from being damaged by the VOUT overvoltage condition. If VOUT is shorted to GND, the PMOSFET will also be turned off automatically so that output power can be limited. Output Over-Voltage Protection As shown in the Figure 12, the RT7207D provides the OVP pin as a backup VOUT over-voltage protection, in case the optocoupler of the feedback loop is malfunction due to aging. If the internal voltage related to VDD is higher by the programmable threshold VVOUT_OVP, the OVP pin will be pulled low. The OVP pin voltage will be latched low until the VDD voltage drops below the VDD turn-off threshold VVDD_OFF, as shown in Figure 13. is a registered trademark of Richtek Technology Corporation. www.richtek.com 23 RT7207D where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. V OUT R D2 RD CV RV OPTO For continuous operation, the maximum operating junction temperature indicated under Recommended Operating Conditions is 125°C. The junction-to-ambient thermal resistance, θJA, is highly package dependent. For a WQFN-24L 4x4 package, the thermal resistance, θJA, is 28°C/W on a standard JEDEC 51-7 high effective-thermalconductivity four-layer test board. The maximum power dissipation at TA = 25°C can be calculated as below : OVP R FB1 + R FB2 VFB V REF_CV - x1.2/x1.25/x1.3 A VDD R1 INT_ “VDDOV” + BLD_EN ADC MCU S PD(MAX) = (125°C − 25°C) / (28°C/W) = 3.57W for a WQFN-24L 4x4 package. Q R VVDD_OFF Figure 12. OVP Pin Block Diagram The maximum power dissipation depends on the operating ambient temperature for the fixed TJ(MAX) and the thermal resistance, θJA. The derating curves in Figure 14 allows Debounce time of latched OPTO by MCU is around 10µs the designer to see the effect of rising ambient temperature on the maximum power dissipation. 4.0 VOUT VDD = VVDD_OFF INT_VDDOV VOVP tD_VOUTOVP Figure 13. Timing Sequence of the OVP Pin Function Thermal Considerations The junction temperature should never exceed the absolute maximum junction temperature TJ(MAX), listed under Absolute Maximum Ratings, to avoid permanent damage to the device. The maximum allowable power dissipation depends on the thermal resistance of the IC package, the PCB layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. The maximum power dissipation can be calculated using the following formula : Maximum Power Dissipation (W)1 OV hys Four-Layer PCB 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 14. Derating Curve of Maximum Power Dissipation PD(MAX) = (TJ(MAX) − TA) / θJA Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 24 is a registered trademark of Richtek Technology Corporation. DS7207D-00 January 2017 RT7207D Outline Dimension D2 D SEE DETAIL A L 1 E E2 e b A3 Symbol D2 E2 1 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A1 1 2 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.950 4.050 0.156 0.159 Option 1 2.400 2.500 0.094 0.098 Option 2 2.650 2.750 0.104 0.108 E 3.950 4.050 0.156 0.159 Option 1 2.400 2.500 0.094 0.098 Option 2 2.650 2.750 0.104 0.108 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 24L QFN 4x4 Package Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS7207D-00 January 2017 is a registered trademark of Richtek Technology Corporation. www.richtek.com 25 RT7207D Footprint Information Package V/W/U/XQFN4*4-24 Option1 Option2 Footprint Dimension (mm) Number of Pin P Ax Ay Bx By C D 24 0.50 4.80 4.80 3.10 3.10 0.85 0.30 Sx Sy 2.55 2.55 2.60 2.60 Tolerance ±0.05 Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 26 DS7207D-00 January 2017