Download row a

The Analog section of the Front-End Board v. 2.1
(Last updated: August 1, 2001)
S.Argiro’1, D.Camin2, P.Cattaneo3, E.Menichetti1, P.Trapani1
1
2
University and INFN, Torino
University and INFN,Milano
3
INFN Pavia
1. Overview of the Front-End Board
We have developed a second version of the Analog section of the Front-End Board
(FEB). For a history of earlier versions, see i. The Digital section, containing FADC,
memories etc, has been developed by the Karlsruhe group . The original design and
simulation of the channel electronics for the Analog section has been made by the
Milano and Pavia groups. The physical implementation, layout and routing of the
board has been made by the Torino. There has been a strong interaction between our
Italian groups and the German group in Karlsruhe in all the phases of this design.
2. Design guidelines
Design guidelines for this version 2.1 have been the following:
-
-
-
Have a full separation of digital and analog worlds (ground, power, signals,
controls)
Implement the Virtual Channel solution for the dynamic range expansion with
respect to the FADC 12 bit capability. The Compressor solution ii, initially
implemented in version 1.0, has been found to raise some problems in terms of
reliability, implementation complexity, power consumption and reconstruction of
waveforms.
Try to implement all the testing facilities and controls foreseen for a final version,
in order to allow for best interconnections with the rest of the trigger and readout
system
Allow for as many programmable controls of the chain as possible, in order to
facilitate setting-up and tuning
3. Description of the Analog section –version 2.1
The Analog section is a sort of daughter board of the FEB, the mother board being
the Digital section. The full FEB is a 9U high, 220 mm deep Eurocard assembly,
housed by a standard VME-like crate and power supply. The FEB is made by a 6U
high Digital section and a 3U high Analog section, connected vertically by 3 high-
density, microminiature 50-pin connectors. The Analog section is also connected to a
dedicated analog backplane by one standard 96-pin connector (Fig. 1).
The board contains 22 channels of Front-End analog electronics, serving as many
pixels, plus two lower gain virtual channels, meant to add up 11 channels each one.
Channels are arranged into two arrays, consisting of eleven elements each one. The
first array contains odd numbered channels (1 to 21), the second even ones (2 to 22).
Analog differential signals from the Camera Distribution Board are received over the
auxiliary (analog) backplane at the top of the rear side of the crate, 22 per connector.
A list of all the board connections is shown in Appendix A .Signals are then routed
through the chain, whose block diagram is shown in Fig. 2. With the two Virtual
channels, the total number of differential outputs (to the FADC sitting in the Digital
section) is 24.
The common signal of each differential input carries a level proportional to the
average detector current, with the goal of providing a background signal useful for
debugging and control. For this purpose, the common signal is splitted out of the pair
and fed to a on-board, Sigma/Delta ADC. The serial output of the ADC is
continuously sent to a digital interface in the Digital section.
On the Analog Board a simple circuitry that allows sending pulses to the Head
Electronics is implemented. An external pulser is connected to the board either via a
pin on the backplane (ATP) or through a Lemo connector located on the front panel.
The signal is then routed to two differential line drivers, and sent to the Head
Electronics over two twisted-pair cables (TP1OUT+, TP1OUT-,TP2OUT+,
TP2OUT). These are meant to be injected at the very front-end, right before the
differential line driver from the anode signal to the AB, through a transistor switch.
The first twisted pair will serve channels corresponding to 1 through 11 on the AB,
while the second will serve channels 12 through 22. In this way, each signal will serve
half a column of PMTs on the camera. Two active-low signals, /EN_C1 and /EN_C2,
perform the enabling of the drivers on the AB. They are sent out as EN_CxD to the
Head Electronics to switch the transistors on. In addition, the possibility of
generating test pulses on the Analog Board, without the need of an external pulser,
has been foreseen. Acting on the digital lines /TP1 and /TP22 will cause an analog
switch to generate a pulse swing from ground to a programmable level, named ATP.
This will simulate a pulse which is routed to the differential line drivers of above.
Signals /TP1 and /TP22 serve channels 12..22 and 1..11 respectively. To avoid
sending signals to unwanted channels, the same /TPxx lines can be used to disable the
corresponding line receivers.
A further test feature allows generation of test patterns, simulating a fluorescence
light track traversing the camera, as suggested by the Karlsruhe group. Again, the
/TPxx lines are used to drive analog switches from ground to a programmable level.
This simulated fluorescence pulse is then injected into the line receiver reference
input. The presence of the Head Electronics is therefore not required.
Chain control and setting is performed with some flexibility, upon changing the value
of programmable potentiometers. A single programmable pot per channel will fix the
gain of the input stage. Power consumption levels have been kept as low as possible,
although a margin for improvement exists. With the present levels of power supply
voltage, we anticipate a linear range of 0 : 4 V for our output signals.
3. Changes from version 1 to version 2
A summary of the most important changes from version 1.0 to version 2.1 follows:





Implementation of the Virtual Channel solution alone for dynamic range
compression
Implementation of the Test Pattern to simulate fluorescence track in the camera
without Head Electronics
Implementation of internal test pulse generation
Replacement of voltage regulators and substitution by LC filters
Changes in the Antialiasing filter: from a 3-pole with cut at 1.5 MHz to a 4-pole
with cut a 4.1 MHz
4. Status of the project (1/8/2001)
48 Analog Boards have been produced and delivered during the month of February.
This is enough to equip two Telescopes with spares.
The boards were proven to function properly on site, a detailed performance study is
ongoing.
A problem of digital noise pickup has been identified. While hoping to improve the
layout to avoid the effect in the production design, we are confident that it will not
harm productive prototype operation.
Figure 1 : Board Layout
RECEIVE
GAIN
STAGE
R
FILTER
G HI
G HI
...
#1
...
#11

G LO
Figure 2: Block Diagram of the Analog Channel
Appendix A
SIGNAL DESCRIPTION:
POWER LINES:
INPUT
+V
+5.2V
-V
-5.2V
Where
A27,B27,C27
On P0
A28,B28,C28
On P0
Dig
/An
I
Turns
I
mA
into
mA
A
+Va1
A
+Va2
+Va3
+Va4
+Va5
+Va6
-Va1
V
5.2V
As above
A
-Va2
-Va3
-Va4
-Va5
-Va6
VM
+V
As above
A
+V_SD
D
VDD
+3.3V
+5V_A
-12V
JDH1
A18,B18,
A17,B17
P0 A29,
B29,C29
C30 on P0
A
A
+5V_A
on
JDH1,
JDH2,
JDH3
Meaning
Regulated to +5V
Serves Analog Channels 1-3-5-7
Serves Analog Channels 9-11-13-15
Serves Analog Channels 17-19-21-23
Serves Analog Channels 2-4-6-8
Serves Analog Channels 10-12-14-16
Serves Analog Channels 18-20-22-24
As above for negative polarity
Regulated to 5V powers the two
differential line drivers on sheet
TPULSE
Regulated to +5V,powers the analog
sections of the four AD73360 on sheet
ADCs
Powers the Digital section of the
AD AD73360
Serves the FADCs on the Digital
Board
Used to enable the NPN transistor
on the HE to allow injection of TP
DIGITAL CONTROLS
DPOT
DCS[0..3]
JDH2 A7,A8,B7,B8
PSDI, PSDO
JDH2 A9,B9
MCLK
JDH3 A19
GI[1..24]
Sheets DPOT, Channels
GO[1..24]
Connected to the
terminals of the
potentiometers, Gain
controls
As Above
JDH1, JDH2, JDH3
/TP1..22
VBIAS[1..2]
4 in 16 decoding for Chip
select of the 7 DPOT
After decoding CS[0..6]
on page DPOT Note that
when no chip is selected
a Null code must be
set (e.g. 1111)
Serial I/O for the DPOT.
The chips are connected
in parallel
MCLK (10Mhz)is sent to
the DPOTS as CLK only
when a chip is selected
DPOT, ADCs
Test Pulse and Test
Pattern controls
allows biasing the
reference to the AD73360
ADCs (AD73360)
SDIFS, SDOFS
A22,B22
SDI, SDO
JDH3 A21,b21
SE
RESET
MCLK
JDH3 A20
JDH3 B20
JDH3 A19
Serial Port Enable
Reset
Master Clock (10Mhz)
SCLK
JDH3 B19
GREF1,GREF2
JDH3 A12, A25 on P0
Serial Port clock (out
from ad73360, made from
MCLK
divided
by
some
programmable ratio)
Ground reference (shield)
for inputs 1-11 and 12-22
see DPOT
VBIAS[1..2]
Frame sync signals for
operation of the Ad73360
Serial Port
Serial Data I/O
TPULSE
TP_IN
/EN_C1, /EN_C2
Front panel or
ATP (A30 on P0)
JDH2 B6, JDH3 B15
EN_C1D, EN_C2D
P0 C12, C25
TP1OUT+, TP1OUTTP2OUT+, TP2OUT-
A13, A26, C13, C26 on P0
Test Pulse In
Active low, enables test
pulsing on channels 1-11
or 12-22
0 or -12V to enable test
pulsing on the Head
Test Pulse Out to HE
on two twisted-pairs
ANALOG Channels
+V[1..22]
-V[1..22]
VOUT[1..22]
SGND[1..24]
P0 A1-A11, C1-C11
P0 A14-A24, C14-C24
JDH 1,2,3
VOUT23
JDH 2
VOUT24
JDH 3
Differential input
output signal
output signal ground
reference
virtual channel :
sum of odd channels
virtual channel: sum of
even channels
Connector J1
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
row a
SGnd01
AGND
Vout03
+5V_A
SGnd05
AGND
Vout07
+5V_A
SGnd09
AGND
Vout11
+5V_A
SGnd13
AGND
Vout15
+5V_A
SGnd17
AGND
Vout19
+5V_A
/Tp01
/Tp05
/Tp09
/Tp13
/Tp17
row b
Vout01
AGND
SGnd03
AGND
Vout05
AGND
SGnd07
AGND
Vout09
AGND
SGnd11
AGND
Vout13
AGND
SGnd15
AGND
Vout17
AGND
SGnd19
AGND
/Tp03
/Tp07
/Tp11
/Tp15
/Tp19
Connector J2
row a
SGnd21
AGND
Vout23
AGND
Spare_1
/Tp21
DCS2
DCS0
PSDI
VDD
/Tp02
/Tp06
/Tp10
AGND
Vout02
+5V_A
SGnd04
AGND
Vout06
+5V_A
SGnd08
AGND
Vout10
+5V_A
SGnd12
row b
Vout21
AGND
SGnd23
AGND
Spare_2
En_C1
DCS3
DCS1
PSDO
DGND
/Tp04
/Tp08
/Tp12
AGND
SGnd02
AGND
Vout04
AGND
SGnd06
AGND
Vout08
AGND
SGnd10
AGND
Vout12
Connector J3
row a
Vout14
AGND
SGnd16
+5V_A
Vout18
AGND
SGnd20
+5V_A
Vout22
AGND
SGnd24
AGND
/Tp14
/Tp18
/Tp22
DGND
VDD
+5Vdig
MCLK
SE
SDI
SDIFS.
Pos0
Pos2
Pos4
Spare_1 and Spare_2 are connected to the FPGA (function to be defined later)
row b
SGnd14
AGND
Vout16
AGND
SGnd18
AGND
Vout20
AGND
SGnd22
AGND
Vout24
AGND
/Tp16
/Tp20
En_C2
DGND
VDD
+5Vdig
SCLK
RESET
SDO
SDOFS
Pos1
Pos3
PosRef
Pin #
1
Row A
V+1
GRef1
Row B
AGnd
Row C
V-1
Function
Differential Input of PMT #1, 5V pp, +/-2.5V relative to
2
V+2
AGnd
V-2
Differential Input of PMT #2, 5V pp, +/-2.5V relative to
GRef1
....
....
....
....
....
....
....
Differential Input of PMT #10, 5V pp, +/-2.5V relative
3
V+3
AGnd
V-3
4
V+4
AGnd
V-4
5
V+5
AGnd
V-5
6
V+6
AGnd
V-6
7
V+7
AGnd
V-7
8
V+8
AGnd
V-8
9
V+9
AGnd
V-9
10
V+10
AGnd
V-10
to GRef1
11
V+11
AGnd
V-11
Differential Input of PMT #11, 5V pp, +/-2.5V relative
to GRef1
12
GRef1
AGnd
En_C1D
Reference for CM chn 1..11 and testpulse enable
13
TP1O+ AGnd
Tp1ODifferential testpulse for chn 1..11 at HE
14
V+12
AGnd
V-12
Differential Input of PMT #12, 5V pp, +/-2.5V relative
to GRef2
15
V+13
AGnd
V-13
Differential Input of V+T #13, 5V pp, +/-2.5V relative
to GRef2
16
V+14
AGnd
V-14
....
17
V+15
AGnd
V-15
....
18
V+16
AGnd
V-16
....
19
V+17
AGnd
V-17
....
20
V+18
AGnd
V-18
....
21
V+19
AGnd
V-19
....
22
V+20
AGnd
V-20
....
23
V+21
AGnd
V-21
Differential Input of PMT #21, 5V pp, +/-2.5V relative to
GRef2
24
V+22
AGnd
V-22
Differential Input of PMT #22, 5V pp, +/-2.5V relative to
GRef2
25
GRef2
AGnd
En_C2D
Reference for CM chn 12..22 and testpulse enable
26
TP2O+ AGnd
TP2ODifferential testpuls for chn 12..22 at HE
27
+V1
+V2
+V3
+V[1..3]: positive analog supply voltage (to be defined
+5..+12 V )
total current per slot: < 500 mA
28
-V1
-V2
-V3
-V[1..3]: negative analog supply voltage (to be defined –
5..-12 V )
total current per slot: < 500 mA
29
+5V_A +5V_A
+5V_A
analog +5V for ADCs and sigma/delta; -12V for
testpulser
total current per slot: < 1000 mA
30
ATP
Spare
-12V
ATP: Analog Amplitude of testpattern generator (from
2.LTB)
31
Pos0
Pos1
Pos2
Pos0..4: Base Address of slot position: 0=slot2,
..,19=slo21
0 = slot 2, 1= slot 3, ....,19= slot21
32
Pos3
PosRef
Pos4
PosRef: Reference for Pos0..4, logical 1 = pull down to
PosRef
Spare: spare line, may be defined later
Note: AGnd and power lines pin 27,28,29,30 are bussed lines to all slots in the crate
i
http://www.to.infn.it/auger/feb
ii
P.F. Manfredi et al., “A bilinear analog compressor to adapt the signal dynamic
range in the Auger fluorescence detector”, Nucl. Inst. Meth. A461 (2001) 526529