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CET270 – Intro. to Microprocessor Design
Team Asmt. 2: CHAPTER PROBLEMS
Due: Feb 16, 2015
Neatly write-up and submit answers to the following chapter 2 exercises:
2, 4, 5, 6, 7, 12, 16, 17, 20, 21, 23, 31, 32, 33, 42, 44, 52
This is a group assignment with team members matching your lab group.
Assignment submission requirements:
 Make sure that this and all future assignments have an appropriate standard cover page following
this template. [3]
 Assignment submissions shall be neat and professional.
 All pages are to be stapled together with a single staple in the upper-left corner.
 Note that your signature on the cover page authenticates that you did in fact participate on the
work in question. Only students whose signature is present on the cover page will receive points
for the assignment.
Answer Key:
2. [3] sequential addition of 3 numbers:
C200
C201
C202
C203
C204
C205
C206
C207
C208
C209
C20A
C20B
C20C
C20D
C20E
C20F
C210
C211
B6
C2
0E
BB
C2
0F
BB
C2
10
B7
C2
11
3E
??
??
??
??
LDAA
ADDA
ADDA
STAA
STOP (WAI)
<= may be any number of bytes
(N1)
(N2)
(N3)
(SUM)
4. [1] Given that an instruction using direct addressing can only access operands in page 0 (000000FF), is it true that the instruction must also be within this address range?
No, the instruction can be located anywhere in memory
5. [1] Is the offset of an instruction with indexed addressing interpreted as an unsigned or a 2’s
complement number?
Unsigned
6. [1] What is the addressing mode of an instruction that contains a constant data number within the
instruction code?
Immediate
7. [1] What is the addressing mode of an instruction that does not form a memory address?
Implied / inherent
12. [1] When a double-byte data number is stored in memory, is the high byte placed at the higher or
lower of the two addresses?
Lower
16. [2] Immediately following the execution of a LDAA instruction, can the N and Z bits both be 1? Both
be 0?
a) no, they cannot both be 1
b) yes, they can both be 0
17. [2] What single instruction will set, without affecting any other CCR bits, the C bit? The N bit?
a) SEC sets only the C flag
b) there is no single instruction that directly affects N
20. [2] What is the machine code for a single instruction that undoubtedly puts zero in accumulator B, and
another instruction that puts zero into memory location C221?
a) 5F (CLRB) or C6 00 (LDAB #0)
b) 7F C2 21 (CLR $C221)
21. [3] (program module to exchange accumulators A & B)
23. [1] The BHS instruction is normally used with unsigned numbers.
31. [1] Bit 11 of D is also bit 3 of the A accumulator.
32. [2] What is the hex code for a BRA that branches to itself? What is the effect of executing this
instruction in a program?
a) 20 FE
b) Causes an infinite loop & locks up the processor/program.
33. [2] Find all known condition code bits if a DEC instruction decrements a $80.
N=0, Z=0, V=1, C=0
42. [1] Two unsigned numbers are loaded into A and B and then subtracted with an SBA instruction. If the
program must branch only when the number in B is lower than the number in A, use the ___
instruction following SBA.
BHS
44. [2] Find the hex code for a BRA instruction at C131 that must branch to C147; and another at C178
that must branch to C158.
a) 20 14
b) 20 DE
52. [1] Which branch instruction must immediately follow a TSTA instruction to cause a branch if and only
if the number in A is a nonzero unsigned number?
BHI