Download EECS 140

EECS 140
Final Project
Due Wednesday 5/14/08 at 5pm
Spring 08
Note: Use the device parameters and spice models given in the class handout
Design a programmable-gain element in an analog to digital converter. Your
amplifier must meet the following specs:
1. Single sided supply between 2.5 and 5.5V.
2. Input between 0 and 1V
3. Output from 0.4 to 2.1V.
4. 0.1pF capacitive load.
5. Digitally controlled gain of 1, 2, 4, 8, or 16, accurate to 0.2% assuming perfect
capacitors
6. Phase margin >45 degrees under all gain settings
Design restrictions
 Your circuit can contain as many mosfets and capacitors as you wish.
MOSFET dimensions should be in multiples of 0.5um. The smallest
MOSFET allowed is W/L 1u/0.5u. Capacitors in the feedback network
must have an integer ratio (e.g. C1=C2, or C1=16*C2). Making C1 equal,
for example, 15.8*C2 is explicitly not allowed.
 Your circuit may contain 1 resistor. If you want more, you need to explain
why.
 Your circuit may contain no independent sources or controlled sources
other than Vdd, phi1, and phi2. All simulations must be run (and all
performance specs met) with the same waveforms for phi1 and phi2.
Using ideal switches and ideal bias voltages will result in a substantial loss
of points.
 All of the sources of error (offset voltage, charge injection, finite
gain, settling time, slew rate, etc...) come together before the
falling edge of phi2. If you get the right output voltage within 0.2%
at the falling edge of phi2 for all of the test cases below, you've
satisfied the gain accuracy requirements. Some of you may have startup
transients on the first iteration of phi1 and phi2. It’s ok to show the
second iteration.
Projects are to be done individually by students. You are encouraged to discuss your
ideas with other students, and help each other with your designs, but there are limits. Do
help each other debug SPICE problems, but Don’t share SPICE decks. Do work together
on topologies, formulas, and design ideas, but Don’t jointly agree on what all the
saturation voltages, drain currents, and W/L values should be.
The report format must be as follows:
Cover page (1 page)
Your name and SID, followed by a short datasheet with the specified
performance, your hand-calculated performance, SPICE simulated performance, and a
reference to the page number where the supporting documentation (SPICE decks & plots,
analysis) can be found.
Schematic diagram (1 page)
Annotated with W/L, Vdsat, and Id for all devices.
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Supporting documentation (no page limit, but please keep it concise and clear!)
1. Bode plot of open loop amplifier loaded with output and feedback capacitance at
Vdd=2.5 and Vdd=5.5, gain of 1 and gain of 16
.op of open loop amplifier at Vdd=2.5 and Vdd=5.5
2. Your hand calculations of Id, Vdsat, gm, ro, w_p1, w_p2, w_pm . These should
match the spice results to within 10%. Label/highlight these quantities on the
plots and spice outputs, and make a table with 5 columns: hand calcs, spice results
at 2.5V, spice results at 5.5V, %error at 2.5V, %error at 5.5V. Spice results with
different supply voltages should match to within 10%.
You may use Vicm=0.5V for both bode plots and .op
3. Transient analysis plot of gain=1, Vin= {0.4V,1V}, Vdd={2.5, 5.5} showing
gain error better than 0.1% (4 plots)
4. Transient analysis plot of gain=16, Vin={25mV, 2.1/16V}, Vdd={2,5, 5.5}
showing gain error better than 0.2% (4 plots).
5. Figure of merit calculation. FOM = 1/(T*Idd) . Show me the breakdown of
where your current goes, and explain what the limiting factor was in minimizing
T.
Note: All transient analyses must be done with the same period for Phi1 and Phi2.
Choose the minimum period that works for all 8 of the gain, Vin, and Vdd plots. That’s
the period T to use for your figure of merit.
Grading
Meeting performance specifications: 60%
Accuracy of hand calculations vs. simulation: 20%
Figure of merit: (Clock Period)*(total supply current): 20%
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