Download SiGe CVD, fundamentals and device applications SiGe CVD

SiGe CVD,
fundamentals and device
applications
Dr Derek Houghton
Aixtron Inc
ICPS, Flagstaff July 2004
ƒ OVERVIEW
1.
1. Introduction
Introduction
2.
2. SiGe
SiGe Market
Market Survey
Survey
3.
3. Fundamentals
Fundamentals of
of SiGe
SiGe CVD
CVD
4.
4. CVD
CVD Equipment
Equipment for
for SiGe
SiGe
5.
5. Device
Device aplications
aplications and
and
commercialization
commercialization
6.
6. SiGe
SiGe materials
materials engineering,
engineering, metrology
metrology
7.
7. Summary
Summary and
and Discussion
Discussion
SiGe’s Market Opportunity...
Si CMOS/BJTs
SiGe HBTs/CMOS?
III-V FETs/HBTs
Automotive
Road
Pricing
Collision
Avoidance
Navigation/Areospace
GPS
x-band
Radar
Communications
GSM
DCS
DECT
ISM
FRA WLAN DTH
WLAN
DBS
OC-48
FRA
OC-192 LMDS
G-Ethernet
0.1 0.2
0.5
1
2
5
10 20
50
Frequency (GHz)
100
SiGe HBT device structure and process description
Key
Key figures
figures of
of SiGe
SiGe HBT
HBT process
process
Only difference: Base
SiGe replaces Silicon
••
SiGe
SiGe BiCMOS
BiCMOS uses
uses SiGe
SiGe HBT
HBT ++ Si
Si
CMOS
CMOS
••
SiGe
SiGe HBT
HBT shows
shows same
same process
process as
as
Si
BT
with
exception
of
30-80
nm
Si BT with exception of 30-80 nm
thin
thin SiGe
SiGe base
base layer
layer (Ge
(Ge <25%)
<25%)
••
Growth
Growth rates
rates used
used are
are about
about 30
30
nm/min
(~
2
min
for
base
layer)
nm/min (~ 2 min for base layer)
••
Typically,
Typically, same
same LPCVD
LPCVD growth
growth
chambers
chambers can
can deposite
deposite both
both Si
Si and
and
SiGe
SiGe layers
layers
••
Depending
Depending on
on SiGe
SiGe HBT
HBT process,
process,
base
base layer
layer deposited
deposited either
either using
using
selective
selective or
or differential
differential epitaxy
epitaxy
SiGe‘s main market is telecommunication (wireless and datacom)
SiGe IC forecast by market, 2000 to 2005, in mil. US$
Comments
Comments
Industrial
1800
SiGe IC Market [Mio. US$]
1600
••
SiGe
SiGe viable
viable alternative
alternative to
to GaAs
GaAs
••
Main
Main markets
markets being
being targeted:
targeted:
Computer
Consumer
Communications
1400
1200
CAGR=+125%
1000
••
Cellular
Cellular // Cordless
Cordless // WLAN
WLAN
••
FO-Datacom
FO-Datacom
(MUX/DEMUX)
(MUX/DEMUX)
••
PC
PC interface
interface cards
cards // LAN
LAN
800
••
600
400
200
0
2000
2001
2002
YEAR
CAGR: Compound Average Growth Rate
2003
2004
2005
Future
Future trends:
trends:
••
integrated
integrated low
low power
power RFRFfront
front end
end of
of most
most handsets
handsets
••
First
First choice
choice for
for up/down
up/down
conversion
in
tuners/
conversion in tuners/
transceivers
transceivers
••
will
will dominate
dominate 40
40 Gbps
Gbps
Source: Strategies Unlimited, 1999
Strained Si: prototypes from Intel, IBM & UMC demonstrated
Almost all large Si-CMOS manufacturers are presenting cross sectional pictures of
CMOS transistors (with gate lengths between 65 and 90 nm) which use Strained-Si
technology. Intel and IBM use their own technology, whereas UMC is Amberwave’s
licensee
Strained-Si HeteroWafer® technology: process and actual status
Actual
Actual status
status Strained-Si
Strained-Si process
process
••
Strained
Strained Si
Si technology
technology enables
enables improvement
improvement
in
in CMOS
CMOS performance
performance and
and functionality
functionality via
via
replacement
replacement of
of the
the bulk,
bulk, cubic-crystal
cubic-crystal Si
Si
substrate
with
a
Si
substrate
that
contains
substrate with a Si substrate that contains aa
tetragonally
tetragonally distorted,
distorted, biaxially
biaxially strained
strained Si
Si
thin
thin film
film at
at the
the surface
surface
••
Different
Different types
types of
of processes
processes developed
developed and
and
patented
patented by
by the
the main
main players:
players: Amberwave
Amberwave
(IQE)
AIXTRON,
IBM,Toshiba
(IQE) - AIXTRON, IBM,Toshiba &
& Intel
Intel
••
First
First demos
demos of
of perfect
perfect working
working 52
52 Mbit
Mbit
SRAMs
SRAMs with
with 90
90 nm
nm CMOS
CMOS devices
devices on
on 300
300
mm
mm wafers
wafers available
available from
from Intel.
Intel. Ramp-up
Ramp-up of
of
Pentium
4
production
with
Str.-Si
planned
Pentium 4 production with Str.-Si planned for
for
2H/2003
!
2H/2003 !
••
Process
Process and
and substrate
substrate costs
costs still
still not
not 100%
100%
fixed.
fixed. Price
Price expectations
expectations for
for substrate
substrate from
from
IC
IC manufacturers
manufacturers still
still unknown
unknown
Strained Si process of Amberwave: One of the Strained Si pioneers
•Typically,
•Typically, 22 to
to 44 µm
µm thick
thick graded
graded SiGe
SiGe buffer
buffer layer,
layer, followed
followed
by
by thin
thin (<20
(<20 nm)
nm) strained
strained Si
Si channel
channel layer
layer
•Depending
•Depending on
on substrate
substrate Ge
Ge concentration,
concentration, clear
clear mobility
mobility and
and
transistor
transistor current
current drive
drive improvement
improvement
•• Through
Through Amberwave’s
Amberwave’s proprietary
proprietary chemical-mechanical
chemical-mechanical
polishing
polishing (CMP)
(CMP) intermediate
intermediate process,
process, SiGe
SiGe buffer
buffer layer
layer
surface
roughness
is
eliminated
before
Si
layer
deposi-tion,
surface roughness is eliminated before Si layer deposi-tion,
resulting
resulting in
in same
same quality
quality compared
compared to
to bulk
bulk Si
Si wafers
wafers
Strained Silicon CMOS technology
*SiGe deposited selectively,
Intel Pentium IV in production
Digital CMOS Electronic Market [Mio. US$]
Strained silicon mainly addresses high-end digital CMOS markets
Digital electronic market forecast and expected strained Si penetration, 2003 to 2007, in mil. US$
100000
CAGR*= 12.5%
Si Digital Signal Processors (DSPs)
60000
Si Micro-controllers (MCUs)
Si Microprocessors (MPUs)
40000
20000
Assumptions
Assumptions
0
100000
Strained Si based CMOS Market [Mio. US$]
Si FPGAs
80000
2003
2004
2005
Source: VLSI Research, 2002
2006
••
Main
Main application
application will
will be
be high-end
high-end
Microprocessors
Microprocessors like
like IBM‘s
IBM‘s
Power-PC,
Power-PC, SUN‘s
SUN‘s Sparc,
Sparc, AMD‘s
AMD‘s
Athlon,
Intel
Pentium
/
Itanium.
Athlon, Intel Pentium / Itanium.
••
Main
Main markets
markets being
being targeted:
targeted:
PCs,
PCs, workstations,
workstations, game
game
consoles,
consoles, other
other internet
internet
appliances
appliances
••
Future
Future trends:
trends: Strained
Strained Si
Si
penetrates
penetrates 3G/WLAN
3G/WLAN wireless
wireless
applications
applications (DSPs/MCUs)
(DSPs/MCUs)
2007
YEAR
80000
60000
CAGR*= >200%
40000
20000
0
2003
2004
2005
YEAR
Source: AIXTRON estimates
2006
2007
CAGR: Compound Average Growth Rate
Carbon and Oxygen concentrations (cm-3)
Effect of air exposure prior to HF passivation
10 21
RCA + 4 hours in air + HF dip
RCA + HF dip
1020
1019
Oxygen
1018
Carbon
1017
0
500
1000
1500
2000
Depth (Å)
2500
3000
3500
Partial pressure for oxygen incorporation from H2O and O2
AIXTRON‘s flexible epi systems for Strained Si / SiGe
Tricent®
Tricent SiGe Cluster Tool: 150, 200 or 300
mm
vs.
Multiwafer Reactor®
AIX 2600G3: up to 7x150 or 3x200 mm
SiGe UHVCVD
Quartz tube
SiH4
GeH4
B2H6
PH3
P~ 10-3 mbar
Tg<600C
wafers
molecular flow  uniform growth
sticking coefficients~10-3
UHV initial conditions, P~10-9 m bar
hydrogen terminated Si wafers at start
Hot wall UHVCVD Batch tool
Uniform Gas Distribution by
AIXTRON´s Closed Coupled Showerhead
Closed Coupled Showerhead Reactor
Growth Rate
Growth Rate
Horizontal Quarz Tube Reactor
Distance to gas inlet
Distance to gas inlet
SiGe Tricent®
Dual-Chamber Showerhead (pat. pend.)
Showerhead Detail
Water-Cooled Reactor Lid
N2/H2
Gas Mix
Showerhead
Process
Chamber
Wafer
Coated Graphite
Susceptor
TLid
TSH
TSubstr
Temperature Control Concept
SiGe Tricent®
Unique CVD chamber features
developed beyond industry standards
Showerhead
ƒƒ Showerhead
Temperaturecontrol
control
ƒƒTemperature
Tricent®
Customer Process Support
Clean
Room Wall
Process platform for
HBTs, HFETs and BiCMOS
- pure Silicon Growth
- differential SiGe:C growth
- selective SiGe:C growth
- SiGe on SOI
Cassette
Station
Temp
550-680°C
650-750°C
730-800°C
800-900°C
SiGe:C
SiGe
sel. SiGe
SEG
Process Gas Sources
SiH4 + GeH4 + SiCH6
SiH4 + GeH4
SiH2Cl2 + HCl + GeH4
SiH2Cl2 + HCl
SiGe HBT in a BiCMOS flow
Metallisation
Polysilicon Emitter
Base SiGe
Spacers
LOCOS
n+
N
+
EpitaxialLayer N
MOS
HBT
XTEM of Si deposition on Si/oxide
HBT base structure SIMS profiling
-3
10
10
18
10
17
SIMS analysis (cameca)
CVD-197
10
Ge
5
10
16
10
15
0
500
1000
Depth (Å)
0
1500
Germanium conc. (%)
Boron conc. (cm)
15
19
Gummel Plot, npn HBT
10
-3
Ic
Ib
IC, IB (A)
10
-5
A E = 0.6 x 1.2 micron
10
10
V
-7
CB
2
=0
-9
NPN11A, CVD-140
10
-11
Triangular SiGe base profile
VBE (V)
10
-13
0
0.2
0.4
0.6
0.8
1
1.2
1.4
CMOS transistor
Selective SiGe
Epitaxy
DC Houghton J.Appl.Phys.1991
Strained Silicon on
graded SiGe buffer
Amberwave
Ge%
Strained Si
Strained Silicon on
SOI wafer by layer
transfer
SOITEC
Strained Si
SiGe stack
SiGe grade
Si substrate
Si substrate
DCD x ray diffraction
SIMS profileStrained Si – Graded SiGe Buffer
Cs
Cascade Scientific
1E+23 12/04/2003
29Si+30Si->
70Ge
interface
1E+21
1E+04
SIMS
1E+03
1E+20
Low O and C background
No Interface peak
1E+19
1E+02
16O
1E+18
1E+01
1E+17
12C
1E+16
1E+00
0
2
4
6
Depth (microns)
8
10
Counts Per Second
1E+22
Concentration
1E+05
Sample A3
Strained Si layers
SiGe 40%
SiGe graded 5...40%
Pure Ge on Silicon substrates
Low defect density Ge without SiGe graded buffer
Ge
Si wafer
Cross sectional TEM
Plan view TEM (looking down
through Ge cap)
Growth Rate vs Germanium concentration
12
Rate @ 495°
Rate @ 525°
Rate @ 570°
570°C
10
Growth Rate (nm/minute)
8
525°C
6
4
495°C
2
0
0
5
10
15
20
25
Ge concentration (%)
30
35
40
Growth Rates vs Temperature
Growth rate (nm/minute)
10
Si0.7 Ge 0.3
600°C
Reactant Limited
Si
1
Ea = 1.6 ± 0.1 eV
495°C
0.1
1.1
1.15
1.2
1000/T (k-1)
1.25
1.3
1.35
SiGe/Si Multilayer structure
SiGe
silicon
Abrupt Si/SiGe interfaces
and precise control
of Ge % for “PIN
Photodetector”
SiGe Multi Quantum Wells (MQW)
Cs
Cascade Scientific
20 12/04/2003
1E+07
Sample A
SIMS
SIMS
16
1E+06
30Si->
14
12
1E+05
1E+04
10
70Ge
8
1E+03
6
1E+02
4
1E+01
2
0
1E+00
0
1000
2000
3000
Depth (angstroms)
4000
5000
Counts Per Second
Concentration (Ge %)
18
a5321d_lin.SWF
SiGe Multi Quantum Wells (MQW)
Comparison
Reference (Active)
A532-1
104
Intensity (cps)
XRD
• Double crystal X-ray data
• Period of super-lattice = 39.5nm
103
• Mean Ge fraction of structure
(Si spacers + SiGe Wells) = 0.6%
102
101
100
10-1
-3000
-2000
-1000
1000
0
th\2th (sec)
2000
3000
Measured by
Raman Scattering
Raman Scattering
Fourier transform low temperature photoluminescence apparatus.
Fourier
Spectrometer
Moving
Mirror
Germanium
Detector
Beamsplitter
Excitation Source
Laser
Cryostat
SAMPLE
PL spectra from SiGe HBT transistors
Patterned
Wafer
Vertical
Profile SiGe
Photoluminescence Intensity
50 nm
SiGe
Layer
Si Surround
SiGe
Etched Off
900
1000
Energy - meV
1100
PL of SiGe HBT
SiGe PL Threshold &
Saturation Effects
0.1
Sample A
As Grown
0.01
Sample B
Annealed
Sample B
As Grown
1E-3
15
16
10
17
18
10
10
-1
-2
Incident Photon Flux / s cm
10
PL Spectra
Sample B Annealed
TO
15%
100
16
-1
NP
TA
Carrier
Wavefunction
Si
10
16
Ge Profile
-2
3.5x10 s cm
PL Intensity
SiGe PL Peak Height
1
-1
20 nm
-2
1.4x10 s cm
1
980
Si
1000
1020
1040
Energy / meV
1060
SiGe - Graded Composition
Si
Photoluminescence Mapping of
Composition and Bandgap on a 6" wafer
Sample point
"NP" energy
(meV)
Energy
bandgap (meV)
Composition
(% of Ge)
a
1080
1092.2
8.97
b
1082.5
1094.7
8.69
c
1085.2
1097.4
8.39
d
1083.3
1095.5
8.60
e
1082.5
1094.7
8.69
f
1084.8
1097.0
8.44
g
1083.7
1095.9
8.56
h
1079
1091.2
9.08
h
g
d
c
b
f
e
a
Auger Electron Spectroscopy
Of Graded germanium concentration profiles
Germanium atomic concentration (%)
20
Actual profile
Ideal profile
15
HBT profile
FET profile
10
5
0
0
2000
4000
6000
Sputtering time (s)
8000
1 10
4
Trends in “novel” epitaxy in Si based materials
For graded SiGe buffers
Low CoO, defect density reduction, flatness
Thin SiGe epitaxy with defect nucleation layer
SOI substrates
Lower thermal budget in CMOS
low leak rate tools
new precursors with high GR at <600C, e.g.trisilane
Selectivity, patterned wafers, SOI substrates
High mobility channels
Pure Ge, III-V’s on Ge on SiGe, epitaxial metals