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BJT Amplifier Design
I. Overview
In Lab 3 (BJT Amplifier) and Lab 4 (FET Amplifier) you will design a two-stage amplifier as
shown in Figure 1. The first stage is a FET amplifier and the second stage is a BJT amplifier. The gain
of the two-stage amplifier is the product of the gains of the single FET and BJT stages.
In Lab 3 you will design, simulate and build a single stage BJT amplifier in two weeks. You
will take another two weeks in Lab 4 to design, simulate and build a single stage JFET amplifier and
connect with the BJT stage to form a two-stage amplifier.
Figure 1. Two-Stage Amplifier Schematic with Feedback
II. BJT Amplifier Design
You will design a common emitter (CE) BJT amplifier shown in Figure 2. Based on the
current-voltage characteristic of the individual BJT (2N2222), each group should select a proper
operation point and then determine the values of the biasing resistors, such as R4, R5, R6 and R7.
DC power supply VCC = 20 volts and load resistor RL = 10 k.
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Figure 2. Common Emitter Bipolar Junction Transistor Amplifier
2.1 . Task of the first week:
A. Obtain current-voltage characteristic of BJT and determine the load line and Q-point
a. Each group picks up one npn BJT (2N2222) and plugs it into the curve tracer. The settings of
curve tracer are as following: type  npn; Vce-max  20V; Ic-max  10mA; Ib/step 
10uA; # of steps  10; Rload  0.25 ; power  0.5 watt.
b. Use Cursor Function to select an operation point (Q-point) with VCE = VCC/3 and the value of IC
in the range of 2 mA  5 mA. Display the data of the Q-point, IB, VCE, IC and hfe (same as
current gain ) on the screen and obtain a hard copy of the screen.
c. Draw the DC load line on your printout by connecting the Q-point and the point with VCE =
20V and IC = 0mA. Find the AC output resistance ro = 1 / k, where k is the slope of the
output curve (NOT the slope of the DC load line) of the transistor.
B. Determine the DC biasing and AC voltage gain
d. Determine collect resistance R6 and the emitter resistance R7
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VCC  VR6  VCE  VR7  I C  R6  VCE  I E  R7
IC    I E 

 1
 IE  IE
V
Selecting the Q - point by the rule of thumb : VR6  VR7  VCE  CC
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V /3
V /3
Then , R6  CC
and R7  CC
IC
IE
(VCC is given as 20 volts. IC is the collect current at the Q-point you select in Step b)
e. Determine the DC biasing voltage, VB, at the base the BJT
The base potential VB is higher than the emitter potential VE by VBE. And VE is equal to the
voltage across the emitter resistance R7.
VB  VE  0.7
V
VE  VR7  CC
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f. Determine the base bias resistance R4 and R5
The base potential VB is determined by the DC voltage supply VCC and the voltage divider
consisted of R4 and R5.
VB  VCC
R5
R4  R5
The value of VB is determined from Step e. By assuming the value of R5, such as 5 k, R4 can
be calculated out from the above equation.
g. Draw the small signal model of the transistor and the AC equivalent circuit of Figure 2. Find
the transconductance gm, AC input resistor r and the AC voltage gain Av.
I
I q
gm  C  C
VT
K T
r 
 VT
IC
Av  Vout / Vin   g m  ( R6 // ro // RL )
h. Create and simulate the schematic of Figure 2 in OrCAD – Capture. All the capacitors have the
value of 100 uF. The AC input is VSIN with settings: Voffset = 0, Vampl = 5mV and f = 1kHz.
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The output of the amplifier is loaded with a resistor, RL, of 10 k. Capture the input and
output voltages labeled with the peak-peak voltages and voltage gain.
i. Compare the voltage gain from simulation with that from the theoretical calculation.
j. Change the amplitude of the AC input, Vampl = 50mV. Capture the input and output
voltages labeled with the peak-peak voltages and voltage gain. Is there any change in the
waveform of the output voltage?
2.2 . Task of the second week:
k. Fabricate and test the hardware circuit as shown in Figure 2. Add one load resistor, RL = 10 k,
between the output terminal (Vout) and ground. The input voltage from Function Generator is
Vamp = 50 mV, Voffset = 0 V, f = 1 kHz. Capture the input and output voltages and show
the peak-peak voltages for both signals. Calculate the voltage gain.
III. Report
One lab report is required for the two-week experiments.

Introduction

Capture from curve tracer. Please indicate the load line, Q-point and the values of IC, VCE, IB, β,
α and ro

Theoretical calculation of gm, r and Av

Schematic from OrCAD - Capture

Simulation results for Vampl = 5 mV and Vampl = 50 mV. Please show input and output
voltages on one plot and indicate both the peak-peak voltages and the voltage gain Av

Hardware Measurements. Capture of input (Vamp = 50 mV from Function Generator) and
output voltages with Vp-p displayed. Calculated the voltage gain Av.

Discussion and conclusion
 Comments on the voltage gains from theoretical calculation and simulation (Vampl = 5mV)
 Comments on the voltage gains from simulation for Vampl = 5 mV and Vampl = 50 mV
 Comments on the voltage gains from hardware measurements
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