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Transcript
Low Cost, Precision JFET
Input Operational Amplifiers
ADA4000-1/ADA4000-2/ADA4000-4
Data Sheet
PIN CONFIGURATIONS
High slew rate: 20 V/μs
Fast settling time
Low offset voltage: 1.70 mV maximum
Bias current: 40 pA maximum
±4 V to ±18 V operation
Low voltage noise: 16 nV/Hz
Unity gain stable
Common-mode voltage includes +VS
Wide bandwidth: 5 MHz
OUT 1
V– 2
ADA4000-1
5
V+
4
–IN
TOP VIEW
(Not to Scale)
+IN 3
05791-001
FEATURES
8
NC
–IN 2
NC 1
ADA4000-1
7
V+
+IN 3
TOP VIEW
(Not to Scale)
6
OUT
5
NC
V– 4
APPLICATIONS
NC = NO CONNECT
Reference gain/buffers
Level shift/driving
Active filters
Power line monitoring/control
Current/voltage sense or monitoring
Data acquisition
Sample-and-hold circuits
Integrators
05791-002
Figure 1. 5-Lead TSOT (UJ-5)
OUT A 1
8
+V
–IN A 2
ADA4000-2
7
OUT B
+IN A 3
TOP VIEW
(Not to Scale)
6
–IN B
5
+IN B
–V 4
05791-027
Figure 2. 8-Lead SOIC (R-8)
OUT A 1
Additional applications for the ADA4000-1/ADA4000-2/
ADA4000-4 include electronic instruments, automated test
equipment (ATE) amplification, buffering, integrator circuits,
instrumentation-quality photodiode amplification, and fast
precision filters (including phase-locked loop filters). The devices
also include utility functions, such as reference buffering, level
shifting, control input/output interface, power supply control,
and monitoring functions.
–V 4
+V
ADA4000-2
7
OUT B
TOP VIEW
(Not to Scale)
6
–IN B
5
+IN B
Figure 4. 8-Lead MSOP (RM-8)
OUT A 1
14
OUT D
–IN A 2
13
–IN D
ADA4000-4
12
+IN D
TOP VIEW
(Not to Scale)
11
–V
10
+IN C
–IN B 6
9
–IN C
OUT B 7
8
OUT C
+IN A 3
+V 4
+IN B 5
05791-029
The ADA4000-1/ADA4000-2/ADA4000-4 are junction field
effect transistor (JFET) input operational amplifiers featuring
precision, very low bias current, and low power. Combining
high input impedance, low input bias current, wide bandwidth,
fast slew rate, and fast settling time, the ADA4000-1/ADA40002/ADA4000-4 are ideal amplifiers for driving analog-to-digital
inputs and buffering digital-to-analog converter outputs. The
input common-mode voltage includes the positive power supply,
which makes the device an excellent choice for high-side signal
conditioning.
+IN A 3
8
Figure 5. 14-Lead SOIC (R-14)
14 OUT D
OUT A 1
–IN A 2
+IN A 3
+V 4
+IN B
5
13 –IN D
ADA4000-4
TOP VIEW
(Not to Scale)
12 +IN D
11 –V
10 +IN C
–IN B 6
9
–IN C
7
8
OUT C
OUT B
05791-030
GENERAL DESCRIPTION
–IN A 2
05791-028
Figure 3. 8-Lead SOIC (R-8)
Figure 6. 14-Lead TSSOP (RU-14)
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADA4000-1/ADA4000-2/ADA4000-4
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Power Sequencing .........................................................................5 Applications ....................................................................................... 1 ESD Caution...................................................................................5 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................6 Pin Configurations ........................................................................... 1 Applications Information .............................................................. 10 Revision History ............................................................................... 2 Output Phase Reversal and Input Noise ................................. 10 Specifications..................................................................................... 3 Capacitive Load Drive ............................................................... 10 Electrical Characteristics ............................................................. 3 Settling Time ............................................................................... 11 Absolute Maximum Ratings............................................................ 5 Outline Dimensions ....................................................................... 12 Thermal Resistance ...................................................................... 5 Ordering Guide .......................................................................... 14 REVISION HISTORY
3/16—Rev. A to Rev. B
Change to Figure 12 Caption .......................................................... 6
Changes to Output Phase Reversal and Input Noise Section
and Capacitive Load Drive Section .............................................. 10
Updated Outline Dimensions ....................................................... 13
3/09—Rev. 0 to Rev. A
Changes to Input Voltage Range Parameter ................................. 4
Changes to Common-Mode Rejection Ration Parameter .......... 4
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 14
5/07—Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet
ADA4000-1/ADA4000-2/ADA4000-4
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = ±15.0 V, VCM = VS/2 V, TA = 25°C, unless otherwise specified.
Table 1.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Test Conditions/Comments
Min
VOS
Typ
Max
Unit
0.2
1.70
3.0
40
170
4.5
40
80
500
+15
mV
mV
pA
pA
nA
pA
pA
pA
V
dB
dB
dB
µV/°C
−40°C ≤ TA ≤ +125°C
Input Bias Current
IB
5
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
2
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
Open-Loop Gain
Offset Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
IVR
CMRR
AVO
ΔVOS/ΔT
VOH
VOL
−11 V ≤ VCM ≤ +15 V
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ, VO = ±10 V
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to ground
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to ground
−40°C ≤ TA ≤ +125°C
−11
80
100
13.60
13.40
13.90
−13.4
ISC
PSRR
ISY
100
100
110
2
±28
VS = ±4.0 V to ±18.0 V
82
92
1.35
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
INPUT IMPEDANCE
Differential Mode
Common Mode
−13.0
−12.80
1.65
1.80
V
V
V
V
mA
dB
mA
mA
SR
GBP
ΦM
VI = 10 V, RL = 2 kΩ
20
5
60
V/µs
MHz
Degrees
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
1
16
0.01
µV p-p
nV/√Hz
pA/√Hz
10||4
103||5.5
GΩ||pF
GΩ||pF
(R||C)IN-DIFF
(R||C)INCM
Rev. B | Page 3 of 16
ADA4000-1/ADA4000-2/ADA4000-4
Data Sheet
VS = ±5 V, VCM = VS/2 V, TA = 25°C, unless otherwise specified.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Test Conditions/Comments
Min
VOS
Typ
Max
Unit
0.20
1.70
3.0
40
170
3
40
80
500
+5.0
mV
mV
pA
pA
nA
pA
pA
pA
V
dB
dB
dB
µV/°C
−40°C ≤ TA ≤ +125°C
Input Bias Current
IB
5
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
2
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
Open-Loop Gain
Offset Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
POWER SUPPLY
Supply Current/Amplifier
IVR
CMRR
AVO
ΔVOS/ΔT
VOH
VOL
−1.0 V ≤ VCM ≤ +5.0 V
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ, VO = ±2.5 V
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to ground
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to ground
−40°C ≤ TA ≤ +125°C
ISC
−1.0
72
106
4.0
3.80
80
80
114
2
4.20
−3.45
±28
ISY
1.25
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
INPUT IMPEDANCE
Differential Mode
Common Mode
−3.20
−3.00
1.65
1.80
V
V
V
V
mA
mA
mA
SR
GBP
ΦM
VI = 10 V, RL = 2 kΩ
20
5
55
V/µs
MHz
Degrees
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
1
16
0.01
µV p-p
nV/√Hz
pA/√Hz
10||4
103||5.5
GΩ||pF
GΩ||pF
(R||C)IN-DIFF
(R||C)INCM
Rev. B | Page 4 of 16
Data Sheet
ADA4000-1/ADA4000-2/ADA4000-4
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 10 sec)
Rating
±18 V
±V supply
±V supply
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT (UJ-5)
8-Lead SOIC (R-8)
8-Lead MSOP (RM-8)
14-Lead SOIC (R-14)
14-Lead TSSOP (RU-14)
θJA
172.92
112.38
141.9
88.2
114
θJC
61.76
61.6
43.7
56.3
23.3
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
POWER SEQUENCING
The operational amplifier supply voltages must be established
simultaneously with, or before, any input signals are applied. If
this is not possible, the input current must be limited to 10 mA.
ESD CAUTION
Rev. B | Page 5 of 16
ADA4000-1/ADA4000-2/ADA4000-4
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
50
VS = ±15V
TA = 25°C
VCM = 0V
45
NUMBER OF AMPLIFIERS
40
35
30
25
20
15
35
30
25
20
15
10
10
5
5
0
–2.0
–1.5
–1.0
–0.5
0
0.5
OFFSET VOLTAGE (mV)
1.0
1.5
2.0
0
–2.0
05791-003
NUMBER OF AMPLIFIERS
40
VS = ±5V
TA = 25°C
VCM = 0V
45
–1.5
–1.0
0.5
–0.5
0
OFFSET VOLTAGE (mV)
1.0
Figure 10. Input Offset Voltage Distribution, VS = ±5 V
Figure 7. Input Offset Voltage Distribution, VS = ±15 V
14
18
VS = ±5V
VS = ±15V
16
12
NUMBER OF AMPLIFIERS
14
NUMBER OF AMPLIFIERS
2.0
1.5
05791-018
50
12
10
8
6
10
8
6
4
4
2
6
8
10
12
TCVOS (µV/°C)
14
16
18
20
0
2
4
6
8
10
12
TCVOS (µV/°C)
14
16
18
20
Figure 11. Offset Voltage Drift Distribution, VS = ±5 V
Figure 8. Offset Voltage Drift Distribution, VS = ±15 V
80
60
135
60
135
40
90
40
90
45
20
60°
100k
1M
FREQUENCY (Hz)
10M
–45
100M
20
180
45
0
–20
1k
05791-010
10k
VS = ±5V
TA = 25°C
CL = 35pF
55°
0
0
–20
1k
GAIN (dB)
VS = ±15V
TA = 25°C
CL = 35pF
PHASE MARGIN (Degrees)
180
80
GAIN (dB)
0
Figure 9. Open-Loop Gain and Phase Margin vs. Frequency, VS = ±15 V
PHASE MARGIN (Degrees)
4
2
0
10k
100k
1M
FREQUENCY (Hz)
10M
–45
100M
05791-020
0
05791-004
0
05791-019
2
Figure 12. Open-Loop Gain and Phase Margin vs. Frequency, VS = ±5 V
Rev. B | Page 6 of 16
Data Sheet
ADA4000-1/ADA4000-2/ADA4000-4
120
100
VS = ±15V
TA = 25°C
VS = ±5V
TA = 25°C
100
80
CMRR (dB)
CMRR (dB)
80
60
60
40
1k
10k
100k
10M
1M
FREQUENCY (Hz)
Figure 13. Common-Mode Rejection Ratio vs. Frequency, VS = ±15 V
15
20
1k
05791-013
20
100
1M
10M
Figure 16. Common-Mode Rejection Ratio vs. Frequency, VS = ±5 V
4
3
2
VOLTAGE (V)
5
VOLTAGE (V)
100k
FREQUENCY (Hz)
VS = ±15V
AV = +1
RL = 2kΩ
TA = 25°C
10
10k
05791-021
40
0
1
VS = ±5V
AV = –1
RL = 2kΩ
TA = 25°C
0
–1
–5
–2
–10
–15
TIME (1µs/DIV)
05791-023
05791-015
–3
–4
TIME (1µs/DIV)
Figure 17. Large Signal Transient Response, VS = ±5 V
Figure 14. Large Signal Transient Response, VS = ±15 V
VS = ±5V
CL = 300pF
AV = +1
TA = 25°C
TIME (2µs/DIV)
Figure 18. Small Signal Transient Response, VS = ±5 V
Figure 15. Small Signal Transient Response, VS = ±15 V
Rev. B | Page 7 of 16
05791-024
TIME (2µs/DIV)
05791-016
VOLTAGE (20mV/DIV)
VOLTAGE (20mV/DIV)
VS = ±15V
CL = 300pF
AV = +1
TA = 25°C
ADA4000-1/ADA4000-2/ADA4000-4
Data Sheet
1.40
3.5
TA = 25°C
TA = 25°C
NO LOAD
1.35
SUPPLY CURRENT (mA)
2.5
2.0
1.5
1.25
1.20
1.15
±6
±7
±8
±9
±10
±11
±12
±13
±14
±15
SUPPLY VOLTAGE (V)
1.10
±4
05791-006
1.0
±5
1.30
±5
±6
±7
±8
±9
±10
±11
±12
±13
±14
±15
SUPPLY VOLTAGE (V)
05791-008
INPUT BIAS CURRENT (pA)
3.0
Figure 22. Supply Current vs. Supply Voltage
Figure 19. Input Bias Current vs. Supply Voltage
16
10000
14
|VOL| VS = ±15V
12
VOH
OUTPUT VOLTAGE (V)
100
10
VS = ±15V
1
8
6
4
|VOL|
2
VOH
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
0
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
LOAD CURRENT (mA)
Figure 23. Output Voltage vs. Load Current
Figure 20. Input Bias Current vs. Temperature
120
1.44
VS = ±5V, ±15V
100
1.40
80
VS = ±15V
PSRR–
PSRR (dB)
1.36
1.32
60
PSRR+
40
1.28
20
VS = ±5V
1.24
–25
–10
5
20
35
50
65
80
95
TEMPERATURE (°C)
110
125
Figure 21. Supply Current vs. Temperature
–20
100
1k
10k
100k
FREQUENCY (Hz)
Figure 24. PSRR vs. Frequency
Rev. B | Page 8 of 16
1M
10M
05791-014
1.20
–40
0
05791-012
SUPPLY CURRENT (mA)
VS = ±5V
05791-009
0.1
–40
10
VS = ±5V
05791-005
INPUT BIAS CURRENT (pA)
1000
Data Sheet
ADA4000-1/ADA4000-2/ADA4000-4
0.6
VS = ±5V, ±15V
TA = 25°C
VS = ±5V, ±15V
0.4
V p-p (µV)
0.2
10
0
–0.2
1
100
10
1
1k
10k
FREQUENCY (Hz)
–0.6
–5
0
1
2
3
4
5
Figure 28. 0.1 Hz to 10 Hz Input Voltage Noise
50
VS = ±15V
TA = 25°C
VS = ±5V, ±15V
AV = +100
40
CLOSED-LOOP GAIN (dB)
100
80
ZOUT (Ω)
–1
–2
TIME (Seconds)
Figure 25. Voltage Noise Density vs. Frequency
120
–3
–4
05791-025
–0.4
05791-026
VOLTAGE NOISE DENSITY (nV/√Hz)
100
60
40
Av = +100
30
AV = +10
20
10
AV = +1
0
–10
20
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 26. Output Impedance vs. Frequency
VIN = 100mV p-p
VS = ±5V, ±15V
RL = 0
AV = +1
+OVERSHOOT
30
–OVERSHOOT
20
10
0
200
400
600
800
LOAD CAPACITANCE (pF)
1000
05791-022
OVERSHOOT (%)
40
0
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 29. Closed-Loop Gain vs. Frequency
60
50
–30
100
Figure 27. Overshoot vs. Load Capacitance
Rev. B | Page 9 of 16
100M
05791-011
0
1k
–20
Av = +1
05791-017
Av = +10
ADA4000-1/ADA4000-2/ADA4000-4
Data Sheet
APPLICATIONS INFORMATION
Phase reversal is a change of polarity in the transfer function of
the amplifier. This can occur when the voltage applied at the
input of the amplifier exceeds the maximum common-mode
voltage. Phase reversal happens when the device is configured
in the gain of 1.
Most JFET amplifiers invert the phase of the input signal if the
input exceeds the common-mode input. Phase reversal is a
temporary behavior of the ADA4000-1/ADA4000-2/ADA4000-4
family. Each device returns to normal operation by bringing back
the common-mode voltage. The cause of this effect is saturation
of the input stage, which leads to the forward-biasing of a draingate diode. In noninverting applications, a simple fix for this is
to insert a series resistor between the input signal and the noninverting terminal of the amplifier. The value of the resistor
depends on the application, because adding a resistor adds to the
total input noise of the amplifier. The total noise density of the
circuit is
The advantage of this compensation method is that the swing at
the output is not reduced because RS is out of the feedback network,
and the gain accuracy does not change. Depending on the
capacitive loading of the circuit, the values of RS and CS change,
and the optimum value can be determined empirically. In
Figure 31, the oscilloscope image shows the output of the
ADA4000-1/ADA4000-2/ADA4000-4 family in response to
a 400 mV pulse. The circuit is configured in the unity gain
configuration with 500 pF in parallel with 10 kΩ of load
capacitive.
INPUT SIGNAL
VOLTAGE (200mV/DIV)
OUTPUT PHASE REVERSAL AND INPUT NOISE
enTOTAL  en  in RS   4kTRS
OUTPUT SIGNAL
where:
en is the input voltage noise density of the device.
in is the input current noise density of the device.
RS is the source resistance at the noninverting terminal.
k is Boltzmann’s constant (1.38 × 10−23 J/K).
T is the ambient temperature in Kelvin (T = 273 + °C).
TIME (1µs/DIV)
Figure 31. Capacitive Load Drive Without Snubber Network
In general, it is good practice to limit the input current to less
than 5 mA to avoid driving a great deal of current into the
amplifier inputs.
When the snubber circuit is used, the overshoot is reduced from
30% to 6% with the same load capacitance. Ringing is virtually
eliminated, as shown in Figure 32. In this circuit, RS is 41 Ω and
CS is 10 nF.
CAPACITIVE LOAD DRIVE
OUTPUT SIGNAL
+15V
TIME (1µs/DIV)
U1
Figure 32. Capacitive Load with Snubber Network
V+
ADA4000-1
2
V–
–15V
1
RS
CS
CL
500pF
0
RL
10kΩ
05791-031
V1
400mV p-p
0
SNUBBER NETWORK
Figure 30. Snubber Network Configuration
Rev. B | Page 10 of 16
05791-033
However, as with most amplifiers, driving larger capacitive loads
in a unity gain configuration can cause excessive overshoot and
ringing. A simple solution to this problem is to use a snubber
network (see Figure 30).
VOLTAGE (200mV/DIV)
INPUT SIGNAL
The ADA4000-1/ADA4000-2/ADA4000-4 are stable at all gains
in both inverting and noninverting configurations. The devices
are capable of driving up to 1000 pF of capacitive loads without
oscillations in unity gain configurations.
3
05791-032
2
2
Data Sheet
ADA4000-1/ADA4000-2/ADA4000-4
SETTLING TIME
Settling time is the amount of time it takes the amplifier output
to reach and remain within a percentage of the final value. This
is an important parameter in data acquisition systems. Because
most bipolar DAC converters have current output, an external
operational amplifier is required to convert the current to voltage.
Therefore, the amplifier settling time plays a role in the total
settling time of the output signal. A good approximation for the
total settling time is
5V/DIV
200mV/DIV
The ADA4000-1/ADA4000-2/ADA4000-4 settle to within 0.1%
of their final value in less than 1.2 μs. The settling time has been
tested by using the configuration circuit in Figure 34.
05791-035
t S Total  (t S DAC)2  (t S AMP )2
200ns/DIV
Figure 33. Settling Time Measurement Using the False Summing Node Method
The input signal is a 10 V pulse and the output is the error
signal for the settling time shown in Figure 33.
+15V
+15V
3
V+
10kΩ
ADA4000-1
2
1
8
V+
10kΩ
AD828
V–
10V p-p
–15V
10kΩ
VOUT
V–
4
V1
–15V
10kΩ
20kΩ
1kΩ
Figure 34. Settling Time Test Circuit
Rev. B | Page 11 of 16
05791-034
0
ADA4000-1/ADA4000-2/ADA4000-4
Data Sheet
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
5
1
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
0.50 (0.0196)
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
45°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 35. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
2.90 BSC
5
4
2.80 BSC
1.60 BSC
1
2
3
0.95 BSC
1.90
BSC
*0.90 MAX
0.70 MIN
0.10 MAX
0.50
0.30
0.20
0.08
SEATING
PLANE
8°
4°
0°
0.60
0.45
0.30
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 36. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions shown in millimeters
Rev. B | Page 12 of 16
100708-A
*1.00 MAX
Data Sheet
ADA4000-1/ADA4000-2/ADA4000-4
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.23
0.09
6°
0°
0.40
0.25
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 37. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.20
0.09
0.30
0.19
0.75
0.60
0.45
8°
0°
SEATING
PLANE
061908-A
1.05
1.00
0.80
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 38. 14-Lead Standard Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
8.75 (0.3445)
8.55 (0.3366)
8
14
1
7
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 39. 14-Lead Standard Small Outline Package [SOIC_N]
(R-14)
Dimensions shown in millimeters
Rev. B | Page 13 of 16
060606-A
4.00 (0.1575)
3.80 (0.1496)
ADA4000-1/ADA4000-2/ADA4000-4
Data Sheet
ORDERING GUIDE
Model 1
ADA4000-1ARZ
ADA4000-1ARZ-R7
ADA4000-1ARZ-RL
ADA4000-1AUJZ-R2
ADA4000-1AUJZ-R7
ADA4000-1AUJZ-RL
ADA4000-2ARZ
ADA4000-2ARZ-R7
ADA4000-2ARZ-RL
ADA4000-2ARMZ
ADA4000-2ARMZ-RL
ADA4000-4ARZ
ADA4000-4ARZ-R7
ADA4000-4ARZ-RL
ADA4000-4ARUZ
ADA4000-4ARUZ-RL
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead TSSOP
14-Lead TSSOP
Z = RoHS Compliant Part.
Rev. B | Page 14 of 16
Package Option
R-8
R-8
R-8
UJ-5
UJ-5
UJ-5
R-8
R-8
R-8
RM-8
RM-8
R-14
R-14
R-14
RU-14
RU-14
Branding
A14
A14
A14
A1H
A1H
Data Sheet
ADA4000-1/ADA4000-2/ADA4000-4
NOTES
Rev. B | Page 15 of 16
ADA4000-1/ADA4000-2/ADA4000-4
Data Sheet
NOTES
©2007–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05791-0-3/16(B)
Rev. B | Page 16 of 16