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A Distributed Timing and Synchronization System for EAST
Zhang Zuchao, Ji Zhenshan, Xiao Bingjia, Wang Yong, Yang Fei
Institute of Plasma Physics, Chinese Academy of Sciences, Hefei, Anhui, PR. China
The Distributed Timing and Synchronization System (DTSS) plays an important role in
Experimental Advanced Superconducting Tokamak(EAST), which is one of the national
key fusion research facilities in China. This system synchronizes each subsystem of EAST
by using reference clock and trigger. A prototype DTSS module has been developed based
on PXI bus and RIO devices. The DTSS can provide reference clock in frequency up to 80
MHz. The trigger can be pre-defined from 1ms to 6872 s with 10 ns accuracy. In addition,
this system can acquire, process signals, and send output or command to other systems. The
DTSS has been successfully applied to 2010 fall EAST experiment, and the results
confirmed its accuracy and reliability. After the analysis of system requirement, the
architecture of the DTSS and the technical implementation based on PXI is presented in
this paper.
Keywords: DTSS; EAST; PXI; RIO
1. Introduction
The China national project of Experimental Advanced Superconducting Tokomak (EAST) is a full
superconducting tokamak with a non-circle cross-section of the vacuum vessel and the active cooling
plasma-facing components
[1]
. This project consists of many subsystems such as power supply system,
plasma current drive and heating system, which are all located in different places and need to be run by
a synchronization control mechanism at specified times to maintain the EAST fusion device operation
stability.
Distributed Timing and Synchronization System (DTSS) is an expandable and real-time control
mechanism which has been developed for the EAST fusion experiment with four functions: (i)to
provide the timing signals, ensure each subsystem works in the same reference clock (ii)to provide the
trigger signals, control the participation in the experiment of subsystems in time series (iii)to perform
the processing and recording of externally generated events. (iv) to acquire the outputs of itself , inspect
the operation state of DTSS automatically.
The DTSS has been designed in a star-type topology [2]with a central node and several local nodes
which are all implemented in the PXI and FPGA industry devices, since the nodes are located in harsh
electromagnetic environment, and it needs more node channels. A PXI chassis with a controller, a
timing I/O module and a multifunction RIO (reconfigurable I/O) with FPGA device are used in a DTSS
local node. The central and local node have similar configuration except that the former has two timing
I/O modules, and the additional module is used for producing synchronization clock.
Based on PXI and FPGA, the DTSS provides reference clocks (from 1MHz to 80 MHz in 1MHz
steps) and delay trigger signals (from 1ms to 6972s in 1ms steps) to the subsystems. The architecture of
the DTSS and the description of the DTSS’ units will be presented in the following sections.
2. System architecture
The DTSS is an independent system which interacts with the Central Control System (CCS) of the
EAST closely, it consists of a console host, a database server, the synchronized optical network, one
central PXI node (CPN), several local PXI nodes (LPNs) and some isolation & drive modules. The
structure of the DTSS with one LPN is illustrated in detail in Fig1.
150m
Isolation & Drive Module
150 m
Console Host
Central PXI Node
EAST Control Network
150m
150 m
Central Control System
Isolation & Drive Module
Database Server
Local PXI Node
Fig.1 Hardware structure of the DTSS
The DTSS operates as follows: On the console host, set by the operator, parameters of each node
are transmitted to the PXI nodes and database server through the gigabit EAST control network. For
synchronization of the PXI nodes, system trigger signal from the CCS and synchronization clock
signals from the CPN are distributed over the synchronized optical network. The synchronized optical
network will be detailed in Section 3.3. On receiving the system trigger signal, clock counters in the
PXI nodes begin to count the tick, and pulse generator module in RIO device outputs the signals to the
subsystems at pre-defined time. The acquisition module acquires the output of the DTSS and stores the
data in the local disk.
The DTSS software architecture is based on a set of software applications (see Fig 2) which run in
both the Windows and LabVIEW Real-Time system, namely HOST VI, RT VI and FPGA VI. HOST
VI executes on the console host, providing the graphical user interface (GUI) of the parameter
management to the operator. Deployed to the PXI controller, RT VI is used for handling the FPGA VI
interface, the data compress and so on. FPGA VI aims at customizing the RIO device to realize the
output of the pulse sequence, the acquisition of the signals and responds to the external events.
Windows System
LabVIEW Real-Time System Reconfigurable FPGA
Console Host
HOST VI
· GUI
PXI Controllers
Network
Communication
for manage
LabVIEW
for Windows
HOSTVIVI
HOST
RT
VI
FPGA
Interface
•Clock signals generator
•Data LZO compress
•Event record
LabVIEW
Real-Time
PXI RIO Targets
HOSTVIVI
HOST
FPGA
VI
•Pulses generator
•Signals acquisition
•Event process
LabVIEW
FPGA
Fig.2 Software architecture of the DTSS
3. The description of the DTSS units
3.1 Console host
The console host is a computer in which the GUI of the parameter management works, and it’s
linked by EAST control network. The GUI of the parameter management is programmed in the
LabVIEW graphics language, assists the operator in setting and managing the PXI nodes’ parameters.
The changed parameters which modified by the operator are delivered to all of the PXI nodes through
transmission control protocol/internet protocol (TCP/IP) socket
[3]
. The GUI utilizes the shot number,
which received from the CCS, as the software trigger to send the parameters store in the database
server where the operator can inquire each channel’s information.
3.2 Database server
MySQL is a relational database management system (RDBMS) based on SQL (Structured Query
Language). It’s an ideal choice to deal with data concurrency and stability which runs as a server in the
platform of Linux and provides multi-thread and multi-user access mechanism. A database named
dtss_data is set up in the server, which includes a main table called dtss_data_db. This table covers
pre-defined characteristics, such as channel_id, channel_name, delay, pulse, sig_polarity, en/disable
and shotno, etc. Channel_id is defined as the index of the table, to improve the speed of the data
retrieval and renewal. User can only select and update permission to access the database for security [4].
3.3 Synchronized optical network
For synchronization of the PXI nodes, a synchronized optical network has been set up by using
50/125μm multi-model fibers. The synchronized optical network includes two parts: One is delivering
a “Start/Stop” signal which generated by the CCS to drive all the PXI nodes’ counters work/stop at the
same time; the other is used to distribute the synchronization clock signals to LPNs for phase lock to
the oscillator of the CPN. All fiber lengths are made the same to guarantee that all signals arrive at
different nodes with the same delay
[5]
. The use of fibers removes ground loops among different
systems, eliminates noise pick-up and provides high voltage isolation among different systems.
3.4 Central PXI node
The CPN is implemented in a PXI-1042Q 8-slot chassis which is equipped with a PXI-8110
controller running on LabVIEW Real-Time system, two PXI-6608 timing I/O modules, and a
PXI-7842R multifunction RIO device. The first PXI-6608 is 5V square wave at 10 MHz, which
generates several synchronization clock signals, is applied to the backplane of each PXI node (includes
the CPN) over the synchronized optical network. The second timing I/O module features a
high-stability of 10 MHz oven-controlled crystal oscillator (OCXO)
[6]
in order to offer the subsystems
with high-precision reference clocks. The PXI-7842R RIO device is customized to realize the output of
the pulse sequence, the acquisition of the signals and responds to the external events. The CPN has the
block diagram presented in Fig 3.
Fig.3 Block diagram of the CPN
The main logic is encapsulated in various application modules in the RT VI and FPGA VI,
providing flexibility and ability to upgrade the design. These modules include initialization module,
configuration module and so on. The list of all the application modules is shown in table 1.
Table 1: List of the application modules
Module Name
Function
Initialization
Gets node information from the database server when power on
Configuration
Configures the parameters of counter/timer module
Clock generator
Generates the defined clocks by using the DAQmx
Communication
Communicates with the HOST VI for receiving parameter strings
Analysis
Converts the parameter strings to specific data format
Trigger mode
Sets DTSS’s operating mode, which includes internal and external trigger
Shot detection
Receives the trigger signal from the CCS, to start/stop the DTSS
Clock counter
Counts the tick using 64 bits counter
Parameter register
Stores the channels’ information
Compare clk_mark
Trigger decision in a cycle of 25ns
Pulse generator
Provides a maximum of 238 pulses of programmable width (25ns at 40MHz)
Acquisition
Acquires signals
Event detection
Detects the events according to user-defined algorithm
Channel setting
Channel configuration, and sends events to the Pulse generator module
Event record
Records the detected event in a file
Data compress
Compresses digitized signals into LZO files and stores them in local disk
3.5 Local PXI node
Relying on the synchronization clock signals, which are distributed by the synchronized optical
network, the LPN can be phase-locked to the oscillator of the CPN. The configuration of hardware and
the block diagram of LPN have similar structures as the CPN. All the modules in the LPN play the
same role as the modules in the CPN except that the LPN only contents one clock module for
distributing high-stability reference clocks to subsystems. The LPN generates 90 delay trigger signals
and 8 reference clock signals, and provides 6 analogy input (AI) channels to acquire signals for
self-inspection; another 2 AIs are used to process the external events.
3.6 Isolation & drive module
The isolation & drive module is used to remove ground loops among different systems which
connected to the same PXI node. It also provides high voltage isolation among those systems, and each
output channel on the PXI node has an independent power supply [3].
4. Test results
Under the star-type topology, the synchronization of trigger output is one of the most critical
indexes for the DTSS, and the self-inspection results can also verify the correctness of the DTSS
outputs. Two trigger signals generated by different LPNs are setting the same characteristics: delay: 0,
pulse width: 10ms, sig_polarity: positive, en/disable: enable. Fig 4 shows the test results by using
Tektronix™ MSO4034 mixed signal oscilloscope. The outputs of the trigger channels meet the setting
parameters and the maximum skewing between each trigger signal is less than 10 ns.
Fig.4 Test result of the delayed trigger signals
Those two signals are also respectively acquired by DTSS after isolation & drive module, the
sampling rate is 10 K sample per second per channel, and the digitized signals are compressed into
LZO files. User can view those signals by using EASTScope,which is a viewers supplied by the
computer application division of ASIPP. The signals’ acquired results in Fig 5 are consistent with that
in Fig 4.
Fig.5 View of the delayed trigger signals after isolation & drive module by EASTScope
5. Conclusions
Based on PXI bus and RIO devices, a DTSS has been developed by using virtual instrument
technique for a real-time control system of the EAST fusion experiment.
The DTSS can provide reference clock in frequency up to 80 MHz, produce delayed trigger signals
from 1ms width and to about 6872s maximum duration with 10 ns accuracy. The ability of acquiring
signal input/output and processing the externally events also integrated into this system. The hardware,
networks, database and LabVIEW software use standard commercial components, which provide an
open and flexible architecture that can be easily modified [5]. And the modular design is also conductive
to expand the system functions for future improvement.
The DTSS has already been applied to the EAST experiment of discharge in fall, 2010, the
application shows that this system runs stably and accurately, fulfills the requirements of experiment.
The GUI and database server will be integrated into the CCS in the future.
Acknowledgments
The authors would like to thank the EAST CODAC Team for their work and help.
This work was partially funded by the National Natural Science Fund of China under Grants
10675128 and a grant from the Innovation Foundation of Chinese Academy of Sciences under contract
numbers KJCX3.SYW.N4.
References
[1]
[2]
S.Wu, The EAST Team, An overview of the EAST project, Fusion Eng.Des.82(2007) 463-471.
J.Sousa et al., The 32 Bit Timing Unit of a Real-Time Event-Based Control System for a Nuclear Fusion
Experiment, IEEE Trans.Nucl.Sci.45(1998) 2052-2056.
[3] Z. Ji et al., East integrated control system, Fusion Eng.Des. 85 (2010) 509–514
[4] F.Yang et al., Design and realization of engineering experiment data publishing system for EAST, Journal of
Hefei University of Technology. 33(2010) 773-776
[5] J.Luo et al., A Distributed Synchronization and Timing System on the EAST Tokamak, IEEE
Trans.Nucl.Sci.55(2008) 2294-2297.
[6] http://www.ni.com.