Download Read Only Memory ROM

Read Only Memory ROM
• A read only memory have
address inputs and data outputs
• With m address lines you can
access the 2m different
memory addresses
• At each address, there is one
data word with n bits
• Usually, the ROM also has an
Output Enable (OE) input
William Sandqvist [email protected]
2m x n
ROM
Am-1
Dn-1
Am-2 D
n-2
A1
A0
D1
D0
Read Only Memory ROM
Exemple of a ROM
Read only memory:
ROM 4M 512k × 8 bit
Chip Enable activates the chip
Output Enable connects memory to outputs
OE (otherwise they are in the three-state mode)
CE
William Sandqvist [email protected]
A small ROM
Possible memory content
8x4 ROM
A2
A1
A0
D3
D2
D1
D0
A2
A1
A0
D3
D2
D1
D0
0
0
0
0
0
1
0
0
0
1
0
1
1
0
0
1
0
1
1
1
1
0
1
1
1
1
0
1
1
0
0
0
0
1
1
1
0
1
0
0
0
0
1
1
0
1
0
0
1
1
1
1
0
0
1
1
William Sandqvist [email protected]
ROM
Pullup ”1”
VDD
GND
0
Adress Content
Innehåll
Address
x1x0 z3z2z1z0
00
1010
01
0101
10
1100
11
0001
x0
Ord 0
GND
Ord 1
1
x1
2
Ord 2
GND
Ord 3
3
OE
OE=Output Enable
z3
z2
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z1
z0
ROM implementation of
combinatorical functions
zm-1
xn-1
…
x1
x0
f(xn-1,…,x1,x0)
…
z1
z0
Adress
Innehåll
Address Content
xn-1…x1x0 zm-1…z1z0
0…00
1…10
0…01
0…01
…
…
1…11
0…01
A ROM having n inputs with m outputs can be used to implement a
combinatorial function with m outputs and
2n min-terms
William Sandqvist [email protected]
ROM implementation of
sequence circuit
zm-1
xn-1
…
x4
f(xn-1,…,x1,x0)
…
z4
x3
z3
...
...
x0
z0
Adress
Address Innehåll
Content
xn-1…x3x2x1x0
zm-1…z3z2z1z0
0…0000
1…0001
0…0001
0…0010
…
…
1…1111
0…0000
CP
A Moore-machine =
one ROM and a
register with D-flipflops
With feedbacks a ROM can be used to generate sequences and
implement state machines
William Sandqvist [email protected]
Read and Write Memory
Random Access Memory RAM
• RAM-memory has also
a Write (WR) input
which allows us to
enter a data word at a
given address
• Dn-1… D0 are both
inputs and outputs.
William Sandqvist [email protected]
2m x n
Am-1RAM
Dn-1
Am-2 D
n-2
A1
A0
OE
WR
D1
D0
Read-Write-Memory Random Access Memory
RAM
Read/Write memory:
RD
SRAM 4M 512k × 8 bit
CS
RD
WR
WR
Chip Select activates the chip
RD read from memory, data outputs are active
WR write to memory
(at write the data outputs are in the three-state mode )
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SRAM
Static Random Access Memory
• A SRAM-memory consits of a
matrix of SRAM-cells
• To write ‘Data’ is used at
input!
– ‘Sel’ is set to 1 and the value that
is on ‘Data’ is stored in the cell
Sel
Strongest!
Data
• To read ‘Data’ is used as
output!
– ‘Sel’ is set to 1, and the value
from the cell is present at the
output
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SRAM
Data 1
Sel 0
A matrix is
formed by 2m x n
SRAM-cells
Sel 1
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Data 0
SRAM-memory
Data inputs
tristate buffers are used to
ensure that you just either
reads or writes
d0
qn – 1
q0
Write
Sel 0
a1
am – 1
m-to-2m decoder
Sel 1
a0
Address
dn – 1 dn – 2
Sel 2
Sel 2m ” 1
Read
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Data outputs
qn – 2
DRAM Dynamic RAM
• SRAM memorycell needs 4 transistors and it
becomes too costly to implement a large
memory
• DRAM memorycell is using only one
transistor and one capacitor
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DRAM Memorycell
• DRAM-cell consists of
only one transistor and
one capacitor
• Skrivning
Bit Line
Word Line
– To load the cell the word
line is set to ‘1’
• The cell now optains the
value from the bit line
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C
1-bit DRAM
cell
DRAM Memorycell
• To read is a little bit more complex
– You do not want to lose the
information when reading!
– The bit-line is set at a voltage between
the High and Low
– To read the cell the word line is set to
‘1’
Bit Line
Word Line
• The bitline now adjusts it’s voltage to a
voltage up or down
• An extra circuit (per bit line) senses the
current change direction to create a real
0 or 1
• Aftervards the charge in the capacitor
C must be restored!
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C
1-bit DRAM
cell
DRAM Memory
Memorymodule with 8 chips
William Sandqvist [email protected]
Chip
256Mbit (32M×8)
SRAM vs DRAM
• SRAM takes up more space but a DRAM
requires a simpler access logic and is therefore
faster (but also more expensive)
• DRAM is used for random access memories in
our regular computers
• When you remove the power you loses the
contents of SRAM or DRAM memory!
William Sandqvist [email protected]
Memory types
• Volatile memorys
– Memories lose their information if power is disconnected
• static RAM (SRAM)
• dynamic RAM (DRAM)
• Non-volatile memorys
– Memories keep their information if power is disconnected
• Flash (blockwise writing)
• EPROM, EEPROM (bytewise writing)
We need a combination of different
memories in an electrotechnical design!
William Sandqvist [email protected]
Flash-memory
• Non-volatile memory
• low cost and low power consumption
• can be erased and updated but it takes much
more time than in a RAM-memory
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EPROM Erasable
Programmable ROM
Programmable ROM (can be
programmed with a chip
programmer)
Erasable - can be erased
using ultraviolet light and
then reprogrammed. Hence
the "window" on the top side
of the chip.
When working with modern electronic equipment you will not
have to meet the EPROM.
William Sandqvist [email protected]
Memory technologies
Technology Accesstime
SRAM
1 ns
Cost $/GB
1000
DRAM
HDD
50 ns
10 ms
100
1
Fast memory is expensive and inexpensive memories are slow!
Principle numbers.
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Logic in a microprocessor
There are both combinatorial and sequential logic in a
processor. Control logik is a statemachine while the
ALU are mostly combinatorial.
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Registry element
Symbol
Din
Dut
WR
Clock
Din
Dut
WR
>
WR / hold
WR = 1 synchronous writing
WR = 0 hold
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1 logic element
in a FPGA
Register
Symbol
WR
>
32 bit register is 32 logic
elements in a FPGA
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Program counter -register
Register: hoppadress
JA
Program memory:
Byteaddressed
”4”
ADD
Jump/Run
MUX
32 bit
instruktion
Register: programräknare
Clock
>
PC
All processors have a program counter
pointing out where the next instruction is
to be fetched in the William
memory.
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An instruction is 4
bytes
PC, Program
Counter counts up
with "4" after each
instruction.
At the program
jumps PC is loaded
with the jump
address JA (Jump
Address) and then
the program
continues from
there.
Register with threestateoutpot
Symbol
WR
OE
>
Symbol bidirectional (inputs and
outputs are connected together)
WR
>
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OE
Register and Databus
0
WR
OE
1 1
>
WR
OE
0
>
Databus
Several bidirectional registers with three state outputs
can be connected to each other to form a common data
bus.
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Register and Databuss
1
WR
OE
0 0
>
WR
OE
1
>
Databus
Data can now be controlled to be copied between all
registers on the data bus.
William Sandqvist [email protected]
Dubble port register
Symbol
WR
>
OE1
OE2
More Dubble portregisters
can be paired with each
other for two common output
buses.
William Sandqvist [email protected]
Mikrocomputer - architecture
The computer
registers.
A 32×32 bit
dubbleport
Register File
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Mikrocomputer - add
Example Add instruction
1. The instruction
add R1,R2,R3 is fetched
from memory (as binary code)
2. The instruction is decoded
William Sandqvist [email protected]
Mikrocomputer - add
Example Add instruction
1. The instruction
add R1,R2,R3 is fetched
from memory (as binary code)
2. The instruction is decoded
William Sandqvist [email protected]
Mikrocomputer - add
Example Add instruction
3. Register R2 and R3 are add with
the ALU
4. The Result is written to register
R1
William Sandqvist [email protected]
Mikrocomputer - add
Example Add instruction
3. Register R2 and R3 are add with
the ALU
4. The Result is written to register
R1
it requires several
clock pulse periods
for the
implementation of
an instruction.
(maybe you could arrange a Pipeline? )
William Sandqvist [email protected]
Register file
The processor has a 32 × 32 bit register file (with dual port
registers). It can therefore be simultaneously read from any two
registers or write to a register per clock pulse.
The computer instruction
add R1, R2,R3
add, means the sum
R2+R3 is put in R1
R0 … R31
A register file whith 32 registers
are 322 = 1024 logic elements in
a FPGA
32×32 bit register file
ADD
A 32 bit adder are 32 logicelements in a FPGA
William Sandqvist [email protected]
Possible instruction format
32 bit
instruction
add r1, r2, r3
5 bit
5 bit
5 bit
1 of 32 reg 1 of 32 reg 1 of 32 reg
Operatingcode – we want to add
William Sandqvist [email protected]
William Sandqvist [email protected]