Download Transistor Amplifiers

Transistor Amplifiers
Lecture notes: Sec. 6
Sedra & Smith (6th Ed): Sec. 5.6, 5.8, 6.6 & 6.8
Sedra & Smith (5th Ed): Sec. 4.6, 4.8, 5.6 & 5.8
F. Najmabadi, ECE65, Winter 2012
How to add signal to the bias
Bias & Signal
vGS = VGS + vgs
Bias & Signal
vDS = VDS + vds
1. Direct Coupling
2. Capacitive Coupling
 Use a capacitor to separate bias
voltage from the signal.
 Simplified biasing problem.
 Use bias with 2 voltage supplies
o For the first stage, bias such that
VGS = 0
o For follow-up stages, match bias
voltages between stages
 Used in discrete circuits
 Difficult biasing problem
 Only amplifies “AC” signals
 Used in ICs
 Amplifies “DC” signals!
F. Najmabadi, ECE65, Winter 2012
Capacitive coupling is based on the fact that
capacitors appear as open circuit in bias
Real Circuit
Bias Circuit
Signal Circuit
 At a high enough frequency, Zc = 1/ (ωC), becomes small (effectively, capacitors
become short circuit).
o Mid-band parameters of an Amplifier.*
 At low frequencies, Zc cannot be ignored. As Zc depends on frequency, amplifier is
NOT linear (for an arbitrary signal) for these low frequencies.
o Capacitors introduce a lower cut-off frequency for an amplifier (i.e., amplifier
should be operated above this frequency).
F. Najmabadi, ECE65, Winter 2012
In ECE102, you will see that transistor amplifiers also have an “upper” cut-off frequency
What are amplifier parameters?
Voltage Gain : Av =
vo
vi
Open - loop Gain : Avo =
Input Resistance : Ri =
vo
vi
RL → ∞
vi
ii
Output Resistance of Amplifier : Ro =
vo
io
Output Resistance of the circuit : Rout =
Output resistance is the
Thevenin resistance between
the output terminals!
F. Najmabadi, ECE65, Winter 2012
vi →0
vo
io
vsig →0
Observations on the amplifier parameters
Overall Gain :
v
v v
Ri
A= o = i × o =
Av
vsig vsig vi Ri + Rsig
vi
Ri
=
vsig Ri + Rsig
 Value of Ri is important.
o For Rsig << Ri , vi ≈ vsig
o For Rsig = Ri , vi = 0.5 vsig
o For Rsig >> Ri , vi ≈ 0
 Prefer “large” Ri
F. Najmabadi, ECE65, Winter 2012
Av =
vo
RL
=
Avo
vi RL + Ro
 Avo is the maximum possible gain
of the amplifier.
 Value of Ro is important.
o For Ro << RL , Av ≈ Avo
o For Ro = RL , Av = 0.5 Avo
o For Ro >> RL , Av ≈ 0
 Prefer “small” Ro
How to Solve Amplifier Circuits
1. Find Bias and Signal Circuits.
2. Bias circuit (signal = 0):
o Capacitors are open circuit.
o Use transistor large-signal model to find the bias point.
o Use bias parameters to find small-signal parameters (rπ , gm , ro ).
3. Signal Circuit (IVS becomes short, ICS becomes open circuit):
o Assume capacitors are short to find mid-band amplifier parameters.
o Replace diodes and/or transistors with their small-signal model.
o Solve for mid-band amplifier parameters (Av , Ri , Ro ).
• For most circuits, we can use fundamental amplifier configurations,
elementary R forms instead of solving signal circuits.
o Include impedance of capacitors to find the lower cut-off frequency
of the amplifier.
F. Najmabadi, ECE65, Winter 2012
Example 1: Draw the small-signal equivalent of the circuit below (assume
capacitors are short for small signal).
IVS → 0
R remains
Caps short
Ground at the bottom
F. Najmabadi, ECE65, Winter 2012
Replace MOS with its
small signal model
Example 2: Draw the small-signal equivalent of the circuit below (assume
capacitors are short for small signal).
IVS → 0
Caps short
Ground at the bottom
(100k || 33k = 24.8 k)
Flip PMOS
Replace MOS with its
small signal model
F. Najmabadi, ECE65, Winter 2012
Example 3: Draw the small-signal equivalent of the circuit below (assume
capacitors are short for small signal).
IVS → 0
Caps short
ICS → 0
(This makes ICS
an open circuit)
Replace MOS with its
small signal model
F. Najmabadi, ECE65, Winter 2012
Basic MOS Amplifier Configurations
We are considering only signal circuit here!
F. Najmabadi, ECE65, Winter 2012
Possible MOS amplifier configurations
Common-Source
Common-Gate
Common-Source with Rs
Same as Common Gate
(vi does not change)
F. Najmabadi, ECE65, Winter 2012
Common-Drain
Not Useful
PMOS configurations are the same as
those of NMOS
Common-Source
Common-Gate
Common-Drain
Since PMOS has the same signal model, configurations and results are exactly the same
F. Najmabadi, ECE65, Winter 2012
Common Source Configuration (Gain)
Signal Circuit:
vo = − g m v gs (ro || RL′ )
Av =
vo
= − g m (ro || RL′ )
vi
Avo = − g m ro
Signal Circuit with
MOS SSM:
F. Najmabadi, ECE65, Winter 2012
Relevant circuit for
Gain calculation
By KCL
Common Source Configuration (Ri)
Signal Circuit with
MOS SSM:
Relevant circuit for
Ri calculation
ii = 0
Ri =
F. Najmabadi, ECE65, Winter 2012
vi
=∞
ii
Common Source Configuration (Ro)
Signal Circuit with
MOS SSM:
Relevant circuit for
Ro calculation (set vi = 0)
Current source becomes open circuit
Ro = ro
F. Najmabadi, ECE65, Winter 2012
Common Source with Source Resistor
Small Signal Circuit:
Signal Circuit with
MOS SSM:
Input Resistance
F. Najmabadi, ECE65, Winter 2012
ii = 0 ⇒ Ri =
vi
=∞
ii
Common Source with Source Resistor (Gain)
Relevant circuit for
Gain calculation
Node voltage method:
v gs = vi − vS
Node vS
vS vS − vo
+
− g m (vi − vS ) = 0
RS
ro
Node vo
vo vo − vS
+
+ g m (vi − vS ) = 0
′
RL
ro
F. Najmabadi, ECE65, Winter 2012
vo
g m ro RL′
=−
vi
ro + (1 + g m ro ) R S + RL′
g m RL′
Av ≈ −
1 + g m R S + RL′ / ro
Av =
Avo = − g m ro
Common Source with Source Resistor (Ro)
 set vi = 0
 Attach vx and compute ix
 Ro = vx /ix
Node voltage method:
v gs = −vS
Node vS
vS vS − v x
+
− g m ( −vS ) = 0
RS
ro
vS
vx
=
RS
ro + (1 + g m ro ) RS
ix =
vS
vx
=
RS ro + (1 + g m ro ) RS
F. Najmabadi, ECE65, Winter 2012
i
1
1
≡ x =
Ro v x ro + (1 + g m ro ) RS
Ro = ro + (1 + g m ro ) RS
Common Gate Configuration
Gain
Node voltage method:
v gs = −vi
Node vo
vo vo − vi
+
+ g m (−vi ) = 0
RL′
ro
vo
1 + g m ro
vi
=
ro || RL′
ro
vo 1 + g m ro
=
(ro || RL′ )
vi
ro
Av ≈ g m (ro || RL′ )
Av =
Avo ≈ g m ro
F. Najmabadi, ECE65, Winter 2012
Common Gate Configuration (Ri and Ro)
Input Resistance
KVL: vi = (ii +g m v gs )ro + ii RL′
vi (1 + g m ro ) = ii (ro + RL′ )
vi ro + RL′
=
ii 1 + g m ro
1
R′
+ L
Ri ≈
g m g m ro
Ri =
Output Resistance (set vi = 0)
Current source becomes open circuit
Ro = ro
F. Najmabadi, ECE65, Winter 2012
Common Drain Configuration (Source Follower)
Gain
Node voltage method:
v gs = vi − vo
Node vo
vo vo
+ − g m (vi − vo ) = 0
RL′ ro
g m vi =
Av =
g m (ro || RL′ )
1 + g m (ro || RL′ )
Avo =
F. Najmabadi, ECE65, Winter 2012
vo
+ g m vo
ro || RL′
g m ro
≈1
1 + g m ro
Common Drain Configuration (Source Follower)
Input Resistance
ii = 0
Ri =
vi
=∞
ii
ix =
vx
v
v
− g m v gs = x + x
ro
ro 1 / g m
Output Resistance (set vi = 0)
Ro =
F. Najmabadi, ECE65, Winter 2012
1
1
|| ro ≈
gm
gm
MOS Basic Amplifier Configurations
(PMOS circuits are identical)
Common Source
Common Gate
Av = − g m (ro || RL′ )
Av = g m (ro || RL′ )
Common Source with RS
Common Drain/Source Follower
g m RL′
Av = −
1 + g m R S + RL′ / ro
F. Najmabadi, ECE65, Winter 2012
g m (ro || RL′ )
Av =
1 + g m (ro || RL′ )
MOS Elementary R forms
A Transistor can be configured to act as a
resistor for small signals!
Ex: Output resistance of a CS Amplifier
ro
Set vi = 0, current source becomes open circuit
Ro = ro
Notation:
ro is the small-signal resistance
between the point and ground
 If we connect any two terminals of a MOS, we get a two-terminal device.
o For Small Signals, this two terminal device can be replaced with its
Thevenin equivalent circuit.
o As there is NO independent sources present, the Thevenin
equivalent circuit is reduced to a resistor.
F. Najmabadi, ECE65, Winter 2012
Transistor can be configured to act as a
resistor for small signals!
 But, MOS should be in saturation for small signal model to work!
o Connection between MOS terminals are, therefore, made through
ground for small signals.
o In fact, one or both MOS terminals have to be connected to bias power
supplies to ensure that MOS is in saturation
Real Circuit
Small Signal Circuit
A)
B)
F. Najmabadi, ECE65, Winter 2012
No Small Signal circuit
MOS is NOT in saturation
MOS Elementary R forms
(PMOS circuits are identical)
ro (1 +g m R ) + R
∞
≈ ro (1 +g m R )
ro +R
1 + g m ro
Output resistance
of CS Amp with Rs
Input resistance
of CG Amp
Input resistance
of CS Amp
ro
1
1
|| ro ≈
gm
gm
Diode-connected
Transistor
Always in saturation!
Above configurations are for Small Signal. Typically one or both “signal” grounds are
actually connected to bias voltage sources to ensure that MOS is in saturation!
F. Najmabadi, ECE65, Winter 2012
Basic BJT Amplifier Configurations
We are considering only signal circuit here!
F. Najmabadi, ECE65, Winter 2012
Possible BJT amplifier configurations
Common-Emitter
Common-Base
Common-Emitter with RE
Same as Common Base
(vi does not change)
F. Najmabadi, ECE65, Winter 2012
Common-Collector
Not Useful
Common Emitter Configuration (Gain)
Signal Circuit:
vo = − g m vπ (ro || RL′ )
Av =
vo
= − g m (ro || RL′ )
vi
Avo = − g m ro
Signal Circuit with
MOS SSM:
F. Najmabadi, ECE65, Winter 2012
By KCL
Common Emitter Configuration (Ri)
Signal Circuit with
MOS SSM:
Relevant circuit for
Ri calculation
ii =
vi
rπ
Ri =
F. Najmabadi, ECE65, Winter 2012
vi
= rπ
ii
Common Emitter Configuration (Ro)
Signal Circuit with
MOS SSM:
Relevant circuit for
Ro calculation (set vi = 0)
Current source becomes open circuit
Ro = ro
F. Najmabadi, ECE65, Winter 2012
BJT Basic Amplifier Configurations
(PNP circuits are identical)
Common Emitter
Common Base
Av = − g m (ro || RL′ )
Av = g m (ro || RL′ )
Common Emitter with RE
Av = −
g m RL′
1 + g m R E +( RL′ / ro )(1 + RE / rπ )
F. Najmabadi, ECE65, Winter 2012
Common Collector/
Emitter Follower
g m (ro || RL′ )
Av =
1 + g m (ro || RL′ )
BJT Elementary R forms
(PNP circuits are identical)
ro
≈
rπ +R
β
≈ ro (1 +g m R )
≈
F. Najmabadi, ECE65, Winter 2012
ro +R
1 + g m ro
rπ + (1 + β ) R
Discrete Amplifier Configurations
We focus on biasing with Emitter/Source degeneration!
F. Najmabadi, ECE65, Winter 2012
Emitter-degeneration bias circuits
Bias with one power supply
(voltage divider)
Bias with two power supplies
VBB = I B RB + VBE + I E RE
VEE = I B RB + VBE + I E RE
F. Najmabadi, ECE65, Winter 2012
Emitter-degeneration bias circuits
have similar signal circuits
Bias with one power supply
(voltage divider)
Bias with two power supplies
Signal Circuits
The same circuit for
RB = RB1 || RB 2
F. Najmabadi, ECE65, Winter 2012
By-pass capacitors
 There is no RE in the basic Common-Emitter
configuration.
Basic CE Configuration
 However, RE is necessary for bias in discrete circuits.
 Use a by-pass capacitor
Real Circuit
F. Najmabadi, ECE65, Winter 2012
Bias Circuit:
Cap is open, RE stabilizes bias
Signal Circuit:
Capacitor shorts RE
Discrete Common-Emitter Amplifier
Real Circuit
CE amplifier:
Input at the base
Output at the collector
F. Najmabadi, ECE65, Winter 2012
Standard Bias Circuit:*
Caps are open circuit
* Bias calculations are NOT done here as we have done them before.
Signal circuit of the discrete CE Amplifier
Real Circuit
Short caps
Zero bias supplies
Rearrange
F. Najmabadi, ECE65, Winter 2012
Discrete CE Amplifier (Gain)
 Signal input at the base
 Signal output at the collector
 No RE
RL′ = RC || RL
Basic CE configuration
vo
= − g m (ro || RC || RL )
vi
vo
Ri
vo
=
×
vsig R i + R sig vi
F. Najmabadi, ECE65, Winter 2012
Discrete CE Amplifier (Ri)
 Replace transistor with its equivalent resistance
R = rπ
Elementary R form
R = rπ
Ri = RB || rπ
F. Najmabadi, ECE65, Winter 2012
Discrete CE Amplifier (Ro)
 Set vsig = 0
 Replace transistor with its equivalent resistance
Elementary R form
R = ro
Ro = RC || ro
F. Najmabadi, ECE65, Winter 2012
Discrete CE and CS Amplifiers
vo
= − g m (ro || RC || RL )
vi
Ri = RB || rπ
Ro = RC || ro
vo
= − g m (ro || RD || RL )
vi
Ri = RG
Ro = RD || ro
F. Najmabadi, ECE65, Winter 2012
vo
Ri
v
=
× o
vsig R i + R sig vi
Discrete CS Amplifier with RS
Real Circuit
Bias Circuit
Caps open
CS amplifier with RS
Input at the gate
Output at the drain
Signal Circuit
Short caps
Zero bias supplies
F. Najmabadi, ECE65, Winter 2012
Discrete CS Amplifier with RS (Gain)
 Signal input at the gate
 Signal output at the drain
 RS !
RL′ = RD || RL
Basic CS configuration with RS
vo
g m ( RD || RL )
=−
vi
1 + g m R S + ( RD || RL ) / ro
vo
Ri
vo
=
×
vsig R i + R sig vi
F. Najmabadi, ECE65, Winter 2012
Discrete CS Amplifier with RS (Ri)
 Replace transistor with its equivalent resistance
R=∞
Elementary R form
Ri = RG
F. Najmabadi, ECE65, Winter 2012
Discrete CS Amplifier with RS (Ro)
 Set vsig = 0
 Replace transistor with its equivalent resistance
 Since ig = 0, Rsig and RG can be removed (vg = 0)
R = ro (1 +g m RS ) + RS
RS
Elementary R Configuration
R = ro (1 +g m RS ) + RS
F. Najmabadi, ECE65, Winter 2012
Ro = RD || [ro (1 +g m RS ) + RS ]
Discrete CE and CS Amplifiers with RE / RS
vo
g m ( RD || RL )
=−
vi
1 + g m R E +[( RD || RL ) / ro ](1 + RE / rπ )
vo
g ( R || RL )
≈− m D
vi
1+ gm R E
Ri ≈ RB || [rπ + (1 +β ) RE ]
 
βRE
Ro ≈ RC || ro 1 +
  rπ + RE + RB || Rsig
vo
g m ( RD || RL )
=−
1 + g m R S + ( RD || RL ) / ro
vi
Ri = RG
Ro = RD || [ro (1 +g m RS ) + RS ]
F. Najmabadi, ECE65, Winter 2012
vo
Ri
v
=
× o
vsig R i + R sig vi




Discrete CB Amplifier
Real Circuit
Bias Circuit
Caps open
CS amplifier with RS
Input at the gate
Output at the drain
Capacitor CB is necessary.
Otherwise, Amp gain drops
substantially.
F. Najmabadi, ECE65, Winter 2012
Signal Circuit
Short caps
Zero bias supplies
Discrete CB Amplifier (Gain)
 Signal input at the source
 Signal output at the drain
RL′ = RC || RL
Basic CB form
vo
= + g m (ro || RC || RL )
vi
vo
Ri
vo
=
×
vsig R i + R sig vi
Discrete CB Amplifier (Ri)
 Replace transistor with its equivalent resistance
RC || RL
ro + ( RC || RL )
1 + g m ro
Elementary R Configuration
R=
 ro + ( RC || RL ) 
Ri = RE || 

+
1
g
r
m o


Discrete CB Amplifier (Ro)
 Set vsig = 0
 Replace transistor with its equivalent resistance
R ≈ ro [1 +g m ( RE || Rsig )]
Elementary R Configuration
Ro = RC || { ro [1 +g m ( RE || Rsig )] }
Discrete CB and CG Amplifiers
vo
= + g m (ro || RC || RL )
vi
 r + ( RC || RL ) 
Ri = RE ||  o

+
g
r
1
m o


Ro = RC || { ro [1 +g m ( RE || Rsig )] }
vo
= + g m (ro || RD || RL )
vi
 r + ( RD || RL ) 
Ri = RS ||  o

 1 + g m ro 
Ro = RD || { ro [1 +g m ( RS || Rsig )] }
F. Najmabadi, ECE65, Winter 2012
vo
Ri
v
=
× o
vsig R i + R sig vi
Discrete CD Amplifier (Source Follower)
Real Circuit
Bias Circuit
Caps open
CS amplifier with RS
Input at the gate
Output at the drain
Signal Circuit
Short caps
Zero bias supplies
F. Najmabadi, ECE65, Winter 2012
Discrete CD Amplifier (Gain)
 Signal input at the gate
 Signal output at the source
RL′ = RS || RL
Basic CD form
vo
g m (ro || RS || RL )
=
vi 1 + g m (ro || RS || RL )
vo
Ri
vo
=
×
vsig R i + R sig vi
F. Najmabadi, ECE65, Winter 2012
Discrete CD Amplifier (Ri)
 Replace transistor with its equivalent resistance
∞
Elementary R Configuration
Ri = RG
F. Najmabadi, ECE65, Winter 2012
Discrete CD Amplifier (Ro)
 Set vsig = 0
 Replace transistor with its equivalent resistance
 Since ig = 0, Rsig and RG can be removed (vg = 0)
R
1
1
|| ro ≈
gm
gm
Elementary R Configuration
R
Ro = RS ||
F. Najmabadi, ECE65, Winter 2012
1
gm
Discrete CC and CD Amplifiers
vo
g m (ro || RE || RL )
=
vi 1 + g m (ro || RE || RL )
Ri = RB || [rπ + (1 +β )(ro || RE || RL )]
Ro ≈
rπ + RB || Rsig
β
vo
g m (ro || RS || RL )
=
vi 1 + g m (ro || RS || RL )
Ri = RG
Ro = RS ||
F. Najmabadi, ECE65, Winter 2012
vo
Ri
v
=
× o
vsig R i + R sig vi
1
gm
Impact of Coupling and Bypass Capacitors (1)
vi
Ri
=
vsig R i + R sig +1 /( jωCc1 )
vi
Ri
1
=
×
vsig R i + R sig 1 − jω p1 / ω
ω p1 =
1
( R i + R sig )Cc1
High Pass filter with pole at ωp1
vo
Ri
v
1
=
× o×
vsig R i + R sig vi 1 − jω p1 / ω
F. Najmabadi, ECE65, Winter 2012
Impact of Coupling and Bypass Capacitors (2)
Each capacitor introduces a pole!
Poles can be found by inspection:
1) Set vsig = 0
2) Consider each capacitor separately
(i.e., assume all others are short).
3) Find R, the total resistance seen
between capacitor terminals
4) Pole is given by
1
fp =
2π R Cc1
The lower cut-off frequency of amplifiers can be found from
f p ≈ f p1 + f p 2 + ...
F. Najmabadi, ECE65, Winter 2012