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Slide 4-1
Computer
Organization
Copyright © 2004 Pearson Education, Inc.
4
Operating Systems: A Modern Perspective, Chapter 4
CSCI 3753 Announcements
• Moodle - posted last Tuesday’s lecture
• Programming shell assignment 0 due
Thursday at 11:55 pm, not 11 am
• Homework #1 due next Thursday at 11 am
• Read Chapters 3 and 4 in the textbook, skip
4.7 and 4.8
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-2
Stored Program Computers and
Electronic Devices
Patter
n
Jacquard Loom
Variable
Program
Stored Program Device
Fixed Electronic Device
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-3
Program Specification
Source
int
. .
a =
d =
a, b, c, d;
.
b + c;
a - 100;
Assembly Language
; Code for a = b + c
load
R3,b
load
R4,c
add
R3,R4
store
R3,a
; Code for d = a - 100
load
R4,=100
subtract R3,R4
store
R3,d
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-4
Machine Language
Assembly Language
; Code for a = b + c
load
R3,b
load
R4,c
add
R3,R4
store
R3,a
; Code for d = a - 100
load
R4,=100
subtract R3,R4
store
R3,d
Copyright © 2004 Pearson Education, Inc.
Machine Language
10111001001100…1
10111001010000…0
10100111001100…0
10111010001100…1
10111001010000…0
10100110001100…0
10111001101100…1
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-5
The von Neumann Architecture
Central Processing Unit (CPU)
Arithmetical Logical Unit
(ALU)
Control Unit
(CU)
Address Bus
Data Bus
Primary
Memory Unit
(Executable
Memory)
Copyright © 2004 Pearson Education, Inc.
Device
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-6
Slide 4-7
The ALU
load
load
add
store
Right Operand
Left Operand
R3,b
R4,c
R3,R4
R3,a
R1
R2
...
Rn
Functional Unit
Result
Status Registers
To/from Primary Memory
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-8
Control Unit
load
load
add
store
R3,b
R4,c
R3,R4
R3,a
Fetch Unit
PC
3050
Decode Unit
IR
load R4, c
3046
3050
3054
3058
10111001001100…1
10111001010000…0
10100111001100…0
10111010001100…1
Execute Unit
Control Unit
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Primary Memory
Control Unit Operation
• Fetch phase: Instruction retrieved from
memory
• Execute phase: ALU op, memory data
reference, I/O, etc.
PC = <machine start address>;
IR = memory[PC];
haltFlag = CLEAR;
while(haltFlag not SET) {
execute(IR);
PC = PC + sizeof(INSTRUCT);
IR = memory[PC]; // fetch phase
};
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-9
Primary Memory Unit
MAR
1234
MDR
98765
Command
read
Read Op:
1. Load MAR with address
2. Load Command with “read”
3. Data will then appear in the MDR
Copyright © 2004 Pearson Education, Inc.
0
1
2
1234 98765
n-1
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-10
Processor Modes
• Mode bit: Supervisor or User mode
• Supervisor mode
– Can execute all machine instructions
– Can reference all memory locations
• User mode
– Can only execute a subset of instructions
– Can only reference a subset of memory
locations
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-11
Kernels
Slide 4-12
• The part of the OS critical to correct
operation (trusted software)
• Executes in supervisor mode
• The trap instruction is used to switch from
user to supervisor mode, entering the OS
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Supervisor and User Memory
User
Process
User
Space
Supervisor
Process
Supervisor
Space
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-13
Procedure Call and Message Passing
Operating Systems
send(…, A, …);
receive(…, B, …);
call(…);
trap
send/receive
return;
Copyright © 2004 Pearson Education, Inc.
receive(…A, …);
…
send(…, B, …);
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-14
System Call Using the trap Instruction
Slide 4-15
…
fork();
…
Trap Table
fork() {
…
trap
N_SYS_FORK()
…
}
Kernel
sys_fork()
sys_fork() {
/* system function */
…
return;
}
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
A Thread Performing a System Call
User Space
Kernel Space
Thread
fork();
sys_fork() {
}
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-16
Examples of Exceptions in Pentium
Systems
Slide 4-17
Class
Cause
Async/
Sync
Return
behavior
Trap
Intentional
exception
Sync
Fault
Potentially
recoverable
error
nonrecoverable error
signal from I/O
device
Sync
always returns
to next
instruction
might return to
current
instruction
never returns
Abort
Interrupt
Copyright © 2004 Pearson Education, Inc.
Sync
Async
Operating Systems: A Modern Perspective, Chapter 4
always returns
to next
instruction
Examples of Exceptions
• Kinds of Exceptions
–
–
–
–
traps, e.g. system calls
interrupts
faults
aborts
• Pentium: Table of 256 different exception types
– some assigned by CPU designers (divide by zero,
memory access violations, page faults)
– some assigned by OS, e.g. system calls
• Pentium CPU contains exception table base
register that points to this table
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-18
Examples of Exceptions in Pentium
Systems
Exception Table
Exception
Number
Description
Exception Class
0
Divide error
fault
13
General
protection fault
fault
14
Page fault
fault
18
machine check
abort
32-127
OS-defined
Interrupt or trap
128
System call
Trap
129-255
OS-defined
Interrupt or trap
OS
assigns
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-19
Software in the CPU
The Device-Controller-Software
Relationship
Application
Program
•Device manager
•Program to manage device controller
•Supervisor mode software
Abstract I/O
Machine
Device Controller
Device
Copyright © 2004 Pearson Education, Inc.
Slide 4-20
Operating Systems: A Modern Perspective, Chapter 4
Device Controller Interface
...
busy
Command
done
Status
Error code
busy done
0
0 idle
0
1 finished
1
0 working
1
1 (undefined)
...
Data 0
Data 1
Logic
Data n-1
Copyright © 2004 Pearson Education, Inc.
Slide 4-21
Operating Systems: A Modern Perspective, Chapter 4
Performing a Write Operation
while(deviceNo.busy || deviceNo.done) <waiting>;
deviceNo.data[0] = <value to write>
deviceNo.command = WRITE;
while(deviceNo.busy) <waiting>;
deviceNo.done = TRUE;
• Devices much slower than CPU
• CPU waits while device operates
• Would like to multiplex CPU to a different
process while I/O is in process
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-22
…
CPU
Ready Processes
Ready Processes
Ready Processes
CPU-I/O Overlap
Slide 4-23
…
CPU
Device
CPU
Device
I/O Operation
Copyright © 2004 Pearson Education, Inc.
…
Operating Systems: A Modern Perspective, Chapter 4
Device
Uses CPU
Software
Polling I/O - Busy Waiting
…
// Start the device
…
While((busy == 1) || (done == 1))
wait();
// Device I/O complete
…
done = 0;
Hardware
busy
Copyright © 2004 Pearson Education, Inc.
done
…
while((busy == 0) && (done == 1))
wait();
// Do the I/O operation
busy = 1;
…
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-24
Slide 4-25
Determining When I/O is Complete
CPU
Interrupt Pending
Device
Device
Device
• CPU incorporates an “interrupt pending” flag
• When device.busy  FALSE, interrupt pending flag is set
• Hardware “tells” OS that the interrupt occurred
• Interrupt handler part of the OS makes process ready to run
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Control Unit with Interrupt
(Hardware)
PC = <machine start address>;
IR = memory[PC];
haltFlag = CLEAR;
while(haltFlag not SET) {
execute(IR);
PC = PC + sizeof(INSTRUCT);
IR = memory[PC];
if(InterruptRequest) {
memory[0] = PC;
PC = memory[1]
};
memory[1] contains the address of the interrupt handler
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-26
Interrupt Handler (Software)
Slide 4-27
interruptHandler() {
saveProcessorState();
for(i=0; i<NumberOfDevices; i++)
if(device[i].done) goto deviceHandler(i);
/* something wrong if we get to here … */
deviceHandler(int i) {
finishOperation();
returnToScheduler();
}
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
A Race Condition
Slide 4-28
saveProcessorState() {
for(i=0; i<NumberOfRegisters; i++)
memory[K+i] = R[i];
for(i=0; i<NumberOfStatusRegisters; i++)
memory[K+NumberOfRegisters+i] = StatusRegister[i];
}
PC = <machine start address>;
IR = memory[PC];
haltFlag = CLEAR;
while(haltFlag not SET) {
execute(IR);
PC = PC + sizeof(INSTRUCT);
IR = memory[PC];
if(InterruptRequest && InterruptEnabled) {
disableInterupts();
memory[0] = PC;
PC = memory[1]
};
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Revisiting the trap Instruction
(Hardware)
Slide 4-29
executeTrap(argument) {
setMode(supervisor);
switch(argument) {
case 1: PC = memory[1001]; // Trap handler 1
case 2: PC = memory[1002]; // Trap handler 2
. . .
case n: PC = memory[1000+n];// Trap handler n
};
• The trap instruction dispatches a trap
handler routine atomically
• Trap handler performs desired processing
• “A trap is a software interrupt”
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
The Trap Instruction Operation
Mode
S
Branch Table
1
2
trap
3
Trusted
Code
User
Copyright © 2004 Pearson Education, Inc.
Supervisor
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-30
Direct Memory Access
Primary
Memory
CPU
Controller
Device
Copyright © 2004 Pearson Education, Inc.
Primary
Memory
CPU
Controller
Device
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-31
Primary
Memory
Device Addresses
Device 0
Device 1
Device n-1
Copyright © 2004 Pearson Education, Inc.
Memory-Mapped Addresses
Memory Addresses
Memory-Mapped I/O:
Addressing Devices
Primary
Memory
Slide 4-32
No need for
special
instructions to
access a device
Device 0
Device 1
Device n-1
Operating Systems: A Modern Perspective, Chapter 4
MMU takes
care of the
mapping
Intel System Initialization
RAM
Boot Prog
Power Up
BIOS
Loader
OS
…
CMOS
ROM
POST
Hardware Process
Data Flow
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
Boot Device
Slide 4-33
Bootstrapping
Slide 4-34
Bootstrap loader (“boot sector”)
1
BIOS loader
0x0000100
0x0001000
Fetch Unit
PC
0000100
IR
…
Decode Unit
Execute Unit
Copyright © 2004 Pearson Education, Inc.
Primary Memory
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-35
Bootstrapping
Bootstrap loader (“boot sector”)
1
2
Fetch Unit
PC
0001000
IR
…
BIOS loader
0x0000100
0x0001000
Loader
0x0008000
Decode Unit
Execute Unit
Copyright © 2004 Pearson Education, Inc.
Primary Memory
Operating Systems: A Modern Perspective, Chapter 4
Slide 4-36
Bootstrapping
Bootstrap loader (“boot sector”)
1
2
Fetch Unit
BIOS loader 0x0000100
0x0001000
3
PC
Loader
0008000
Decode Unit
OS
IR
Execute Unit
Copyright © 2004 Pearson Education, Inc.
…
0x0008000
0x000A000
Primary Memory
Operating Systems: A Modern Perspective, Chapter 4
Bootstrapping
Slide 4-37
Bootstrap loader (“boot sector”)
1
2
Fetch Unit
BIOS loader 0x0000100
0x0001000
3
PC
Loader
000A000
Decode Unit
OS
IR
Execute Unit
…
0x0008000
0x000A000
Primary Memory
4. Initialize hardware
5. Create user environment
6. …
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4
A Bootstrap Loader Program
Slide 4-38
FIXED_LOC:
// Bootstrap loader entry point
load R1, =0
load R2, =LENGTH_OF_TARGET
// The next instruction is really more like
// a procedure call than a machine instruction
// It copies a block from FIXED_DISK_ADDRESS
// to BUFFER_ADDRESS
read BOOT_DISK, BUFFER_ADDRESS
loop: load R3, [BUFFER_ADDRESS, R1]
store R3, [FIXED_DEST, R1]
incr R1
bleq R1, R2, loop
br
FIXED_DEST
Copyright © 2004 Pearson Education, Inc.
Operating Systems: A Modern Perspective, Chapter 4