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Supplementary Material for the publication:
Self-Aligned Organic Field-Effect Transistors on Plastic with Picofarad
Overlap Capacitances and Megahertz Operating Frequencies
S.G. Higgins,1,a) B.V.O. Muir,1,2 G. Dell’Erba,3,4 A. Perinot,3 M. Caironi,3 and A. J.
Campbell 1,b)
Department of Physics and the Centre for Plastic Electronics, Imperial College London, South Kensington Campus,
London SW7 2AZ, UK
1
Department of Chemistry and the Centre for Plastic Electronics, Imperial College London, South Kensington,
Campus, London SW7 2AZ, UK
2
Centre for Nano Science and Technology @ PoliMi, Istituto Italiano di Tecnologia, Via Pascoli 70/3, 20133 Milano,
Italy
3
Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza Leonardo da Vinci, 32,
20133 Milano, Italy
4
a)
Current address: Optoelectronics Group, Cavendish Laboratory, University of Cambridge, Cambridge CB3 0HE, UK.
b)
Author to whom correspondence should be addressed. Electronic mail: [email protected]
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TABLE SI. Summary of device geometry parameters and specific capacitances.
Parameter
Symbol
Value
PL channel width
W
5425 µm
NIL channel width
W
4972 µm
PL channel length
L
3.77 µm
NIL channel length
L
0.73 µm
PL dielectric specific capacitance
C’
17 nF cm-2
GRA dielectric specific capacitance
C’
33 nF cm-2
Note S1. Analysis technique and device parameters
Abbreviations:
a) PL = photolithographically patterned
b) NIL = nanoimprint lithographically patterned
c) GRA = gravure printed
In all cases the semiconductor is inkjet printed. DC characterization was performed in a nitrogen filled
glovebox using a semiconductor parameter analyser (B1500A, Agilent) and probe station. A summary of
the key device parameters used in the analysis is given in table SI. More accurate geometries than the
nominal design values were determined from scanning electron and optical microscopy using equivalent
architectures, details reported elsewhere.1
The field-effect mobility is calculated numerically as the first derivative with respect to VGS of the
square root of the drain current IDS, as expressed by equation S1.
𝐿
𝜇sat = (𝑊𝐶 ′ )
sat
𝜕√𝐼DS
𝜕𝑉GS
|
(S1)
𝑉DS
The derivative is smoothed using a Savitsky-Golay 3rd order polynomial with a window of 20 points.
This was found to reduce noise without significantly affecting the mobility value obtained.
VT is extracted from the inflexion point of the transfer characteristics. This represents a more
useful/realistic turn-on voltage, as opposed to a straight-line intercept fit, however does typically yield a
larger value.
The on/off ratio is calculated according to equation S2, and is expressed as the exponent value i.e. ‘x
orders of magnitude’.
𝐼 max
log10 ( DS
min )
(S2)
𝐼DS
2
Figure S1. Corresponding DC characteristics (transfer, extracted mobility, output) for all devices
presented in main manuscript. No output curves were measured in (e) due to device breakdown.
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TABLE SII. Summary of extracted parameters from devices shown in figure S1.
Gate
Dielectric
Semiconductor
µsat (cm2 V-1 s-1)
VT (V)
On/off ratio (10x)
PL
PL
p-type
0.006
-5.7
4.3
PL
PL
n-type
0.005
-7.7
5.2
NIL
PL
p-type
0.017
-3.4
3.1
NIL
PL
n-type
0.003
-18.9
4.1
NIL
GRA
p-type
0.024*
-2.1*
3.0*
NIL
GRA
n-type
0.005
1.8
3.2
NOTES:
a) Mobilities extracted from the peak of the forward sweep. This is the effective (apparent) device mobility, to be
distinguished from the intrinsic mobility of the semiconductor.
b) For transfer measurements all devices were biased at |VDS| = |VGS| = +30 V, except for * where |VDS| = |VGS| = +20 V.
This is due to device breakdown during AC testing, as described in the main text.
TABLE SIII. Comparative calculation of transition frequency from directly measured transconductance during AC
characterisation (direct) and from DC data as shown in figure S1 (indirect).
Gate
Dielectric
Semiconductor
gm (direct)
(µS)
gm (indirect)
(µS)
fT (direct)
(MHz)
fT (indirect)
(MHz)
PL
PL
p-type
3
1
0.3
0.1
PL
PL
n-type
2
1
0.2
0.1
NIL
PL
p-type
24
11
2.2
1.0
NIL
PL
n-type
7
6
0.6
0.6
NIL
GRA
p-type
3*
40*
1.9*
25.5*
NIL
GRA
n-type
38
10
2.7
0.7
NOTES:
a) ‘Direct’ refers to the extraction of the transconductance directly from the AC measurement technique itself.
‘Indirect’ is using the transconductance extracted from the DC transfer characteristics under the equivalent biasing
regime. In both cases the same capacitance (CGS and CGD) values are used from the AC measurement.
b) Transconductance (gm) values measured at |VDS| = |VGS| = +30 V, except for * where |VDS| = |VGS| = +20 V. This is
due to device breakdown during AC testing, as described in the main text.
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Figure S2. Schematic of the AC measurement setup, adapted from Higgins et al. (2015).2
Supplementary References
1
S.G. Higgins, B.V.O. Muir, G. Dell’Erba, A. Perinot, M. Caironi, and A.J. Campbell, Adv. Electron. Mater. (in press).
2
S.G. Higgins, B.V.O. Muir, J. Wade, J. Chen, B. Striedinger, H. Gold, B. Stadlober, M. Caironi, J.-S. Kim, J.H.G. Steinke,
and A.J. Campbell, Adv. Electron. Mater. 1, 1500024 (2015).
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