Download ATLAS: An adaptively formed hierarchical cell library based analog

ATLAS: An Adaptively formed Hierarchical Cell Library
based Analog Synthesis Framework
Angan Das and Ranga Vemuri
Department of Electrical and Computer Engineering, University of Cincinnati, Cincinnati, OH 45221-0030, USA
Email: {dasan, ranga}@ececs.uc.edu
Abstract— This paper presents ATLAS - a framework for automated
analog circuit synthesis that comprises of both topology generation and
subsequent circuit sizing. A hierarchically arranged building block or
cell library is used in this regard. The adaptively formed library starts
only with basic elements and gradually includes functionally useful
and bigger blocks, pertinent to the design under consideration. The
sizer is based on the simulated annealing algorithm, and HSPICE is
used for performance evaluation. The tool has been used to synthesize
an operational amplifier and a ring oscillator. Results show that with
reasonable computational effort, designs and associated cells have evolved
that are human understandable and comparable to hand-crafted designs.
Performance
specifications
Cell Library
Roulette map for selection
Topology generation
New cell formation
& Library update
No. of gen. + 1
The domain of IC Design/CAD cannot do without analog circuits
owing to their numerous contributions, the most noted being interfacing with the external world [1]. But unfortunately, in the same genre
where digital circuit synthesis has achieved maturity and success,
its analog counterpart still lacks a robust and complete synthesis
framework. Automated analog circuit-level synthesis basically encompasses two sequential steps - 1) Topology formation and 2) Sizing
of the topology. Now, topology selection and topology generation
are two different approaches to topology formation. The former
depends heavily on design knowledge and starts with a predefined
framework. OASYS [1], DARWIN [2] and Maulik et al.’s IP-based
tool [3] are some examples in this regard. But the considerable setup
overhead and that too specific to each application hampered its worth,
discouraging further research to continue in that direction.
On the contrary, topology generation, based mainly on genetic
algorithms (GA) and genetic programming (GP), emerged to be a
promising area. The so-called evolutionary synthesis techniques were
introduced by Koza et al. [4] and Lohn et al. [5]. But they required
substantial computational overhead and produced functionally correct
but unfamiliar circuits. To alleviate this, Dastidar et al. [6] and Wang
et al. [7] blended some design knowledge, although minimal, with the
evolutionary aspects. They used a fixed set of user-defined building
blocks and connectivity rules to evolve analog circuits. Unfortunately,
the approach in [6], [7] has drawbacks, too. First, the methods fail
completely in the absence of a well-defined library. Secondly, the
library of building blocks used, being specific to the class of circuits
designed, needs to be updated or changed for each new design.
[8], [9] are two of our prior works on the synthesis of passive
analog circuits. In this work, we introduce ATLAS - an adaptively
formed hierarchical cell library based analog synthesis framework for
active circuits. The primary characteristics of ATLAS are:
•
•
•
It is not a GA/GP based work in the true sense, but some of the
concepts and terms used do belong to that of GA/GP.
Any number of input and output terminals can be specified.
Constructs circuits through well defined rules, with the help of
building blocks contained in a hierarchically arranged library.
This work was supported in part by National Science Foundation under
award number CCF-0429717 and in part by Ohio Board of Regents PhD
Enhancement Program.
978-1-4244-1684-4/08/$25.00 ©2008 IEEE
Fitness (F) / Performance
evaluation
No
I. INTRODUCTION
Maxm no. of
gen. reached ?
Yes
Fig. 1.
•
•
•
•
Sizing of topology
No
F = FMAX ?
Yes
End
ATLAS: Synthesis flow
The reusable block library initially consists of basic elements
only. It gradually includes bigger and more meaningful blocks
or cells, pertinent to the design, with each passing generation.
The framework produces cells and circuits that match handcrafted designs, and are thereby understandable by the designer.
A simulated annealing (SA) [10] based sizer and HSPICE based
performance evaluator have been integrated into the same tool.
Presently, the framework is capable of designing circuits based
on PMOS, NMOS, and current sources only. However, it can be
easily extended to include other kinds of elements as well.
The rest of the paper is organized as follows. Section II describes
the synthesis methodology. The circuit construction and adaptive cell
library formation procedures are dealt in greater details. Section III
discusses the sizer and associated fitness evaluation. Section IV
demonstrates the application of ATLAS to build an operational
amplifier and a ring oscillator. Section V finally concludes the work.
II. ATLAS: SYNTHESIS METHODOLOGY
A. Synthesis Flow
The general flow of the ATLAS synthesis framework is shown
in Fig. 1. A generation is a collection of solutions known as
chromosomes. One generation gives birth to the next generation.
Initially, the user provides the performance specifications along with
the other run parameters. A cell library is maintained throughout the
synthesis procedure. The library initially consists of the most basic
elements required - PMOS, NMOS, and current sources along with
their different combinations with the power rails (Vdd, Gnd, etc.),
input(s) and output(s). The library cells are ranked based on their
performance or fitness (initially zero) and stored in the form of a
roulette map. Roulette map selection is a procedure whereby better
candidates have higher chances of getting selected [11].
The circuit formation procedure starts with roulette selection of
better cells. These are then joined through some connectivity rules,
2542
Level_1
<In_1 – In_2 – Out>
001
000
010
VDD
VDD
Main library
M6
111
M5
M7
M8
Div - 1
Level_2
<Gnd – Vdd>
01
00
2 PMOS
1 NMOS
P11
P12
P21
P22
11
P13
Element combinations Level_3
M1
VOUT
M2
VIN-
VIN+
M1
M2
M1
M2
Level_4
Netlist & Outlet info
No. of occurrences, Fitness
Div - 2
M4
M3
Fig. 2.
VDD
M9
Hierarchical cell library (shown for a 2-input 1-output design)
Stage - 1
giving rise to a topology. The generated topology is eventually sized
with a SA-based sizer and the performance evaluated with HSPICE
simulator. After each generation, the cell library is updated with
necessary information acquired from the present set of circuits. A
new generation is formed and the procedure continues till the desired
fitness is achieved, considering the allowable number of generations.
B. Cell or Building Block: Definition & Characteristics
Here, a building block is actually a netlist of elements. It may be
viewed as a blackbox with the following information:
• Number of terminals.
• Terminal signal type: This is of 3 types: voltage only (like gate
of a transistor); current only (like current source terminals); and
mixed (like drain or source of a transistor).
• Terminal direction: For current only and mixed terminals, 3
current directions → ‘in’ (like PMOS source), ‘out’ (like PMOS
drain), and ‘in + out’ (like junction of PMOS and NMOS drains).
Apart from the blackbox features, the information on input and
output (i/o) nodes and the power rail connection (Vdd, Gnd, etc.)
are also stored within the cell itself. The former helps us to quickly
identify a potential set of circuit i/o gateway configurations, while
the latter helps to avoid connecting terminals to Vdd/Gnd forcefully.
C. Hierarchical Cell Library
The cells are stored in a hierarchical cell library. The term hierarchy
symbolizes the pattern of cell arrangement within the library. The
levels are defined based on the presence (1) or absence (0) of aspects
like input node(s), output node(s), power rails (Vdd, Gnd) in a cell,
apart from its elements. The different levels, as shown in Fig. 2, are:
1) Level 1: Combinations of i/o nodes present. For example for a
2-input 1-output circuit, there will be 23 = 8 level 1 libraries.
2) Level 2: Each level 1 library is further subdivided based on
the power rail content. For e.g., for only Vdd and Gnd rails,
there will be 22 = 4 level 2 libraries for each level 1 library.
All level 1 and level 2 libraries also contain Roulette ranked
fitness maps for the cells contained within them.
3) Level 3: Number and combinations of basic elements (PMOS,
NMOS and current sources) present within a cell.
4) Level 4: Lowest level containing the cell netlist and it’s terminal information. Each cell also contains an occurrence count
and a fitness, signifying the number of times it is used in circuit
formation and its appropriateness for the same, respectively.
The hierarchical nature provides two distinct advantages. First of
all, during circuit formation, it helps us in selecting fitter cells as
per the power rail and i/o requirements. Depending on the number
of constraints available, we decide on a level and eventually select
a cell from the roulette map at that level. Secondly, during library
update, it helps us to ensure the absence of a particular cell (say test
cell) in the library to avoid redundant inclusion.
Fig. 3.
Stage - 2
Stage - 3
Topology generation of the 2-input 1-output opamp circuit
D. Circuit Formation
Circuit formation is an important part of the synthesis framework.
For the ease of understanding, we demonstrate the individual aspects
with the help of the circuit generated for a 2-input, 1-output opamp
design (test experiment no:1, section IV-A), as shown in Fig. 3.
1) Simple template for placing cells: A very simple template consisting of successive stages, with each stage consisting of one or more
vertical divisions, serves as the backbone for the circuit. Fig. 3 has
3 stages and 2 vertical divisions per stage (barring stage-3).
2) Combination of i/o containing cells: A one time tree is formed
containing all the possible i/o containing sequences. For e.g., for 2in 1-out design, the various paths of the tree are say (In1)-(In2)-(Out),
(In1+Out)-(In2), etc. The opamp has the sequence (In1+In2)-(Out).
3) Placing input-output cells: For the i/o sequence selected, the input
cells fill up the pockets starting with stage-1 forwards, and output
cells vice-versa. Regarding vertical positioning, Vdd cells are placed
starting from the upper division downwards, and Gnd ones vice-versa.
In Fig. 3, the i/p and o/p cells are placed in P21 and P13 respectively.
4) Placing other cells: The remaining empty pockets are filled with
non-i/o cells. There is no preference for horizontal positioning, but
the vertical positioning follows the same guideline as for i/o cells.
5) Selection of cells from library: Fitter cells are preferentially selected from the library level 1 or level 2 maps. Depending on the i/o
and power rail needs, we decide on a level and eventually select a
fitter cell from the roulette map at that level.
6) Connection between cells: The different cell terminals are interconnected amongst themselves in ways as given below. However,
preference is given to floating nodes over the already utilized ones.
•
•
•
Voltage terminals are connected either to mixed or to voltage
nodes of previous stages. In Fig. 3, this applies to the connections M9:M3, M5:M8, M8:(M2-M7 jn.), and M4:(M8-M9 jn.).
Current terminals are connected to mixed terminals of other cells
in the same stage, depending on the direction and availability.
Mixed terminals are connected to current or mixed terminals
in the same stage (M1:M6, M2:M7, and M8:M9 connections).
These nodes are also preserved for connection to voltage nodes
of succeeding stages (the M2:M7 and M8:M9 junctions are
preserved and eventually connected to M8 and M4, respectively).
7) Connection of floating terminals: In case of unconnected terminals, voltage terminals are biased with an external voltage source.
For current terminals, the lone current source is deleted. Mixed ones
with only ‘in’ or ‘out’ are connected appropriately to the power rails.
Those with ‘in+out’ do not hinder simulation and hence left as it is.
8) Checking inter-connection of stages: Despite being simulatable, if
there is no path from input to output, we simply discard the circuit.
2543
Gen = 1
E. Adaptive Formation of Library
ATLAS updates and extends the cell library adaptively after each
generation. The main heuristic behind adaptivity is that the fitness of
the present circuit produced decides on how well its building blocks
qualify to be prospective cells for future generations of circuits. The
methodology is explained as follows:
1) Implication of circuit fitness: Owing to the inherent nature
of analog circuits, we assume that the merit or fitness (F ) of a
circuit is actually contributed by the appropriateness or fitness of
the participating building blocks. But in this evolutionary CAD
framework, since we are unaware of the different underlying design
heuristics and equations, we need some further assumptions regarding
the definite contributions from each block. In this regard, here, we
flatly distribute the total fitness to all the participating blocks.
2) Existing-cell parameters update: After a circuit is formed and
its fitness evaluated, the parameters of all the participating library
cells need to be updated. The parameters and required updates are:
• No. of occurrences (Ni ): The cell’s count in the library is
incremented by unity each time it is used for circuit formation.
• Fitness: The fitness of a cell denotes its appropriateness for the
design. The new average gross fitness of the i-th cell (Finew )
comes from its old fitness (Fiold ) and its equal share (F̂i ) from
the circuit fitness (F ). For a circuit built with C library cells,
F̂i
=
F/C
Finew
=
(Fiold ∗ Ni ) + F̂i
Ni + 1
For ranking candidates, the effective fitness measure gives importance to both the average gross fitness and the occurrence count. The
effective fitness (Fief f ) for the i-th cell is given by
Fief f = (γ ∗ Fi ) + (δ ∗ Ni ), γ, δ → constants(< 1)
3) Formation of new cells: New cells need to be formed to expand
the library. To serve this purpose, for each node of an element in a
new circuit formed, the surrounding elements up to a certain limit are
examined. Subsequently, all possible non-redundant combinations of
these elements are formed. This combination forms a new cell only
if it contains any of the following → a) Input or output terminals;
b) A continuous path from Vdd to Gnd; c) Two or more elements
connected to the same power rail, but connected at some other point,
too; d) Any gate-gate combination; e) Three/more elements connected
at the same node. These extraction rules minimize the inclusion of
otherwise functionally meaningless combinations into the library.
Fig. 4 shows how two simple cells in gen-1 gradually combine
with other cells to produce bigger and functionally useful new cells.
For e.g., Fig. 4(a) shows an NMOS producing a differential pair,
which further produces that with a constant current biasing.
4) Extension of library: Before inclusion of the newly formed
cell into the library, the absence of the cell is ensured. Required flag
variables for levels 1-3 are generated for the new cell and we search
upto the level 3 trivially. If found, consequently, an exhaustive cell to
cell comparison is made at level 4 that includes netlist/element content, connectivity information, and terminal properties. A truly new
cell is introduced with a generation-proportionate fitness (Fnew cell ):
Fnew cell = (F/No. of new cells) ∗ η ∗ gen no, η → scale factor
III. SIZER AND FITNESS EVALUATION
A. Sizing of the Topology
The aptness of the topology generated for the design cannot be
judged without sizing it properly. The sizer is based on the SA
algorithm [10]. The user specifies the range and granularity of each
Gen = x
VIN+
VIN+
Gen = y (y > x > 1)
VIN-
VIN+
VIN-
(a)
VDD
th
Pa
VOUT
2
VDD
VDD
Pa
th
Gen = 1
VDD
-1
Gen = n (n > m > 1)
Gen = m
(b)
Fig. 4. Results showing (a) an NMOS and (b) a PMOS gradually giving
rise to bigger and functionally meaningful newer cells
design variable (like dimensions of transistors, bias voltages, currents
etc.) for all the elements in the circuit. The performance evaluation for
each solution is done with Synopsys HSPICE simulator. The related
cost function is given by Eqn.(1) (it will be described in section IIIB). Though there are several other sizing techniques, the SA-based
approach is adopted mainly because it is fast enough to size hundreds
of unknown circuits; it could be executed in the batch mode; and it
requires minimal set-up effort, only in the form of tuning.
B. Fitness Evaluation
Most of the analog circuit designs are multi-objective optimization
problems. In this respect, here, we adopt the the normalized weighted
sum approach for multi-criteria optimization. Each performance
criterion is denoted by four values (increasing in the given order)
viz. absolute minimum (min p), lower limit (lower p), upper limit
(upper p) and absolute maximum (max p). A definite weightage
factor (ω) is assigned to each specification. An error function (ε)
gives the normalized deviation between the obtained value (obt p)
and target range for each specification. Quantitatively, ε for objective
i in a design involving P objectives is given by:
⎧ lower p −obt p
i
i
⎪
⎨ lower pi −min pi when obt pi < lower pi ,
obt pi −upper pi
εi = max p −upper p when obt pi > upper pi ,
i
i
⎪
⎩
0
when lower pi <= obt pi <= upper pi .
The total deviation (E) given by the weighted sum of the individual
error terms, and its normalized value, viz. fitness (F ) are given by:
P
P
1
ωi ∗ εi ,
ωi = 100%
(1)
F =
, where E =
1+E
i=1
i=1
Thereby, a fitness of unity represents the required solution.
IV. EXPERIMENTS AND RESULTS
The specifications for the two test designs and the relative weightages for each of the objectives are shown in Table I. They have
been decided after carefully considering several such hand designed
circuits [12]. ATLAS has been coded in C++. The program was run
on a Sun Workstation having two 750 MHz UltraSPARC-3 processors
and 2 GB RAM, with Solaris 10 OS. The technology used is 0.18μ.
The various proportionality constants are fixed carefully after tuning
the algorithm over a lot of runs. They are γ = 0.95, δ = 0.05, and η
= 0.01. The range of the variables for the sizer are (in the format —
min:granularity:max) W tran → 4:0.2:80μ; V bias → 0.5:0.01:5.0V;
I source → 0.1:0.1:20μA, the symbols having their usual meanings.
All the transistor lengths are fixed at 2μ for ease in solving the SA.
Also, the synthesis uses 200 chromosomes for each generation.
2544
1.5
VDD
VIN+
VIN-
Oscillator output: Vout+ (Volt)
VDD
VIN-
VIN+
VIN-
1.25
VOUT+
VOUT-
VOUT+
VOUT-
VINVIN+
Stage-1
VINVIN+
Stage-2
(i)
VOUT+
VOUTStage-3
VDD = 2.5V
1
6.0
6.0
VOUT+
0.75
VIN+
VOUT8.6
1.5V
0.5
0
1
2
3
4
(a)
5
6
7
8
9
10.6
VIN-
14.0
(ii)
(c)
10
Time (ns)
(b)
Fig. 5. (a) Some of the fitter library cells for opamp design; (b) Output waveform (shown till 10ns) of ring oscillator; (c) 3-stage ring oscillator design →
(i) Prototype circuit (ii) Synthesized circuit for a single stage (All dimensions are in μ, L= 2μ for all transistors)
TABLE I
D ESIGN S PECIFICATIONS , P ERFORMANCE VALUES AND R ESULTS
PARAMETERS
ω (%)
Design-I: Operational amplifier
DC Gain
60
Bandwidth
40
3dB frequency
40
Design-II: 3-stage ring oscillator
Oscillation frequency
70
Amplitude (Vdd = 2.5V)
30
PARAMETERS
Max. no. of — stages / divisions
No. of generations required
No. of library cells produced
Specifications
Obtained val.
≥ 70 dB
≥ 900 MHz
≥ 1.5 MHz
70.1 dB
946.9 MHz
1.79 MHz
≥ 850 MHz
≥ 0.8V
870 MHz
0.87V
Design-I
3/3
173
112
Design-II
2/3
95
79
of one feeds to the input of the next. So instead of designing the whole
oscillator, we took help of the prototype system level circuit shown in
Fig. 5(c)(i) and synthesized a single stage. Starting with basic initial
cells, the fully compliant circuit, shown in Fig. 5(c)(ii), was obtained
in the 95th generation. With the initial voltage at Vout+ of stage-1 set
to 0V, the output waveform obtained is given in Fig. 5(b). The circuit
produced a formidable 870 MHz oscillation frequency. Our technique
is better compared to [6], which synthesized a somewhat similar
design taking 63 generations, each consisting of 600 chromosomes.
Also, the final design obtained is well perceivable by the designer.
It consists of a differential pair and diode-connected loads. Similarly,
the cell library comprised of differential pairs, diode-connected loads,
set of biased transistors, input transistors and so on.
V. CONCLUSION
A. Design I - Operational Amplifier
An operational amplifier is a widely used analog circuit having
a vast range of applications including comparators, filters, preamplification stages, signal converters and so on [12]. The 2-input
1-output opamp designed is given a load capacitance (CL ) of 10pF.
ATLAS started evolving acceptable designs from the 150th generation onwards. The totally compliant design, obtained in the 173rd
generation, is shown in Fig. 6. It clearly shows that the design actually
comprises of identifiable blocks like differential pair and current
mirror. Out of the 112 new cells formed, some of the fittest cells are
shown in Fig. 5(a). These cells are all designer perceivable. Table I
shows that all the specifications are met. Also, we have seen that most
of the computational burden owes to the costly SPICE simulations.
B. Design II - 3-stage Ring Oscillator
A ring oscillator is considered as our second design example. Now,
a ring oscillator is truly a cascade of similar stages where the output
VDD = 5V
4.0
4.0
5.8
9.0
VIN+
1.17 V
6.0
6.0
6.8
VIN-
VOUT
4.2
4.0
Fig. 6. Operational amplifier circuit generated for design experiment-1 (All
dimensions are in μ, L= 2μ for all transistors)
We have introduced an analog synthesis framework that is capable
of synthesizing human understandable and competent designs, but
with minimum design knowledge and minimum application dependency. The preferred building blocks or cells are stored in a library,
that is updated throughout the synthesis run. The tool has been able to
synthesize an operational amplifier and a 3-stage ring oscillator. For
industrial relevance, the underlying structure of ATLAS is flexible
and hence it can be integrated with any existing framework.
R EFERENCES
[1] R. Harjani, R. A. Rutenbar, and L. R. Carley, “OASYS: A framework
for analog circuit synthesis,” IEEE Trans. on CAD, vol. 8, no. 12, 1989.
[2] W. Kruiskamp and D. Leenaerts, “DARWIN: CMOS opamp synthesis by
means of a genetic algorithm,” in Proc. of ACM/IEEE Design Automation
Conference, June 1995, pp. 433–438.
[3] P. C. Maulik, L. R. Carley, and R. A. Rutenbar, “Integer programming
based topology selection of cell-level analog circuits,” IEEE Transactions on CAD, vol. 14, no. 4, pp. 401–412, April 1995.
[4] J. R. Koza, F. H. Bennett III, D. Andre, M. A. Keane, and F. Dunlap,
“Automated synthesis of analog electrical circuits by means of genetic
programming,” IEEE Trans. on Evol. Comp., vol. 1, no. 2, 1997.
[5] J. D. Lohn and S. P. Colombano, “A circuit representation technique for
automated circuit design,” IEEE Transactions on Evolutionary Computation, vol. 3, no. 3, pp. 205–219, September 1999.
[6] T. R. Dastidar, P. P. Chakrabarti, and P. Ray, “A synthesis system for
analog circuits based on evolutionary search and topological reuse,”
IEEE Tran. on Evolutionary Computation, vol. 9, no. 2, April 2005.
[7] X. Wang and L. Hedrich, “An approach to topology synthesis of analog
circuits using hierarchical blocks and symbolic analysis,” in Proc. of Asia
South Pacific Design Automation Conf., January 2006, pp. 700–705.
[8] A. Das and R. Vemuri, “GAPSYS: A GA-based tool for automated
passive analog circuit synthesis,” in Proc. of ISCAS, May 2007.
[9] ——, “An automated passive analog circuit synthesis framework using
genetic algorithms,” in Proc. of IEEE ISVLSI, March 2007, pp. 145–152.
[10] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, “Optimization by
simulated annealing,” Science, vol. 220, no. 4598, May 1983.
[11] D. E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning, 1st ed. Addison-Wesley Professional, 1989.
[12] B. Razavi, Design of Analog CMOS Integrated Circuits, 1st ed.
McGraw-Hill, 2003.
2545