Download Chapter 16 Solutions

CHAPTER 16
16.1
3. 64 k1  0.15 1  0. 03   R  3. 64 k 1  0.15 1  0. 03  |
4. 06 k  R  4. 31 k
16.2
 V

V
 I
V
I
 V BE1 
I C1  I S1 exp  BE1  | I C2  I S 2 exp  BE 2  | C2  S 2 exp  BE 2
 | V BE  V BE 2  V BE 1
I S1
VT
 V T 
 V T  IC1


IS  I S1  I S 2 | I S 
IS 1  I S 2
2
I
 IC1
a  I C 2  IC1 : V BE  V T ln  C2
 I 
| I S1  I S 1  S  |
 2I S 

 IS
I S1 
 0. 025 ln 1 

IS 2 

 IS

 I 
I S 2  IS 1  S 
 2 IS 

1 


1 

IS  

2 IS 
1. 05  
 
 0. 025 ln 
  2. 50 mV


IS
0. 95 

2 IS 
 
1.10  
b  V BE  0. 025 ln 
  5. 02 mV
0. 90  
b  I S 1
IS 2

1 



1 

IS 

IS 
 V
 V BE1 
I
0. 001 
 exp  BE 2
 1. 04  S  0. 02 or 2%
  exp 
0. 025 
VT
IS
IS 



IS 
16.3
250 1  0. 05  A 2  1  0. 025 2 | I max  250 1  0. 05  A 1  0. 025 2 = 138 A
a  I DS 



DS
2 
2 
2
V
2
250 1  0. 05  A
2
I min
DS 
2 1  0. 025  = 113 A
2
V
138 A + 113 A
I DS 
 125 . 5A | I DS  138 A  11 3 A = 25 A |
2
I DS
I DS
 19 . 8%
IDS
3  0. 025  = 1. 20 m A
2
V2
250 1  0. 05  A 3  0. 025 2 = 1. 05 m A



2
V2
1. 20 mA + 1. 05 mA

 1. 125 mA | I DS  1. 20 mA  1. 05 mA = 0.150 mA |
2
b  I max
DS 
I min
DS
250 1  0. 05  A
V
2
I DS
 13 . 3%
I DS
1
16.4
V GS1  V TN 
V GS2  V TN 
2I DS1
 V TN 
 W 
K 'n  
 L 1
2I DS1
1
 V TN 
W

 
W / L
K 'n   1 
 L 
2W / L 
2I DS1  W / L  
1
W   4 W / L  

K 'n   
 L 
2IDS2
 V TN 
W
K 'n 
 

 L 2
2I DS2
1
 V TN 
W


W / L
K 'n 
 
 1 
 L 
2W / L 
2I DS2   W / L 
1

W 
K 'n 
 
  4 W / L 
 L 
I DS2  I DS1: V GS2  V GS1 
 W / L 
2IDS2  W / L 
 2 W / L   V GS  V TN 2 W / L 
W


 

 
K 'n    
 L 
 W / L 
0.10 
 25 mV
a V GS  V GS  V TN 
  0.5 
 2 
2 W / L 
 W / L 
V GS
0.003
2
2
 1. 2 %
b 
W / L 
0.5
V GS  V TN 
16.5
 V

V
 0.002  IS1
0.002 
I S1 exp BE1   I S2 exp BE1
 =1.08 | I S1  1.08I S2
 | I  exp
V
V
0.025 
 T 


T
S2
I  I S2
I S 0. 08
IS  I S1  I S2 = 0.08I S2 | I S  S1
=1. 04I S2 |

= 7.7%
2
IS
1. 04
 10V 
 10 V 
 F1  100 1  0. 025 1 
  123 |  F2  100 1  0.025 1 
  117
 50 V 
 50V 
100A
100A
I B1 
 0.813 A | I B2 
 0. 855 A
123
117
16.6
I OX
W

1
 

 V DSX
 L X
1  V DSX

I REF
| R OX  
 W 
1  V DS1
I OX
 
 L 1
V DS1  V GS1  V TN 
I O2
I O3
I O4
2
2I D1
 0.75 
Kn

  1.52V
4 25 x10 
2 30x10 6
6
1
 10
10
1  0.015 10 

30A 
= 84.3A | R O2  0. 015
 909k
4
1  0.015 1.52
84.3A
1
8
20
1  0.0158
0.015

30A 
= 164A | R O3 
 455k
4
1  0. 0151.52 
164A
1
12
1  0. 01512
40
0.
015

30A
=
346A
|
R

 227k


O4
4
1  0.015 1.52 
346A
16.7
5  V SG1
15x10-6 2 
5  V SG1
2
|
 V SG1  2.985 V
 V SG1  0.9  1  0.01V SG1  
4
R
2
1 
3x10
5  2.985
I REF 
 67. 2A
3x10 4
1
 V SD2
15x10 -6 8 
100  5
2
I O2 
 2. 985  0.9 1  0. 015  274A | R OUT2  

 383k
2
1 
I O2
274A
I SD1 
I O3 
15x10 -6 16 
100  10
2
 2. 985  0.9  1  0. 0110   574A | R OUT3 
 192k
 1 
2
574A
16.8
*Problem 16.8 - NMOS Current Source Array
IREF 0 1 DC 30U
VD2 2 0 DC 10 AC 1
VD3 3 0 DC 8 AC 1
VD4 4 0 DC 12 AC 1
M1 1 1 0 0 NFET W=4U L=1U
M2 2 1 0 0 NFET W=10U L=1U
M3 3 1 0 0 NFET W=20U L=1U
M4 4 1 0 0 NFET W=40U L=1U
.MODEL NFET NMOS KP=25U VTO=0.75 LAMBDA=0.015
.OP
.AC LIN 1 1000 1000
.PRINT AC IM(VD2) IM(VD3) IM(VD4) IP(VD2) IP(VD3) IP(VD4)
.END
The results are identical to the hand calculations.
16.9
*Problem 16.9 - PMOS Current Source Array
RREF 0 1 30K
VSS 4 0 DC 5
VD2 2 0 DC 0 AC 1
VD3 3 0 DC -5 AC 1
M1 1 1 4 4 PFET W=2U L=1U
M2 2 1 4 4 PFET W=8U L=1U
M3 3 1 4 4 PFET W=16U L=1U
.MODEL PFET PMOS KP=15U VTO=-0.9 LAMBDA=0.01
.OP
.AC LIN 1 1000 1000
.PRINT AC IM(VD2) IM(VD3) IP(VD2) IP(VD3)
.END
The results are identical to the hand calculations.
16.10
K 'p  W 
2
15x10 -6 8 
2
 V SG2  V TP  1  V SD2  | 35x10 -6 
 V SG1  0.9  1  0.015 
2  L 
2
1 
 W 
8 
  1  V SD2 
  1  0.015 
I
 L 2
35A
1 2
 1.645 V | SD2 
|

 I REF  8. 47A
I REF
W 
I REF
2 
  1  V SD1 
  1  0.011. 645 
 L 1
1 1
I SD2 
V SG1
3
I REF 
5  V SG1
5  1. 645
| R=
 396 k
R
8. 47A
16.11 (a)
V  14.3 V BE 
12  0.7
 226 A | I REF  I C1  1  5  8.3I B | I REF  I S exp BE 1 

4
 FO
V A 
5x10
 V T 

V CE 2
5
1
1
V BE  V CE 2 
VA
60
I O2  5I S exp
| IO2  5226A
 944 A
1 
  5I REF
14.3 V BE
14.3 0.7
V A 
 V T 
1

1

 FO
VA
50
60
V A  V CE 2
60  5
R OUT2  r o 2 

 68. 9 k
IC 2
9.44x10 4
V
3
1 CE 3
1
VA
60
I O3  8.3IREF
 8. 3226A 
 1.52 mA
14.3 V BE
14.3 0.7
1

1

 FO
VA
50
60
V  V CE 3
60  3
R OUT3  r o 3  A

 41.5 k
IC 3
1.52x10 3
b  I REF  12  0.7 4 0.7  212 A | I REF  I C1  1  5  8.3 I B
5x10
 FO 1
a I REF 
 V 
14. 3
2V BE 
I REF  IS exp BE 1 


V A 
 V T   FO  FO  1
V CE 2
VA
2V BE
14.3

 FO  FO 1
VA
1
I O2
V  V

 5I S exp BE 1  CE 2   5I REF
V A 
 V T 
1
I O2
5
V  V CE 2 60 V  5V
60
 5212A 
 1.12mA | R OUT 2  r o2  A

 58.0 k
14. 3
1.4
IC 2
1.12mA
1

50 51 60
1
V CE 3
3
1
VA
60
 8.3212A 
 1.80 mA
14.3
2V BE
14.3
1.4
1

1

FO  FO  1
VA
5051 60
1
I O3  8.3IREF
R OUT3  r o 3 
16.12
4
V A  V CE 3 60V  3V

 35.0 k
IC 3
1.80mA
*Problem 16.12(a) - NPN Current Source Array
RREF 2 1 50K
VCC 2 0 DC 12
VC2 3 0 DC 5 AC 1
VC3 4 0 DC 3 AC 1
Q1 1 1 0 NBJT 1
Q2 3 1 0 NBJT 5
Q3 4 1 0 NBJT 8.3
.MODEL NBJT NPN BF=50 VA=60
.OP
.AC LIN 1 1000 1000
.PRINT AC IM(VC2) IM(VC3) IP(VC2) IP(VC3)
.END
*Problem 16.12(b) - Buffered NPN Current Source Array
RREF 2 5 50K
VCC 2 0 DC 12
VC2 3 0 DC 5 AC 1
VC3 4 0 DC 3 AC 1
Q1 5 1 0 NBJT 1
Q2 3 1 0 NBJT 5
Q3 4 1 0 NBJT 8.3
Q4 2 5 1 NBJT 1
.MODEL NBJT NPN BF=50 VA=60
.OP
.AC LIN 1 1000 1000
.PRINT AC IM(VC2) IM(VC3) IP(VC2) IP(VC3)
.END
The results are almost identical to the hand calculations.
16.13
I REF  IC1  1  5  8.3 
 V 
IB
14.3IB
14.3
2V BE 
 I C1 
 I S exp BE 1 


FO  1
 FO  1
V A 
 V T   FO  FO  1
 V 
 V BE 
14.3
1. 4 
I REF  IS exp BE 1 

  1.029I S exp

 V T  50 51 60 
 V T 
V
1  CE 2
 V BE 
V CE 3 
VA
166A 1. 029
I O3  8.3IS exp
1
 8. 3I REF
| I REF 
 19.6A



3 
V A 
1.029

 V T 
8.3 1

 60 
12  0.7  0.7
12  1.4
I REF 
| R=
 541 k
5x104
19.6A
V
5
1 CE 2
1
VA
60
I O2  5I REF
 519. 6A 
 103 A
1.029
1.029
16.14
I REF 
IB =


15  0.7
V
 238A | I REF  2I C1  2  1  6  9IB = 2 FO 1  EC 1 I B  18I B
6x10 4
V

A 
238A
= 2.00A
0.7 
18 + 250
1


60 
 V

60  15
 15 
I O2   FO 1  EC 2 I B  50 1 
2. 00A   125A | R OUT2  r o2 
 600 k
V A 
 60 
1.25x10 4



V
9 
60  9

I O3  6 FO 1  EC 3 I B  300 1 
2.00A   690A | R OUT2  r o2 
4  100 k
V

60

6.90x10

A 


V
60  27
 27 
I O2  9 FO 1  EC 4 I B  450 1 
2.00A   1.31mA | R OUT 2  r o2 
 66.4 k
V

60

1. 31x10 3

A 
5
16.15
R REF 
15V  0.7V  0.7V
2  1  6  9IB
 544k | I REF  I C1 
25A
 FO  1
 V

18I B
25A
I REF  2 FO 1  EC 1 I B 
| IB 
 0.2435A
1.4  18
V


1


A 
FO
2 50 1 
 

60  51
 V

 15 
I O2   FO 1  EC 2 I B  50 1 
I  15.2 A
V
 60  B

A 


V
9 

I O3  6 FO 1  EC 3 I B  300 1 
I B  84.0 A
V A 
 60 

 V

50
 27 
I O4  9 FO 1  EC 4 IB  450 1 
IB  159 A | I C5   F I E 5 
18I B  4.30 A
V A 
 60 
51

16.16
V BE 2  IE 2 R 2  V BE 3  IE 3 R 3  I E3 
R2
V
 V BE3
I E2  BE 2
R3
R3
In order to have equal base- emitter voltages, the two transistors must operate at the
equal collector current densities:
I E 2 I E3 5IE 2


 n  10
2 A nA
nA
16.17 Note: The two 5-V supplies should be 10 V. With the large voltage drop across the
emitter resistances, the output resistance of the current sources will be very high and
the VCE mismatch terms will be negligible.
I REF
I
I
76  I REF  I REF
 REF | I E1  C1 

 
7
1.093

75 1.093  1.079
F
1
75
I REF
12 V - 0.7 V
12  I REF 10k  0.7V 
 586A | I E1  543A
10k | I REF 
1.079
10k1. 927 
75
I E 2  2I E1 | I O2   F 2I E1   2
543A   1. 07mA
76
75
1
1
I E 3  4I E1 | IO3   F 4I E1   4

 46.6
543A   2.14mA |
76
g m1 40 536A 
I REF  IC1  7I B | I C1 
6
 1

R th  R 
 R 1   10k 46.6  10k  5.01k | R th2  R th r  3   o3  12. 5k
g m1


r 2 

750.025 V 
75 0.025V 
60  10  5. 35
 1.75k | r  3 
 0.876k | r o 2 
 60.4k
1. 07mA
2.14mA
1. 07mA
R th2  5.01k 0.876k  762.5k 4.88k


 oR E

75 5k

R OUT2  r o 2 1 
 60. 4k1
  2.01 M

 4.88k  1.75k  5k 
 R th2  r 2  R E 
r o3 
60  10  5.35 V  30.2k | R  R r    1 5k
 o  
th2
th  2
2.14mA
R th3  5.01k 1.75k  76 5k  4.95k


o R E

75 2.5k

R OUT3  r o 3 1 
  30.2k1 4.95k  0.876 k  2.5k  710 k
R

r

R



th
3
E 
16.18
For V BE 2 = V BE 3, IO3 R 3  IO2 R 2 | R 3 
IO2
I
I
2
R 2  35k  15 k | O2  O 3 | n =
IO3
2A nA
3
16.19
I REF 
 I I 
10 V  0.7V  0.7V
 860A  I C1 | I O2 R 2  V T ln  C1 S2 
10k
I O2 IS1 
860A 2 
10 4 IO2  0. 025 ln 
  I O2  12.4 A | V E 2  12.4 A 10k  0.124V
 IO2 1 
60  5  0.124
r o2 
 5.23 M | R th is small and the voltage across R E is also small.
12.4A
R OUT2  r o 2 1  g m2 R E 2   5.23M1  4012.4 A 10k  31.2 M
860A 12 
5x10 3 IO3  0.025 ln 
 I O3  29.3 A | V E 3  29. 3 A 5k  0.147 V
1 
 IO2

60  5  0.147
r o3 
 2.21 M | R OUT2  r o 3 1 g m3 R E 3   2.21M1  40 0.147   15. 2 M
29. 3A
16.20
R
10  0.7  0.7V  115k | R  V T lnI REF I S2   0.025 V ln75A 2   17.0 k
2




75A
I o2  IO2 I S1 
5A
 5A 1 
 I
75A n 
I 
I o3 R 3  V T ln  REF S3  | 10A2k  0.025V ln 
  n = 0. 297
I
I
 O3 S1 
10A 1 
16.21
*Problem 16.21 - Buffered NPN Widlar Current Source Array
RREF 1 3 10K
VCC 1 0 DC 10
VC2 2 0 DC 5 AC 1
Q1 3 4 0 NBJT 1
Q2 2 4 5 NBJT 2
RE2 5 0 10K
7
Q3 2 4 6 NBJT 12
RE3 6 0 5K
Q4 1 3 4 NBJT 1
.MODEL NBJT NPN BF=100 VA=60
.OP
.AC LIN 1 1000 1000
.PRINT AC IC(Q2) IC(Q3)
.END
Results: IC1 = 858 A, IC2 = 12.7 A, IC3 = 30.2 A, ROUT2 = 28.8 M ROUT3 = 13.9 M
16.22
I REF 
Note: Use VA = 70 V
5V  0. 7V  0.7V  5V 
40k
 215A  IC1 | I O2 
V T I C1 IS 2 
ln 

R2
IO2 I S1 
0.025 V 215A 10 
ln 
 IO2  22.7 A | V E 2  22.7A 5k  0.114 V
5k
1 
 IO2

70  5  0.114

 3.30M | R th is small and the voltage across RE is also small.
22.7A
I O2 
r o2
R OUT2  r o 2 1  g m2 R E 2   r o2 1  40IC 2 R E 2   3.30M1  40 0.114   18.3 M
0.025 V 215A 20 
ln 
  I O3  45.5 A | V E 3  45. 4A 2.5k  0.114V
2.5k
1 
 IO3
70  5  0.114

 1.65M | R OUT3  r o3 1  g m 3R E3   1.65M1  400.114   9.17 M
45.5A
I O3 
r o3
16.23
R
5  0.7  0.7  5 V  172 k
R2 
50A
V T IREF I S2  0.025 V 50A 10 
ln 
ln 
  9. 78 k
 
I o2
10A
10A 1 
 I O2 I S1 
 I
I 
50A n 
I o3 R 3  V T ln  REF S3  | 10A2k  0.025V ln 
  n = 0. 445
I
I
 O3 S1 
10A 1 
16.24 Note: Use -VEE = -5 V
8
For the current mirror at the bottom: I C2   F I B 2 | I E 3 = IC1 + IB1 + I B 2 = n F IB 2  nIB 2  I B 2
IC 2 
IO
F
 F 1 n  F  1
I
IE 3 | I O   F I E 3 
I C2 | I C 2  IREF  I B 3  IREF  O
1  n  F  1
F  1
F
F
1
n
1  n  F  1 
 F  F  1
I O 
n

I REF 
 IO 
I REF 


n
1
n I REF  nI REF for  F  n
F  1
 F 

1

1
 F  F F  1
F
 r
125 40  0.7  5 V
50A  49.6 A | R OUT  o o 
 55.8 M
1
2
2
49.6
A
1
125
3
 or o 125 44. 3 V
b  I O 
3 50A  146 A | R OUT  2  2 146 A  19.0 M
1
125
c V CS  I O R OUT  146A19.0M  2770V d V CB 3 = V EE  0.7V  0.7 V  0  V EE  1. 40V
16.25
 r
 V
 V
12540 
50
R OUT  o o  o A  o A | For Prob. 16.24, R OUT 

M
2
2IO
2nI REF
2n50A
n
1
a I O 
16.26
i x 
0  
 
g m1  g 3
g  g
 m1
3
g 3 ve 
  | I C1  I C2  I C 3 so small - signal parameters are the same
g  3  g o2 
v b 


1 
 = 2g m1 g  3  g m1 g o2  g 3 g o 2  g m1 g  3 2  o 
  2g m1g  3
f  f 

ve  i x
g  3  g o2
ix
=

2g m1
v b  v e  i x
f   o  1
  o 
ix
g  g 3
| v b  i x m1
1     2g


f 
m1
g m1  g o2
i
 x

2g 3
vx  v e  i x   oi 1 r o 3 
for

1  i x
i
r 3 | i 1  g 3 v b  v e   x
1 
 

2
2

f 
ix
i
1
 r
 r
 i x r o3   or o 3 x | R OUT 
 r o3  o o3  o o 3
2g m1
2
2g m1
2
2
16.27
V CB 3  V C 3  V BE 3  V BE 2   V EE   0  V C 3  V EE  V BE 3  V BE 2
IC 3
I
I
I
I
 1
 V T ln C1 | I C1  C1  C1  C 3  F
IC 3 | From Prob.
IS 3
IS1
 F n F
F
F
n
5
1
F  1

I REF 
15A  72.1A | I C1 
I C3  72.0A
n
5
1
1
F
1
1
1

F
125
 F n F
V BE 3  V BE1  V T ln
16.24: IC 3
72. 0A 
 72.1A
V BE 3  V BE 2  0.025 V ln
 ln
 1.16V | V C 3  V EE  1.16 V

3fA
15fA 
16.28 (a)
9
Assuming balanced drain voltages, I DS3  I DS1  I REF
V GS1  V TN 
2I DS1
 0.75 
K n1
5  0.75 
I REF 
2I REF
4 5K 'n
 
2I REF
4
 
'
5K n
W

 

 L 1 IREF
=
W

4
 

 L 2
| V GS3  0.75 
 0.75 
2I REF

'
4 20K n
30k

2I REF
4 20K 'n

| I REF 
5  V GS1  V GS3
30k

| 30kI REF  3.5  1.5
IREF
10K 'n
Using K 'n = 25x10 -6 and rearranging: 9x10 8 I 2REF  2.19x10 5 I REF 12.25  0
I
I REF  87.2 A and I O  REF  21.8 A. Drain voltage balance on M1 and M2
4
requires VGS4  V GS3 | V TN 
(b)
2IREF
 V TN 
W
  '
  K n
 L 4
2IREF
4 20K 'n


W
80
| 
 
 
 L 4
1
This part requires an iterative solution or the use of a computer solver
.
Assuming V DS balance between M1 and M 2 ,   0 will not affect the
current mirror ratio, but it will change VGS and hence IREF slightly.
One iterative approach:
5K 'n
V GS1  V TN 2 1 V GS1 
2
2IDS1
 V TN 
'
20K n 1   5  V GS1 
Guess V GS1 | Then ID1 
Since IDS3  IDS1 , V GS3


5  V GS1  V GS3
I
and I DS1  REF .
30k
4
If the second value of IDS1 does not agree with the first, then try a new VGS1 .
A spreadsheet yields: V GS1  1.336 V, V GS3  1. 381V, I REF  87.5A , I O  21.7A.
I REF 
Note: There is essentially no change from the first answer!
(c)
16.29
10
*Problem 16.28 - NMOS Wilson Source
RREF 1 0 30K
VSS 4 0 DC -5
M1 3 3 4 4 NFET W=5U L=1U
M2 2 3 4 4 NFET W=20U L=1U
M3 0 1 3 3 NFET W=20U L=1U
M4 1 1 2 2 NFET W=80U L=1U
.MODEL NFET NMOS KP=25U VTO=0.75 LAMBDA=0.015
.OP
.END
I O  I REF
R OUT 
 W 
 
 L 1
1
1
| R OUT   f 2 r o 3  f 2

W 
3 I O 2
 
 L 2
1
2
W 
2   K 'n
 L 2
1
I REF
 3 I REF
16.30
Since  = 0, I DS3  I DS1  I REF
 W 
 
 L 2
1

 W 
23
 
 L 1
2K n 1
I DS2  3 I O
3
 W  2

'

 L 2  2K n


W 
 I REF  
 



L 1


 W 
 
 L 1 150A
=
= 37.5A
W

4
 

 L 2
V DS3  V GS3  V TN3 | V D3  10  V GS1   V GS3  V TN3 | V D3  10  V GS1  V GS3  V TN3
V D3  10  V TN1 
2I DS1
 V TN3 
K n1
V D3  10 V  0.75V 
2I DS3
 V TN3
K n3
237.5A V 2

5 25A
237.5AV 2
 8.09 V
20 25A 
16.31
1
1
 W 
 W 
R OUT   f 2 r o 3 |   =    IO = IREF = 50A | r o3 

 1.60M
 L 2  L 1
I DS3 0. 012550A 
 f2 
R OUT
250M
1

 156 | Using Eq . 13.71,  f 2 
r o3
1.60M

2K n
IDS2
2 I
2
5x10 5
3. 80
 W 
    f 2  DS2

0.0125
156



 2 2.5x10 5  1
 L 2
2K 'n


16.32 The circuit is the same as Fig. 16.20 with the addition of RREF in parallel with ro2. We
require RREF >> ro2 in order not to reduce the gain of the feedback loop. A current source with
a source resistor which achieves ROUT = ro(1+gmRs) should be sufficient. A cascode or Wilson
source will also work.
16.33
11
(a ) R O  F 4 r o2 | All K n are the same: I O  I REF  17.5A
V GS1  0.75 
r o2

2 17.5x10 6
75x10
6
  1. 43V |
V 3  V GS3  V TN3  1. 43V  0.75V  0. 680
1
1
 1. 43
 5  1.43 
0.0125
0.
0125

 4.65M | r o4 
 4.78M
17. 5A
17.5A



g m4 = 2 75 x10 6 17.5x10 6 1  0.0125 5  1.43   5.24x10 5 S
 F4  5.24x10 5 S 4.78M   250 | R O  1.16 G
( b) V CS  I O R O  20. 3 kV !
16.34
(c) V min
DD  V GS1  V 4  1.43  0.680  2.11V
*Problem 16.34 - NMOS Cascode Source
IREF 0 1 DC 17.5U
VDD 2 0 DC 5
M1 3 3 0 0 NFET W=3U L=1U
M2 4 3 0 0 NFET W=3U L=1U
M3 1 1 3 3 NFET W=3U L=1U
M4 2 1 4 4 NFET W=3U L=1U
.MODEL NFET NMOS KP=25U VTO=0.75 LAMBDA=0.0125
.OP
.TF I(VDD) VDD
.END
Results:
IO = 17.5 A ROUT = 1.17 GThe same as the hand analysis.
16.35
2I C1
I
2I
I
 C 2  IC1  C1  C1
F
F  1
F
F  1
F
I REF
  F IC1 
 F 1 1 + 2  1
F F  1
a I REF = I C 3 + IB 3 + I B4 = I E 3  I B4  I C1 
I C1 
I REF
| I O  I C 4   F I C2
2
1
1+

 F F  1


110  17.5A

 or o
110 50
IO 
2
1   16. 9 A | R OUT  2  216.9A   163 M
111 
1+


 110 111 
b  V CS  I O R OUT  16. 9A 163M  2750 c  V CC  2V BE  1. 40 V
16.36
12
*Problem 16.36 - NPN Cascode Current Source
IREF 0 1 17.5U
VCC 2 0 DC 5
Q1 3 3 0 NBJT 1
Q2 4 3 0 NBJT 1
Q3 1 1 3 NBJT 1
Q4 2 1 4 NBJT 1
.MODEL NBJT NPN BF=110 VA=50
.OP
.TF I(VCC) VCC
.END
Results:
IO = 16.9 A ROUT = 1.86 MThe same as the hand analysis.
16.37
1
1
W 
 W 
R OUT   f 4 r o2 |   =    I O = I REF = 50A | r o 2 

 1.60M
 L 2  L 1
I DS2 0. 0125 50A
 f4 
R OUT
250M
1

 156 | Using Eq . 13.71, f 4 
r o2
1.60M

2K n4
IDS4
2 I
2
5x10 5
3.80
 W 
    f 4  DS4'  0.0125 156 

5
 L 4
2K n
1
2 2.5x10

16.38

*Problem 16.38 - NPN Widlar Current Source
IREF 2 1 50U
VCC 2 0 DC 10
Q1 1 1 0 NBJT 1
Q2 2 1 3 NBJT 20
R2 3 0 4K
.MODEL NBJT NPN BF=110
.OP
.DC IREF 50U 5M 50U
.PROBE IC(Q2)
.END
16.39
 V
 V
V
I
I O   F I E 2   F  BE1  I B1   BE1  T ln C1
R2
R2
I S1
 R 2

V  V BE 2  V BE1
V  V BE 2  V BE1
I C1  EE
 I B 2  EE
R1
R1
a I C 2 
0. 025V
15 1.4
V BE1
0.7V
ln 4
 318 A | Note:

 318 A
15
2.2k
R
2.2k
10 10
2
b  I C 2 
0.025V
3.3 1. 4
V BE1
0. 7V
ln 4
 295 A | Note:

 318 A
15
2.2k
R2
2. 2k
10 10
c I C 2 
VT
V  V EB 1  V EB 2 0.025 V
5 1. 4
0.7V
ln CC

ln 4
 66.5 A |
 70 A
R2
I S1R1
10k
10k
10 10 15






16.40
13
vx  v1  v e  i x   o i1 r o 4  i x  2i r o 2 | i1  i | v x  i x   oi r o4  i x  2i r o2
i
ix
 2i r o2
r  4  R th
i = ix
where Rth 
g m3

1
g m2
 r  4 | i 
ix  2ir o2
r 4
| i = ix
f 2
i

 r

 x for 2 f 2   o | v x  i x r o2  r o4  o o4  r o2 
 o4  2f 2
2

2


  r
R OUT  r o 4  o  1  o o4
 2

2
14
1
for R th  r 4 and 2f 2   o
r o2
r 4  2r o 2
16.41
An iterative solution is required:
K
2
V
1. Choose VGS2 . Then I DS2 = n2 V GS2  V TN2  and I DS1  GS2
2
R2
2. V GS1  V TN1 
3. I DS2 
2I DS1
K n1
V DD  V GS1  V GS2
R1
Compare to IDS2 in step 1 and choose new VGS2
2.5x10-4
V GS2  0.75 2 | I DS1  VGS2 | V GS1  0.75  2I DS1 -4
2
15k
2.5x10
10  V GS1  V GS2

| Iteration yields VGS2  2. 8V, I O  I DS2  187 A
10k
I DS2 =
I DS2
16.42
An iterative solution is required:
K p1
2
V
1. Choose VSG1. Then I SD1 =
V SG1  V TP1  and I SD2  SG1

2
R2
2. V SG2  V TP2 
3. I SD1 
2ISD2
K p2
V DD  V SG1  V SG2
Compare to I SD1 in step 1 and choose new VSG1
R1
10-4
V
2I SD2
2
V SG1  0.75  | I SD2  GS2 | V SG2  0.75 

2
18k
10 -4
V
 V SG1  V SG2
 DD
| Iteration yields VGS2  2.24 V, I O  I DS2  111 A
10k
I SD1 =
I SD1
16.43
I C1  I C 3  3I C4 | I C 4 = I C2 =
IC2 
16.44
I  V  I I 
V BE1  V BE 2 V T  I C1
=
 ln C2   T ln C1 S2 
ln
R
R  I S1
I S2  R  IC 2 I S1 
0. 025V  3I C2 20 A 
ln
  46.5 A | IC1  3I C2  140 A
2.2k  IC 2 A 
*Problem 16.44 - BJT reference current cell
VCC 1 0 DC 1.5 AC 1
VEE 5 0 DC -1.5
Q4 2 2 1 PBJT 1
Q3 3 2 1 PBJT 3
Q1 3 3 5 NBJT 1
Q2 2 3 4 NBJT 20
R 4 5 2.2K
.MODEL NBJT NPN BF=100 VA=50
.MODEL PBJT PNP BF=100 VA=50
.OP
.AC LIN 1 1000 1000
.PRINT AC IC(Q1) IC(Q2)
.END
15
Results: IC1 = 140 A
I
S VC1CC  2. 92x10
IC2 = 47.8 A
2
I
3
SVC2CC  9.92x10 S
16.45
The M3 - M 4 current mirror forces I SD1  I SD2 .
V GS1  V GS2  I DS2 R | I DS2R  V TN 
I DS2 
0.293
R
1
0.293
' 
5100
5K n

2IDS2
2IDS2 
1 

' | I DS2 R 
' 1 
20K n
10K n 
2 
2I DS1
 V TN 
10K 'n
1
5 25 x10 6

 IDS2  26. 4 A
16.46
a The M3 - M4 current mirror forces I SD1  ISD2 .
V GS1  V GS2  I DS2 R | I DS2R  V TN1 
I DS2 
0.293
R
1
0.293

'
5K n
10 4
b  V TN1  V TO | V TN2  V TO
I DS2 R  V TO 
I DS2 
16.47
2I DS1
 V TN2 
10K 'n
1
5 25 x10 6

   2
2I DS1
 V TO  0.5
10K 'n
F

2I DS2
2I DS2
| IDS2 R 
20K 'n
10K 'n
 IDS2  6.86 A

 V SB  2 F  V TO  0.5
 0. 6  I

1 
1 


2 
DS2 R

 0. 6 
 0.6  I
DS2 R
 0.6
2IDS2
20K 'n
0.293 2IDS2
0.5 

0.6  10 4 IDS2  0.6   I DS2  3. 96 A
4
'

10
10K n 10 4 
*Problem 16.47(a) - MOS reference current cell
VDD 1 0 DC 5 AC 1
VSS 5 0 DC -5
M1 3 3 5 5 NFET W=10U L=1U
M2 2 3 4 5 NFET W=20U L=1U
M3 3 2 1 1 PFET W=10U L=1U
M4 2 2 1 1 PFET W=10U L=1U
R 4 5 10K
.MODEL NFET NMOS KP=25U VTO=0.75 PHI=0.6 GAMMA=0 LAMBDA=0.017
.MODEL PFET PMOS KP=10U VTO=-0.75 PHI=0.6 GAMMA=0 LAMBDA=0.017
*.MODEL NFET NMOS KP=25U VTO=0.75 PHI=0.6 GAMMA=0 LAMBDA=0
*.MODEL PFET PMOS KP=10U VTO=-0.75 PHI=0.6 GAMMA=0 LAMBDA=0
*Problem 16.47(b) - MOS reference current cell
*.MODEL NFET NMOS KP=25U VTO=0.75 PHI=0.6 GAMMA=0.5 LAMBDA=0.017
*.MODEL PFET PMOS KP=10U VTO=-0.75 PHI=0.6 GAMMA=0.75 LAMBDA=0.017
.OP
.AC LIN 1 1000 1000
.PRINT AC ID(M1) ID(M2)
.END
I
2
I
2
 7.64 x10
SVDSDD2  6.23x10
Results: (a) ID2 = 13.9 A ID2 = 12.3 A S VDS1
DD
The currents differ considerably from the hand calculations.
I
2
I
2
 7.75x10
SVDS2
 6.31x10
Results: (b) ID1 = 8.19 A ID2 = 7.24 A S VDS1
DD
DD
The currents differ considrably from the hand calculations.
16

The currents are quite sensitive to the value of . The hand calculations used  = 0.
simulations are run with  = 0, then the results are identical to the hand calculations.
17
If the
16.48
I 5A 
V
0.025 V 2I C2 5A 
I C 2  T ln  C1
ln 
 | I C1 = IC 3  2I C 4  2I C 2 | I C2 
  5. 23 A
R
11k
 A I C2 
 A I C 2 
I C7  5IC 4  55.23A   26.2 A | I C 8 
I C5  2.5I C1  5I C2  26. 2 A | I C 6 
V T I C4 3A  0.025 V 15.7A 
ln 
ln 
 
  I C 8  6.00 A
R 8  A IC 8 
4k
 I C 8 
V T I C1 A  0. 025V 10.4A 
ln
ln
 
  I C 8  5. 42 A
R 6  A I C6 
3k
 I C6 
16.49
V T  I C1 I S2  0.025 V  2I C 2 7I S1 
ln
 
ln
  15.3 A | I C1  2I C2  30.6 A
R  IC 2 I S1  4.3k  I C 2 I S1 
 IC1  30.6 A | I C3  I C7  I C2  15.3 A
I C1  2IC 2 | I C2 =
I C 4  I C5  I C6
16.50
*Problem 16.50 - NPN Cascode Current Source
VCC 1 0 DC 5 AC 1
Q4 2 2 1 PBJT 2
Q3 3 2 1 PBJT 1
Q5 4 3 2 PBJT 1
Q1 6 6 0 NBJT 1
Q2 5 6 7 NBJT 7
Q6 4 4 6 NBJT 1
Q7 3 4 5 NBJT 1
R 7 0 4.3K
.MODEL NBJT NPN BF=100 VA=50
.MODEL PBJT PNP BF=50 VA=50
.OP
.AC LIN 1 1000 1000
.PRINT AC IC(Q7) IC(Q5)
.END
Results: IC2 = 15.2 A IC1 = 28.5 A Similar to hand calculations.
I
S VC2CC  1.81x10
3
I
S VC2CC  7.07x10
4
16.51 Note: VDD = 10 V is not large enough to saturate all the transistors. Use V DD = 15 V to
ensure saturation.
The M3 - M 4 current mirror forces I DS1  1.5I DS2 .
V GS1  V GS2  I DS2 R | I DS2R  V TN 
I DS2 
1  3I DS2


R  10K 'n
18

2I DS2 
1 
3I DS2



'
30K n  3300  10 25x10 6



2IDS2
30K 'n
2I DS2

30 25x10 6
57.9
 I DS2  308 A
I DS1  462 A
3300
 I SD5  I DS6  I DS1  462 A | I SD3  I DS7  I DS2  308 A
I DS2 
I SD4
2I DS1
 V TN 
10K 'n





16.52 Note: VDD = 10 V is not large enough to saturate all the transistors.
*Problem 16.52 - MOS reference current cell
VDD 1 0 DC 15 AC 1
M3 3 2 1 1 PFET W=10U L=1U
M4 2 2 1 1 PFET W=15U L=1U
M5 4 3 2 2 PFET W=10U L=1U
M6 4 4 6 6 NFET W=10U L=1U
M7 3 4 5 5 NFET W=10U L=1U
M1 6 6 0 0 NFET W=10U L=1U
M2 5 6 7 7 NFET W=30U L=1U
R 7 0 3.3K
*.MODEL NFET NMOS KP=25U VTO=0.75 LAMBDA=0
*.MODEL PFET PMOS KP=10U VTO=-0.75 LAMBDA=0
.MODEL NFET NMOS KP=25U VTO=0.75 LAMBDA=0.017
.MODEL PFET PMOS KP=10U VTO=-0.75 LAMBDA=0.017
.OP
.AC LIN 1 1000 1000
.PRINT AC ID(M1) ID(M2)
.END
Results: IDS2 = 265 A IDS1 = 377 A These differ from the hand calculations due to the
non-zero value of . Simulation with  = 0 (and VDD = 15 V) gives results very close to the
hand calculations.
I
4
I
4
S VDSDD2  9.82 x 10
S VC2CC  6. 99 x 10
16.53
Current mirror model:
1
Assuming V DS <<
since it is unknown:

r
50 
4
4  50
A dd  g m1 r o2 r o 4   g m1 o 4  2 5x10
10  -4
-4   0.316mS 250k   79.1
2
10 10 
A cd is determined by the mirror ratio error:
i cc
g
 g m4  g o3
1
i cc + g m4 v 3  i cc - g m 4
 i cc m3
= i cc
for g m3  g m 4
g m 3  g o3
g m3  g o3
 f3  1
This error current goes through ro4 to produce the output voltage since the



common - mode output resistance at the drain of M2 is very large: v od = i cc
i cc  vic
g m1
1
1  r o 4 
 vic
| A cd 
 
1  2g m1R SS
2R SS
f 3  1 
2R SS 
CMRR =
79.1
 1.26 x 106 122 dB 
6.28x10-5
16.54
r o4
f 3  1

500k
1
5
2 79.1  1  50M  6.28 x 10
 
 
*Problem 16.54 - MOS Amplifier with Active Load
VDD 1 0 DC 10
VSS 5 0 DC -10
V1 6 8 DC 0 AC 0.5
V2 7 8 DC 0 AC -0.5
VIC 8 0 DC 0
M3 2 2 1 1 PFET W=50U L=1U
M4 3 2 1 1 PFET W=50U L=1U
M1 2 6 4 4 NFET W=20U L=1U
19
M2 3 7 4 4 NFET W=20U L=1U
ISS 4 5 DC 199.7U
RSS 4 5 25MEG
.MODEL NFET NMOS KP=25U VTO=1 LAMBDA=0.02
.MODEL PFET PMOS KP=10U VTO=-1 LAMBDA=0.02
.OP
.AC LIN 1 1000 1000
.PRINT AC VM(3) VP(3)
.TF V(3) VIC
.END
Results: Adm = 95.8 Acd = 6.16 x10-5.
The results are similar to hand calculations.
The
discrepancies result from not including VDS in the hand calculations for gm and ro.
16.55
Assuming V CE << V A since it is unknown:


A dd  g m2 r o 2 r o4  g m 2
ro 4
 60 60 
 40 10 4  -4
  4.00mS 300k  1200
2
10 10 -4 


A cd : This circuit is often the input stage of a feedback amplfier and the feedback
applies an offset voltage Vos that forces VC1  V C 2 . In this case, the induced collector
current imbalance exactly matches the curren t mirror imbalance and Acd = 0.
Note that the case f or VC1  V C 2 is a tough problem!
The mirror ratio causes a mismatch in the colle ctor currents and therefore
g m
g m
a mismatch in g m : g m1  g m 
g m2  g m 
| The common- mode voltage that is
2
2
  is multiplied by g
cm
developed across r1 and r 2 v 
m1
cm
and g m2 . The common gm v 
term
is canceled out by the current mirror, but the mismatch terms add at the output of t he
current mirror. The output voltage is given approximately by


vo  g m2 v cm
r o 4 r o2  g m2 v cm


cm
v
 v ic
A cd 
r 2

r  2   o  1 2R 1 r o 2

r o2
g m2 cm f 2

v
2
g m2 
2
 v ic
v ic
v
1

 ic for 2R1 > r o2
g m2 r o 2 f 2
g m2 2R1 r o2


vo
1 g m 2

v ic 2 g m2
The collector current imbalance can be found as follows
: Assume that VEC 4  V EC 3  V
0.7  V
1
 V 
VA
V
60 V
and equal Early voltages: I C 4  I C2  I C1
1
| V  A 
 0.48V

2 0.7 = I C1 
F
125
 V A 
1

F V A
20
 V 

V  V 
V
V
IC  I C1  I C 2  IC 0 1  C1   I C 0 1  C1
| I C 0  I S exp BE  I C
  I C 0
V A 
VA
VA
VT



V
V
I C V
1
g m2 IC
1
1
IC  I C 0
 IC
|


|


| A cd 
VA
VA
IC
VA
F
g m2
IC
F
2 F
A cd 
1
1200
 4x10 -3 | CMRR =
 3x10 5 110 dB 
2 125 
4x10 -3
Note that Vos 
V
60
0.48
| V 
 0. 48V | V os 
 0. 400mV
A dd
125
1200
These results can be easily checked with SPICE - See Problem 16.56.
16.56
*Problem 16.56 - BJT Differential Amplifier with Active Load
VCC 1 0 DC 5
VEE 5 0 DC -5
Q4 3 2 1 PBJT 1
Q3 2 2 1 PBJT 1
Q1 2 6 4 NBJT 1
Q2 3 7 4 NBJT 1
*Apply offset voltage to balance collector voltages
V1 6 8 DC 0.4107M AC 0.5
*V1 6 8 DC 0 AC 0.5
V2 7 8 DC 0 AC -0.5
VIC 8 0 DC 0
I1 4 5 199.8U
R1 4 5 25MEG
.MODEL NBJT NPN BF=125 VA=60
.MODEL PBJT PNP BF=125 VA=60
.OP
.AC LIN 1 1000 1000
.PRINT AC VM(3) VP(3) VM(4) VP(4)
.TF V(3) VIC
.END
Results: Adm = 1200 Acd = 5.11x10-6. CMRR = 167 dB. The results are similar to hand
calculations. Note that a very high CMRR is achieved when the circuit is brought
back to balance, as is the case in operational amplifier input stages with feedback
applied. For the case with no offset voltage applied, Acd = 3.73x10-3, and V = 0.49
V. These agree well with the analysis in Prob. 16.55. The value of the required offset
voltage is also very similar to the hand calculations.
16.57
21
a I SD5  I SD4  I SD3  IDS2  I DS1 
2I DS1
V GS2  V GS1  V TN 
K n1
I SS
 100 A
2
 0.75 
V SG5  V SG4  V SG3  V TP 

2 10 4


2I SD4
 0.75 
K p4
 1.20V

2 10 
 1. 25V | V
80 10 
40 2.5x10 5
4
5
SD3
 V SG4  V SG5  2.50V
V DS1  V DS2  10  V SG4  V SG5   V GS1   8.70 V | V SD5  V SD4  V SG4  1.25 V
Q  Pts: 100A, 8.70V  100A ,8.70V  100A,2.50 V 100A,1. 25V  100A ,1.25 V


b  A dd  g m2 r o 2
2

 f 3r o5   g m2 r o2
3

 1

 0. 017  8.7 
A dd  240  2. 5x10
10 1  0.017 8.7 
  0. 479mS 675k  323
10 4




(Note that the loop- gain of the Wilson source is reduced by the presence of R
OUT1  2r o1 .)

5

4
c A dd  g m1 r o1 r o3  | r o3

 1  1.25 


  0.017 4
  601k
10




A dd  0.479mS 675k 601k  152 - The Wilson source yields a 2X improvement
16.58
22
I DS2  I DS1 
I1
I
 125 A | I SD3  I SD4  I DS5  IDS6  I DS7  I2  1  125 A
2
2
For the NMOS transistors VGS  V TN 
For the PMOS transistors VSG   V TP 
2IDS
 0.75 
Kn
2I SD
 0. 75 
Kp

  1.25V
40 2.5x10 
2 1.25 x10 
 1.54 V
40 10 
4
2 1.25x10
5
4
5
V DS1  V DS2  V SG3  1.54V | V DS7  V DS6  V GS6  1.25V | V DS5  V GS6  V GS7  2.50 V
V SD4  V SD3   V GS1  V SG3  5  V DS5   1.25  1.54  5  2.50  2.79 V
Q  Pts: 125A,1.54V  125A,1.54 V  125A, 2.79 V  125A, 2.79V 
125A ,2.50V  125A,1.25 V  125A,1.25V 
 
b  A dd  g m2 f 4 r o2  f 5 r o 7   f 2 f 4
2
g m2 

240 2.5x10

g m4  240  10
A dd 
5
5
1.25x10 1  0.017 1.54   0.507mS |
4
1.25x10 1  0.017 2.79  0.324 mS |
4
r o4
r o3
 1

 0.017  1.54 
 
 483k
4 
 1. 25x10



 1
 2.79 
 0. 017

 
 493k
4 
 1.25x10



 f 2 f 4 0.507mS 483k0. 324mS 493k

 19600
2
2
23
16.59
V SG  V GS  V TN 
16.60




2 2.5x10 4
2I DS
10  2.16  2.16 V
 0.75 
 2.16 V | R 
 22.7k
6
Kn
A
2.5x10 4
10 25x10
*Problem 16.60 - CMOS Folded Cascode Amplifier with Active Load
VDD 1 0 DC 5
VSS 10 0 DC -5
*an offset voltage must be applied to bring output to -2.5V
V1 4 11 DC -5.085M AC 0.5
V2 5 11 DC 0 AC -0.5
VIC 11 0 DC 0
M1 2 4 6 6 NFET W=40U L=1U
M2 3 5 6 6 NFET W=40U L=1U
M3 8 6 2 2 PFET W=40U L=1U
M4 7 6 3 3 PFET W=40U L=1U
M5 8 9 10 10 NFET W=40U L=1U
M6 9 9 10 10 NFET W=40U L=1U
M7 7 8 9 9 NFET W=40U L=1U
I2A 1 2 DC 250U
I2B 1 3 DC 250U
I1 6 10 DC 250U
.MODEL NFET NMOS KP=25U VTO=0.75 LAMBDA=0.017
.MODEL PFET PMOS KP=10U VTO=-0.75 LAMBDA=0.017
.OP
.AC LIN 1 1000 1000
.PRINT AC VM(7) VP(7) VM(6) VP(6) VM(8) VP(8)
.TF V(7) VIC
.END
Results: Add = 23700, Acd = 1.81x10-4. ROUT = 47.7 M, CMRR = 1.31 x 108. The values of
Add and ROUT are similar to hand calculations. Acd and the CMRR are limited by the
small residual mismatches in device parameters.
24
16.61
For  F  , I B  0. V BE 3  V EB 4  V BE 2 
V BE 2
 R 
V BE 2
R 2  V BE 2 1  2 
R1
 R 1 
200A  I1
V
 0. 025 ln
| I1  BE2 | V BE 2  0.025 ln
10fA
R1
V BE 2
R1
10fA
200A 
V BE 2
0.589
20k  V
V BE 2  0. 025 ln
 171A
BE 2  0.589V | I C 2  00A 
10fA
20k
1
20k 
Since IS4  I S3 , V BE 3  V BE 4  0.589 
1 
  0.589 V and IC 4  I C 3  171 A
 20k 
2
200A 
16.62
 F  : V BE3  V EB 4  V BE1  V EB 2 
V T ln
V BE 2
R2
R1
IO
IO
I2
I2
A E 3 + V T ln
A E4 - V T ln
A E1 - V T ln
A
I SON
I SOP
I SON
I SOP E2
A EO
A EO
A EO
A EO
0

I2O A 2EO
I SONI SOP A E1 A E 2 
I 2O A E1 A E2
A E 3A E 4
V T ln 
 1 | IO  I2
  0  2
2 2
I
I
A
A
I
A
I
A
A
A E1 A E2
 SON SOP E 3 E 4

2 EO
2 E3 E4
16.63
Using the results from Prob. 16.62, I O  300A
16.64
A E 3A E 4
 100 A
3A E3 3A E 4
Note: The W/L of M7 should be 15/1.
I DS9  I DS10  I DS12  I DS11  IREF  250A | I SD6 = I DS7  I DS8  3I DS12  750A
I
I DS1  I DS2  I SD13  I SD5  I SD3  ISD4  DS9  125A
2
V DS10  V DS12  V DS11  V GS12  V TN 
V GS1  0.75 
2125A 

40 25x10 6

2I DS12
 0.75 
K n12
2250A 

5 25x10
6
 2.75V

 1.25V | V DS9   V GS1  10  V GS12   6V
2750A 
V DS7  V O  10  V GS12  V GS11  V GS7   0  10  2. 75  2.75  0.75 

15 25x10 6

 7. 25V
V DS8  10  V DS7  2.75 V
V SD6  10  V O  10V  0  10V | V SD5  V SD13  V SD3  V SD4  0.75 
IDS (A)
2125A 

80 10x106

 1.31V
1
2
3
4
5
6
7
8
9
10
11
12
13
125
125
-125
-125
-125
-750
750
750
250
250
250
250
-125
25
VDS (V)
b 
8.63
8.63
-1.31
-1.31
-1.31
-10
8.71
1.29
6.00
2.75
2.75
2.75
-1.31
5
'
K n W 
2
10  W 
2
   V
 V TP  
  V
 V SD5  0.75   750A
2  L 6 SG6
2  L 6 SD4
10 5  W 
2
W 
  2.62  0.75   750A     42.9
2  L 6
 L 6
A dd  A V1 A V 2  g m2 r o 2 g m6 r o6   f 2 f 6 |  f 2
 f6 
1
p
16.65
2K p6
ISD6

1
0. 017

242.9  10x10 6
750x10 6
1

n
  62. 9 |
2K n2
1

I DS2
0.017

240 25x10 6
125x10
6
  235
A dd  235 62.9   14800
*Problem 16.65 - CMOS Amplifier with Active Load
VDD 8 0 DC 10
VSS 14 0 DC -10
*Connect feedback to deterimine Vos
*V1 1 13 DC 0
*The offset voltage must be used to set Vo to approximately zero voltages.
V1 1 15 DC 0.4423M AC 0.5
V2 2 15 DC 0 AC -0.5
VIC 15 0 DC 0
M1 3 1 5 5 NFET W=40U L=1U
M2 4 2 5 5 NFET W=40U L=1U
M3 6 7 8 8 PFET W=80U L=1U
M4 7 7 8 8 PFET W=80U L=1U
M5 4 3 7 7 PFET W=80U L=1U
M6 13 4 8 8 PFET W=42.9U L=1U
*The offset can be adjusted to zero by correcting the value of W/L
*M6 13 4 8 8 PFET W=37.25U L=1U
M7 13 9 12 12 NFET W=15U L=1U
M8 12 10 14 14 NFET W=15U L=1U
M9 5 9 11 11 NFET W=5U L=1U
M10 11 10 14 14 NFET W=5U L=1U
M11 9 9 10 10 NFET W=5U L=1U
M12 10 10 14 14 NFET W=5U L=1U
M13 3 3 6 6 PFET W=80U L=1U
IREF 0 9 DC 250U
.MODEL NFET NMOS KP=25U VTO=0.75 LAMBDA=0.017
.MODEL PFET PMOS KP=10U VTO=-0.75 LAMBDA=0.017
.OP
.AC LIN 1 1000 1000
.PRINT AC VM(13) VP(13) VM(4) VP(4)
.TF V(13) VIC
.END
Results: Vos = 0.4423 mV, Adm = 22500, Acm = 0.2305, CMRR = 99.9 dB, ROUT = 90.3 M.
The values of Add and ROUT are similar to hand calculations. Acd and the CMRR are
limited by the offset induced mismatches in the devices. With the W/L of M 6
corected, Vos ≈ 0, Adm = 20800, Acm = 9.28 x 10-3. ROUT = 90.3 M, CMRR = 127
dB.
26
16.66
A dm  A V1 A V2 A V 3  g m 2 r o 2 r o4
 
 g m5 r o5 r o12  1
I DS10 = I REF =100A | I DS12 = I DS11 = 2IDS10 = 200A | I DS1  I DS2  I SD3  ISD4 
I SD5  IDS12  200A | V SD4  V SG3  V GS2  V TN 
V DS2  10  V SD4   V GS2   10.0 V | g m 2 
2I DS2
 0.75 
K n2

I DS11
 100A
2
2100A 

20 25x10
6

 1. 38V

220  25x10 6 100A 1  0. 01710  0.342mS
1
1
58.8 10 V
58.8  1.38 V

 58.8V | r o 2 
 688k | r o 4 
 602k | A V1  110
4
 0.017
A
A
10
10 4
V SD12  V SD5  10 
g m5 

V GSGG
| V GSGG  0.75 
2

2200A

5 25x10 6


 2.54 V | V SD12  V SD5  8.73V
2100  10 5 2x10 4 1  0.017 8.73  0.678mS | r o12  r o 5 
A V 2  115 | A dm  A V1 A V2 A V 3  110  115  1  12600
58. 8  8.73 V
 338k
2x10 4
A
A dm  10900 if 1 + V DS  is neglected in gm .
16.67
*Problem 16.67 - CMOS Amplifier with Active Load
VDD 8 0 DC 10
VSS 14 0 DC -10
*An offset voltage is used to set Vo to approximately zero volts.
V2 1 15 DC 0.3506M AC 0.5
V1 2 15 DC 0 AC -0.5
VIC 15 0 DC 0
M1 3 1 5 14 NFET W=20U L=1U
M2 4 2 5 14 NFET W=20U L=1U
M3 3 3 8 8 PFET W=50U L=1U
M4 4 3 8 8 PFET W=50U L=1U
M5 6 4 8 8 PFET W=100U L=1U
*The offset can be adjusted to zero by correcting the value of W/L
*M5 6 4 8 8 PFET W=89.5U L=1U
M6 8 6 13 14 NFET W=10U L=1U
M7 14 7 13 8 PFET W=25U L=1U
MGG 6 6 7 14 NFET W=5U L=1U
M10 9 9 14 14 NFET W=10U L=1U
M11 5 9 14 14 NFET W=20U L=1U
M12 7 9 14 14 NFET W=20U L=1U
IREF 0 9 DC 100U
.MODEL NFET NMOS KP=25U VTO=0.75 LAMBDA=0.017
.MODEL PFET PMOS KP=10U VTO=-0.75 LAMBDA=0.017
*.MODEL NFET NMOS KP=25U VTO=0.75 GAMMA=0.6 LAMBDA=0.017
*.MODEL PFET PMOS KP=10U VTO=-0.75 GAMMA=0.75 LAMBDA=0.017
.OP
.AC LIN 1 1000 1000
.PRINT AC VM(13) VP(13) VM(4) VP(4)
.TF V(13) VIC
.END
Results:
Adm = 11200, Acm = 0.604, ROUT = 3.10 k.
27
(a)
1
2
3
4
5
6
7
GG
10
11
12
IDS (A)
112
112
-112
-112
-223
44.2
-44.2
223
100
223
223
VDS (V)
(b)
9.96
9.99
-1.41
-1.37
-8.70
10.0
-10.0
2.60
1.63
8.63
8.70
IDS (A)
110
110
-110
-110
-219
0
0
219
100
219
219
VDS (V)
11.2
11.2
-1.40
-1.37
-8.85
10.0
-9.97
3.79
1.63
7.41
7.35
Note that the body effect has increased the threshold voltages of M6 and M7 to the point that
they are no longer conducting. VTN6 = 2.24 V VTP7 = -2.61V. The W/L ratio of MGG needs to
be redesigned to solve this problem.
16.68
I DS10 = I REF = 250A | I DS11 = 2I DS10 = 500A | I DS12 = 4I DS10 =1000A
I DS1  I DS2  I SD3  I SD4 
I DS11
2250A 
 250A | V DS10  V GS10  0.75 
 2.16 V
2
10 25x10 6

I SD5  IDSGG  IDS12  1000A | V GSGG  0.75 
V
 GSGG  2. 375V | I SD7  I DS6
2
V GS6  V SG7
V SD4  V SD3  V SG3  V GS2  V TN 
21000A 

 4.75 V


1025x10 

2.375  0.75 
5 25x10 6
6
2
2
2I DS2
 0.75 
K n2
2250A

20 25x10 6

V DS1  V DS2  7.5  V SD4   V GS2   7.50V | V SD12  V SD5  7.5 
V DS6  V SD7  7. 5V | V DS11  7.5  V GS2  7.5 1. 75  5.75 V
 330A
 1.75 V
V GSGG
= 5.13V
2
1
2
3
4
5
6
7
GG
10
11
12
IDS (A)
250
250
-250
-250
-1000
330
-330
1000
250
500
1000
VDS (V)
SPICE
7.50
7.50
-1.75
-1.75
-5.13
7.50
-7.50
4.75
2.16
5.75
5.13
IDS (A)
264
266
-264
-266
219
359
-359
1050
250
530
1050
VDS (V)
7.46
7.09
-1.76
-2.14
-5.20
7.54
-7.46
4.69
2.14
5.78
5.11
 
A dm  A V1 A V2 A V 3  g m 2 r o 2 r o4
g m2 

 g m5 r o5 r o12  1

220 25x10 6 250A1  0.017 7.50   0. 531mS
1
1
58.8  7.50 V
58.8  1.75 V

 58.8V | r o2 
 265k | r o4 
 242k | A V1  67.2
4
4
 0.017
A
A
2.5x10
2. 5x10
58.8  5.13 V
g m5  2100  10 5 10 3 1  0.017 5.13   1. 48mS | r o12  r o5 
 63. 9k
3
A
10



A V 2  47.3 | A dm  A V1 A V 2 A V 3  67. 2 47.3 1  3180
SPICE Results:
28
Adm = 2950, Acm = 0.03, ROUT = 1.10 k.
16.69
a For saturation of M11 :
V DS11 = 0  V GS2   V SS   V SS  V GS2 
2I DS2
 0.75 
K n2
V GS2  V TN 
2100A 

2200A 
2I DS11

K n11
20 25x10 6


20 25x10 6

 0.894
 1. 38V | V SS  1.38  0.894  V SS  2.27 V
For saturation of M12 :
V DS11 = 0 
V GSGG
2
V GSGG  0.75 
  V SS   V SS 
2200A 

5 25 x10
6

V GSGG
2
2I DS12


K n12
 2.54V | V SS 
2 200A 

20 25x10 6

 0.894
2.54
 0.894  V SS  2.16V
2
For saturation of M1 and M 2 :
V DS1 = V DD  V SG3  V GS1   V DD  V SG3 + V GS1 
2IDS1

K n1
2100A 

20 25x10 6

 0. 633
V SG3 = V GS1: V DD  0.633V
For saturation of M5 :
V SD5 = V DD 
2.54

2
2ISD5

K p5
2200A

100 10x10 6

 0.633 V  V DD  1.90 V
M 6 and M7 are always saturated: e.g. V DS6  V GS6
The minimum supply voltages are: V DD  1. 90V V SS  2.27 V
For the symmetrical supply case, V DD  V SS  2. 27V
b  The values of VDD and V SS in part (a) do not permit any significant common - mode
input voltage range. For saturation of M11 with V IC  5V,
V DS11 = V IC  V GS2   V SS   V SS  1.38  5  0.894  V SS  7. 27V
For saturation of M1 and M 2 :
V DS1 = V DD  V SG3  V IC  V GS1   V DD  5 1. 38 +1. 38  0.633  V DD  5.63V
For an output range of 5V, saturation of M12 requires
V
2.54
V DS12 = 5  GSGG  V SS   V SS  5 
 0.894  V SS  7.25V
2
2
For Saturation of M5 :
2.54
V SD5 = V DD 
 5  0.633V  V DD  6. 90V
2
The minimum supply voltages are: V DD  6.90V V SS  7.25 V
For the symmetrical supply case, V DD  V SS  7.25 V
29
16.70
I DS8 = IREF = 250A | I DS10 = IDS9 = 2I DS8 = 500A
I DS1  I DS2  I SD3  I SD4 
I DS9
2250A 
 250A | V DS8  V GS8  0.75 
 2.16 V
2
10 25x10 6

I SD5  IDS11  I DS10  500A | V GS11  0.75 
V GS6  V SG7
V
 GS11  1.789V | I SD7  I DS6
2
V SD4  V SD3  V SG3  V GS2  V TN 
2500A 
 3.58V


10 25x10 

1.789  0. 75
5 25x10 6
6
2
2
2250A
2I DS2
 0.75 
K n2

20 25x10 6
V DS1  V DS2  5  V SD4   V GS2   5.00V | V SD10  V SD5  5 
V DS6  V SD7  5. 00V | V DS9  5  V GS2  5  1.75  3.25V
IDS (A)
VDS (V)
SPICE
IDS (A)
VDS (V)

 135A
 1.75 V
V GS11
= 3.21V
2
1
2
3
4
5
6
7
8
9
10
11
250
250
-250
-250
-500
135
-135
250
500
500
500
5.00
5.00
-1.75
-1.75
-3.21
5.00
-5.00
2.16
3.25
3.21
3.58
255
4.97
255
4.99
-255
-1.74
-255
-1.73
-509
-3.24
139
5.01
-139
-5.00
250
2.14
509
3.28
509
3.23
509
3.52
 
A dm  A V1 A V2 A V 3  g m 2 r o 2 r o4
g m2 



 g m5 r o5 r o12  1

220 25x10 6 2.50x10 4 1  0.017 5. 00  0.521mS
1
1
58.8  5.00 V
58. 8  1.75 V

 58.8V | r o2 
 255k | r o4 
 242k | A V1  64.7
4
4
 0.017
A
A
2.5x10
2.5x10
58.8  3.21 V
g m5  2100  10 5 5.00 x10 4 1  0. 017 3.21  1.03mS | r o12  r o5 
 124k
4
A
5.00x10



A V 2  63.9 | A dm  A V1 A V2 A V 3  64.7  63.9  1  4130
SPICE Results:
16.71
A dm 
Adm = 4000, Acm = 0.509, ROUT = 1.81 k.
 f 2 f 5
| For the MOSFET,  f 2 
2
But, I DS2  I REF and I SD5  IREF  Adm 
a A dm  16000
16.72
30
100A
 6400
250A
1
I DS
 Adm 
1
I DS2
1
I REF
b  A dm  16000
100A
 80000
20A
1
I SD5
A dm 
I C2
 f5

| For our BJT models,  f and o are independent of current
IC5 o5 2
We have I C2  I REF and I C5  I REF  A dmis constant a A dm  7500
16.73
b  A dm  7500
The W/L ratios have been scaled to keep the Q-points and gain the same. Note that the
output stage should remain a source follower pair and is not mirrored.
16.74
Note that the output stage should remain complementary emitter followers.
I
The gain of the first stage is approximately AV1  g m1 r 5  C1  o 5 , the mirror
I C5
image amplifier with an npn transistor for Q5 will have the highest gain. The
voltage gain of the rest of the amplifier is the same.
16.75
V EB 7  V EB 8  V EB 6  V EB 4  2V T ln
 250A 
IC 4
I
 2V T ln C 44  0.05 ln 
  1.142 V
I S4
2IS 4
215fA  
V EB 7  V EB 8  V T ln
IC 7
I
I
60 IC 8 I C8
 V T ln C 8 I C 7   F I B 8   F C 8 

IS7
IS 8
F
61 60
61
V EB 7  V EB 8  V T ln
IC 8
I C8
I 2C8
 V T ln
 0.025 ln
 1.142
6115fA 
415fA 
6115fA 4 15fA 
I C 8  1. 946 mA | I C16  I C 8 | A E16 
I C16
1946 A
A E12 
1  7.78
I C12
250A
2 0.5583 V 
75A 
V BE 6  V EB 10  0. 025 ln 
  0.558 V | R BB 
 574 
 15fA 
1.946 mA

   o  1r  8
A dm  A V1 A V2 A V 3  
g m2 r o 2 r 7   o  1r 8  r    1r g m 8 r o8 r o16  1
 7
o
8

 
 
A dm  A V1 A V2 A V 3  g m 2 r o 2 r 7   o  1r  8
 
A dm  g m2 r o2 2r 7
R ID  2r 1  2
16.76
4f 8


r


 o  1r 8
7   o  1r 8

 f 8 
 1
2 
I C2

125A
4060  4. 3
5
 o7 f 8 
60
 3.03 x 10
I C7
2
31,8A
2
1500.025 V 
 60 k
125A
*Problem 16.76 - Bipolar Op-Amp
VCC 1 0 DC 5
VEE 14 0 DC -5
V1 6 15 DC -74.17U AC 0.5
V2 7 15 DC 0 AC -0.5
VIC 15 0 DC 0
Q1 4 6 8 NBJT 1
Q2 5 7 8 NBJT 1
Q3 4 4 2 PBJT 1
Q4 5 4 3 PBJT 1
31
Q5 2 3 1 PBJT 1
Q6 3 3 1 PBJT 1
Q7 14 5 10 PBJT 1
Q8 11 10 1 PBJT 4
Q9 1 11 12 NBJT 1
Q10 14 13 12 PBJT 1
Q12 9 9 14 NBJT 1
Q14 8 9 14 NBJT 1
Q16 13 9 14 NBJT 7.78
IB 0 9 250U
RBB 11 13 574
.MODEL NBJT NPN BF=150 VA=60 IS=15F
.MODEL PBJT PNP BF=60 VA=60 IS=15F
.OP
.AC LIN 1 1000 1000
.PRINT AC VM(12) VP(12)
.TF V(12) VIC
.END
SPICE Results:
Vos = -74.17V, Adm = 2.83 x 105, Acm = 0.507, CMRR = 115 dB,
RID = 81.6 k, ROUT = 523 .
16.77
a We require forward- active region operation of all transistors.
For Q14 : V CB14  0  V BE1  V EE  V BE14   0  V EE  1. 4V
For Q1 : V CB1  V CC  V EB 6  V EB 4  0  V CC  1.4 V
For Q16 : V CB16  0  V EB 10   V EE  V BE14   0  V EE  1.4 V
For Q8 : V BC 8  V CC  V EB 8  V BE6  0  V CC  1.4V
So V CC  1. 4V and V EE  1.4V
b  We require forward- active region operation of all transistors with VIC present.
For Q14 : V CB14  V IC  V BE1  V EE  V BE14   1  0. 7   V EE  0.7  0  V EE  2. 4V
For Q1 : V CB1  V CC  V EB 6  V EB 4  V IC  V CC  0.7  0.7 1  0  V CC  2.4V
For an output range of  1V,
For Q16 : V CB16  V O  V EB10   V EE  V BE14   1  0  V EE  1.4V
For Q8 : V BC 8  V CC  V EB 8  V O  V BE 6   V CC  0.7  1  0.7  0  V CC  2. 4V
So V CC  2. 4V and V EE  2.4V
16.78
32
a I C 22  I C20 
V CC  V EB 22  V BE 20   V EE  3V  0.7  0.7  3V 

 46.0A
R1
100k
I C 23  3I C 22  138 A | I C 24  I C 22  46. 0 A |
V
I
0. 025V
46. 0A
46.0A
I1  T ln C 20 
ln
 6.25A ln
 I1  9.72A
R
I1
4k
I1
I1
22V  0.7  0.7  22V 
 426A
100k
I C 23  3I C 22  128 mA | I C 24  I C22  426 A |
V
I
426A
I1  T ln C 20  6. 25A ln
 I1  19.3A
R
I1
I1
b  I C 22  I C20 
c The input bias current and input resistance of the amplifier are directly
dependent upon I1 whereas the gain of the interior amplifier stages is
approximatley independent of bias current.
33
16.79
250A
 83. 3 A | I 3  I REF  83. 3 A
3
V  V EB 22  V BE 20   V EE 
12  0.7V  0.7  12 V
I REF  CC
| R1 
 271 k
R1
83.3
A
V
I
0. 025V
83. 3A
R 2  T ln REF 
ln
 255 
I1
I1
50A
50A
I 2  3I REF  IREF 
16.80
I REF  I3  300 A | I 2  3I REF  900 A
V CC  V EB 22  V BE 20   V EE 
15  0.7 V  0.7  15 V
| R1 
 95. 3 k
R1
300
A
V
I
0. 025V
300A
R 2  T ln REF 
ln
 462 
I1
I1
75A
75A
I REF 
16.81
For forward - active region operation of Q3 , V BC 3  0
V EE  V IC  V BE1  V BE 3  V BE7  V BE 5  V R 1
For forward - active region operation of Q1, V CB1  0
V CC  V EB 9  V IC
For the output stage, V CC  V BE15  V I3 = 0. 7 + 0.7 =1. 4 V
 V EB 16  V EB 12  V BE11  V R 5   V EE   V EE  3V BE  V R 1  2.1V
a V IC  0, V EE  4V BE  V R 1  2.8V | V CC  V EB 9  0  V CC  0.7V
Combining these results yields: V CC  1. 4V and V EE  2.8V
b  V IC  1, V EE  1  4V BE  V R1  3.8V | V CC  V EB 9  1  V CC  1.7V
If also account for the output stage, V CC  V O  V BE15  V I3 = 1+ 0.7 + 0.7 = 2. 4 V
Combining these results yields: V CC  2. 4V and V EE  3.8V
16.82
The input stage current is proportional to 1I: I C2 =
50A
7.32A = 20.3A
18A
Using Eq . 16.12: i o  2020.3Av id  0.406 mS v id | I C 4 =
50A
7.25A  = 20.1A
18A
 20.3A1k
60 V
R OUT6  r o 6 1 
 283 M
  1.81r o6 | 1.81r o6 2r o4  0. 952r o4  0. 95
0.,025
V
20.1A




i o  4.06 x 10-4 vid | R = 283 M
16.83
 r
50 60  15.7
 2. 84M | The cascode source uses up an extra VEB
a R 2  o 2 o2 
2
2 0.666mA
b  y 22   R OUT11 R 2  407k 2.84M  356k | Other y- paramters are unchanged.
c A dm  256 6.70mS 356k  6.11 x 10 5
1
34
16.84
16.85
g m10  40 19. 8A   0.792mS | r 10 
150 0.025 V
60V
 189k | r o10 
 3.03M
19.8A
19.8A
g m11  400.666mA   26. 6mS | r 11 
1500.025 V 
60V
 5.63k | r o11 
 90.1k
0.666mA
0. 666mA
*Problem 16.85 - Small Signal Parameters.
V1 1 0 DC 0
V2 4 0 AC 1
RPI10 1 2 189K
RO10 2 0 3.03MEG
GM10 0 2 1 2 0.792M
RE10 2 0 50K
RPI11 2 3 5.63K
RO11 4 3 90.1K
GM11 4 3 2 3 26.6M
RE11 3 0 100
R2 4 0 115K
.TF I(V2) V1
.AC LIN 1 1000 1000
.PRINT AC IM(V2) IP(V2) IM(V1) IP(V1)
.END
10
Results: y-1
S  0 | y 21  6. 66 mS | y-1
11  2.38 M | y 12  3.27 x 10
22  81. 9 k
16.86
I C11
 50A | I C 3  I C6  I C 4  50A
2
I
 2 C8
F
a Assume large  F : I C11  I REF  100A | I C 4  I C5 
I C1  I C 3  IC 7  50A | I C2  I C 6  IC 8  50A | I C9
V CE1  V CE 2  15  0.7   15. 7V | V EC 4  V EC 5  0.7V
V CE7  V CE 8  0.7  0. 7  1. 4V | V CE 9  15  15  0.7   29.3V | V CE10  0.7V
V EC 3  V EC 2  0  0.7   15  1. 4  12.9 | V CE11  0  0.7  0.7  15   13.6 V
1
2
3
4
5
6
7
8
9
10
11
IC (A)
100
100
-50
-50
-50
-50
50
50
---
100
100
VCE (V)
15.7
15.7
-12.9
-0.7
-0.7
-12.9
1.4
1.4
29.3
0.7
13.6
(b) Transistor Q11 replicates the reference current. This current divides in two and controls
two matched current mirrors formed of Q4-Q3 and Q5-Q6. The currents of Q1 and Q7, and
Q2 and Q8 are equal to the output current of Q3 and Q4.
(c) v1 is the inverting input; v2 is the non-inverting input.
35
g m5  g m6 | g m2  2g m6 | r o 8 = r o6 | i o  g m6 v e 6
gm 2
1
1
 vid | i o  g m6 vid
 1

2
2
1
1  g m2 

g m 5 g m6 
1
1
1
 g m 6  g m 2  40 100A   1.00 mS
2
4
4
ve 6  v id
Gm



1
R OUT  r o 8 R 6OUT  r o8 r o 6 1  g m6 

g m5  g m2 

R OUT  r o 8 1. 33r 06 
61. 4V
72. 9V
1.33
 752 k
50A
50A
16.87
I
a Assume large  F : I C 8  I REF  100A | I C10  I C 9  IB 8 = C8
F
I C 3  IC 4
I
I
I
  F C10  C 8  50AI C1  I C3  I C5  50A | I C 2  I C4  I C 6  50A | I C7  2 C5
2
2
F
V CE1  V CE 2  15  0.7   15. 7V | V CE5  V CE 6  0.7  0.7  1.4 V
V EC 3  V EC 4  0  0.7  15 1.4   12.9V | V CE 7  15  15  0.7   29.3V
V EC 8 = 0.7 + 0.7 =1. 4V | V CE 9  0.7V | V CE10  0  0.7  0. 7  15   13.6V
1
2
3
4
5
6
7
8
9
10
IC (A)
50
50
-50
-50
50
50
---
-100
---
---
VCE (V)
15.7
15.7
-12.9
-12.9
1.4
1.4
29.3
1.4
0.7
13.6
(b) Transistors Q9 and Q10 form a current mirror that replicates the base current of transistor
Q8. The output current divides in two and forms the base currents of Q3 and Q4. Since
Q3 and Q4 match Q8, the collector currents of Q1-Q6 will all be equal to IREF/2.
(c) v1 is the inverting input; v2 is the non-inverting input.
io
 g m 4 v e4 | i o  2g m 4 ve 4
2
v
g m2
1
v
 id
 v | i o  g m4 id
2
 1  4 id
2
1  g m 2 

g m4 
1
1
1
 g m 4  g m2  40 50A  1.00 mS
2
2
2
g m2  g m 4 | r o6 = r o 4 |
ve 4
Gm

 1 
R OUT  r o 6 R 4OUT  r o6 r o 4 1  g m4 

g m2 

R OUT  r o 6 2r o 4 
16.88
36
61.4 V
72.9V
2
 864 k
50A
50A
16.89
R

 R

 R

 R

a v O  0
V REF   1
V REF  1
V REF   0 
V REF   1.125 V

b  v O
 2R

 4R

 8R

 16R

R
  0  R V
  0  R V
 1  R V
  1. 688V
 1
 2R V REF 
  
 4R REF 
  
 8R REF 
  
 16R REF 


0000
0
0100
-0.750 V
1000
-1.500 V
1100
-2.250 V
0001
-0.188 V
0101
-0.938 V
1001
-1.688 V
1101
-2.438 V
0010
-0.375 V
0110
-1.125 V
1010
-1.875 V
1110
-2.625 V
0011
-0.563 V
0111
-1.313 V
1011
-2.063 V
1111
2.813 V
37
16.90
 1. 05R 
For an input code of 0000, v O  V OS 1 
 | R EQ  16R 8R 4R 2R  0.9375R
R EQ 

1. 05R 

v O  0.005 V 1 
 10.6 mV | The DAC offset voltage is +10. 6 mV
 0.9375 R 
1. 05R 
 1R 
1 LSB is now equal to VREF 
  0.06563 V REF instead of V REF 
  0.0625 V REF
 16R 
16R 
The DAC has a gain error of 5%.
16.91
Code
Output Voltage
Step Size (LSB)
DLE (LSB)
ILE (LSB)
000
0.0000
001
0.1000
0.8000
-0.2000
-0.2000
010
0.3000
1.6000
0.6000
0.4000
011
0.3500
0.4000
-0.6000
-0.2000
100
0.4750
1.0000
0.0000
-0.2000
101
0.6300
1.2400
0.2400
0.0400
110
0.7250
0.7600
-0.2400
-0.2000
111
0.8750
1.2000
0.2000
0.0000
LSB Size:
0.125
0.0000
16.92
Nominal Case
38
Code
Output Voltage
Step Size (LSB)
DLE (LSB)
ILE (LSB)
000
0.0000
001
0.1220
0.9719
-0.0281
-0.0281
010
0.2564
1.0716
0.0716
0.0434
011
0.3784
0.9719
-0.0281
0.0153
100
0.5000
0.9694
-0.0306
-0.0153
101
0.6220
0.9719
-0.0281
-0.0434
110
0.7564
1.0716
0.0716
0.0281
111
0.8784
0.9719
-0.0281
0.0000
LSB Size:
0.12548021
0.0000
Test Case -1
1
4R & 8R 5% Low, 2R 5% High
Code
Output Voltage
000
0.0000
001
Step Size (LSB)
DLE
ILE
0.1161
0.9169
-0.0831
-0.0831
010
0.2442
1.0110
0.0110
-0.0721
011
0.3603
0.9169
-0.0831
-0.1552
100
0.5263
1.3103
0.3103
0.1552
101
0.6425
0.9169
-0.0831
0.0721
110
0.7705
1.0110
0.0110
0.0831
111
0.8867
0.9169
-0.0831
0.0000
LSB Size:
0.12666572
Test Case - 2
1
Code
Output Voltage
000
0.0000
001
0.1284
1.0276
0.0276
0.0276
010
0.2699
1.1330
0.1330
0.1606
011
0.3983
1.0276
0.0276
0.1881
100
0.4762
0.6237
-0.3763
-0.1881
101
0.6046
1.0276
0.0276
-0.1606
110
0.7461
1.1330
0.1330
-0.0276
111
0.8745
1.0276
0.0276
0.0000
LSB Size:
0.12492367
4R & 8R 5% High, 2R 5% Low
Step Size (LSB)
DLE (LSB)
ILE(LSB)
0.0000
16.93 The five resistors are each assigned a random value, and the 16 output voltages are
calculated using these values. Then the step sizes, differential linearity error and integral
linearity error are found. This is repeated for 200 test cases using a spreadsheet.
R  1  0.1 * (RAND()  0.5)
R2  2 * 1  0.1* (RAND  0.5)
R 4  4 * 1  0.1* (RAND  0.5)
R8  8 * 1  0.1* (RAND  0.5)
R16  16 * 1  0.1 * (RAND  0.5)
Results: The worst case results observed in a number of trials - DLE = 0.66 LSB, ILE = 0.33
LSB
39
16.94 Note that the two switches should be driven with complementary signals.
1
R on 
| The worst - case condition for the switches occurs
 W 
K 'n   V GS  V TN  V DS 
 L 
for the one with VDS  0 and V SB  0. If V
V D  3V and V S  3V
REF
 3V and R ON  0.0110k  100
10k
 2.97 V | V DS = 0. 03V
10k  100
 2.97 + 0. 6 
V TN =1 + 0.5

.6 =1.56 V
W
1

 
 =

5
 L  5x10 100 5  2.97   1.56  0.03 
455 



 1 
 W 
1
50 
When the grounded transistor is on,V DS  0 |  =
  
5
 L  5x10 100 5 1  0   1 
16.95 Consider each bit acting by itself:
 R 1  0   V
1   0  1  1 
 0  1 
V REF 
   V REF
  REF  V REF 
2
2
2 
2

2R 1   1 
 R 1   0   V REF
 0   2 
V REF 
 V REF
 
4R
1


4
4
 
2 
 R 1   0   V
 0   3 
V REF 
 REF  V REF
8
8
8R 1   3  
Adding these together yields
V REF
 0   1   V
2
REF
 0   2   V
4
REF
 0   3   0.05V
8
REF
7



  1  2  3  0.05
8 0 2
4
8
Giving each term the same weight:
7

 0  1.25% and  0  1.43% | 1  1.25% and  1  2.5%  2  5%  3  10%
8
2
16.96
An n-bit DAC requires (n+1) resistors. Ten bits requires 11 resistors.
210 R 210

or 1024:1
R
1
A wide range of resistor values is required but it could be done. For R = 1 k, 1024R = 1.024
M.
40
16.97 Taking successive Thévenin equivalent circuits at each ladder node yields:
16.98
VTH
RTH
vO
0001
VREF/16
R
-0.3125 V
0010
VREF/8
R
-0.6250V
0100
VREF/4
R
-1.250 V
1000
VREF/2
R
-2.500 V
Note: The feedback resistor should be 1.2188kto give the ideal step size.
Code
Output Voltage
Step Size (LSB)
DLE (LSB)
ILE (LSB)
000
0.000
001
-0.739
1.182
0.182
0.182
010
-1.434
1.112
0.112
0.294
011
-2.089
1.048
0.048
0.342
100
-2.708
0.990
-0.010
0.333
101
-3.294
0.938
-0.062
0.270
110
-3.849
0.888
-0.112
0.158
111
-4.375
0.842
-0.158
0.000
LSB Size:
-0.625
0.000
16.99
RREF = 0
R1= 2.2kR2 = 4.2k R3
=8.2k
R
1.0742 k
Code
Output Voltage
000
0.0000
001
-0.6550
1.0480
0.0480
0.0480
010
-1.2788
0.9981
-0.0019
0.0460
011
-1.9337
1.0480
0.0480
0.0940
100
-2.4413
0.8121
-0.1879
-0.0940
101
-3.0962
1.0480
0.0480
-0.0460
110
-3.7200
0.9981
-0.0019
-0.0480
111
-4.3750
1.0480
0.0480
0.0000
LSB Size:
-0.6250
1.0000
Step Size (LSB)
DLE (LSB)
ILE (LSB)
0.0000
41
RREF = 250 
R
1.2929 k
Code
Output Voltage
000
0.0000
001
-0.7650
1.2241
0.2241
0.2241
010
-1.4527
1.1003
0.1003
0.3243
011
-2.1353
1.0922
0.0922
0.4165
100
-2.6386
0.8052
-0.1948
0.2217
101
-3.2573
0.9900
-0.0100
0.2117
110
-3.8167
0.8950
-0.1050
0.1067
111
-4.3750
0.8933
-0.1067
0.0000
LSB Size:
-0.6250
1.0000
Step Size (LSB)
DLE (LSB)
ILE (LSB)
0.0000
16.100 Note: The areas of the left four transistors should be 128A, 64A, 32A, 16A.
I
Let R1 be the scaling resistor to be found. The total current through R1 is R .
8
1 IR
V REF  V BE 
R
I
 F 8 1 V REF  V BE
1 IR
1 I R R1
For the R transistor: I E16 

=

16
 F 16
R
R
F 8 R
However, for the I R transistor: I E1 
V REF  V BE
I
 R
R
F
1 IR
I
1 IR R1
15
 R 
 R1 
R
 F 16  F  F 8 R
2
16.101
For this design, two three- bit sections are connected through a scaling resistor R1 .
I
Let R1 be the scaling resistor. The total current through R1 is R .
4
I
If I R is the current in the MSB, then the first transistor in the second section hasCI  R
8
1 IR
V REF  V BE 
R
IR
1 IR
 F 4 1 V REF  V BE
1 IR R1
For the
transistor: I E 8 

=

8
F 8
R
R
F 4 R
V REF  V BE
IR
1 IR
IR
1 IR R1
7
However, for the I R transistor: I E1 

|


 R1  R
R
F
F 8
F F 4 R
2
V
 V BE
3  0.7
7
R = REF
 6
 1.438 k | R = 5.031 k | 2R  2.875 k | 4R = 5.750 k
IMSB
2
2 25A 
16.102
42
n
a The n- th bit requires 2 n C, and the feedback capcitor= C: C TOTAL   2i C  2 n1  1C
i 0
b  Each bit requires (C + 2C), and a single terminator is required: C TOTAL  3n  1C
16.103
*Problem 16.103 - C-2C Ladder
VREF 9 0 DC 5
VB3 8 0 PWL (0 0 5N 0 10N 10 50N 10 55N 0 100N 0)
VB3B 7 0 PWL (0 10 5N 10 10N 0 50N 0 55N 10 100N 10)
M1 6 7 0 0 NFET W=10U L=1U
M2 9 8 6 6 NFET W=10U L=1U
C1 1 0 0.5PF
C2 1 0 0.5PF
R1 1 0 1T
C3 1 2 1PF
C4 2 6 0.5PF
R2 2 0 1T
C5 2 3 1PF
C6 3 0 0.5PF
R3 3 0 1T
C7 3 4 1PF
C8 4 0 0.5PF
R4 4 0 1T
CF 4 5 1PF
RF 5 4 1T
E1 5 0 0 4 1E6
.MODEL NFET NMOS KP=25U VTO=0.75 PHI=0.6 GAMMA=0 LAMBDA=0.017
.OP
.TRAN 0.5N 60N
.PROBE
.END
16.104
V
a I DAC  I O  I REF | I O  I DAC  I REF  I DAC  REF
1000
| V O  5000I O  5000I DAC  5
5mV
2mA
 5A | 1 LSB =
 125A | I OS is negligible.
b  I OS 
4
1k
2
43
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
-5.000
-4.375
-3.750
-3.125
-2.500
-1.875
-1.250
-0.625
0.000
0.625
1.250
1.875
2.500
3.125
3.750
4.375
000
001
010
011
100
101
110
111
-2.500
-1.875
-1.250
-0.625
-0.000
0.625
1.250
1.875
16.105
16.106 Note that the resistor width should be 5 m. The DAC will require 1024 resistors of
equal value. Suppose R = 500 . This requires 10 squares per resistor or 10240
squares. For a 5 m width, the total length would be 0.0512 m or 5.12 cm.
5.12
cm/2.54 cm/in = 2.02 in! Note that contacts have been neglected in this estimate.
44
16.107
ADC code is equivalent to 2-1  23  2 5  2 7  2 9  2 10  2 13 x V FS  0.66711426 x V FS


The ADC input may be anywhere in the range
:
1


0.66711426  LSB x V FS  3.4154625 V  0.15625 mV | 3.415469 V  V X  3.415781V


2
16.108
a 1 LSB =
2V
 1. 90735 V
220 bits
1. 63V 20
2  854589.4 bits  85458910  11010000101000111101 2
2V
0. 997003 V 20
2  522716. 7 bits  522717 10  01111111100111011101 2
c
2V
b 
16.109
The quantization error is always positive and can be as large as 1 LSB. Both these
characteristics are undesirable. Note, however, that the properly offset ADC does have a
large quantization error for inputs approaching the full scale range of the converter.
16.110
Use fc = 1MHz.
3.760 V 12
1541
a
2  1540. 01 bits 154110  0110000001011 2 | T T 
 1.541 ms
10V
fC
7. 333V 12
3004
2  3003.6 bits  300410  101110111100 2 | T T 
 3. 004 ms
b 
10V
fC
16.111
1 LSB =
5.12 V
5.000 mV
n

|t=
 10 6 n | The conversion is complete when
210 bits
bit
fC


-6
the counter ramp first exceeds the input voltage
: 0.005n  5cos 5000 10 n

Using MATLAB, n = 94.0065  n = 9510  0001011111 2 | T T = 95 s
16.112
a 0.1 LSB  0.1
16.113
2V
12
2 bits
 48.8 V b  0.1 LSB  0.1
2V
2
20
bits
 0.191 V
1
 20.0 s.
5x10 4
Twelve decisions must be made during this timeignoring the final logic decision.
The total conversion time is TT =
The time for each decision is
20.0s 1.67s

| f C  600kHz |
12
bit
0.1 bit 1. 67s  167 ns
bit
16.114 Note: Part (b) should refer to a single-ramp converter
45
a V 'REF  3.00  0.01  2.99 V
T
T
b  1  3dt  5.12V | 3 1  5.12  RC  19.53 mS | C = 19.53mS  0.391 F
RC 0
RC 30
50k
16.115
Ao s
1
R
sCR
5
|  s  

| V S s  
1
sRC 1  A o s 
sCR

1
s
R
sC
sCR


A
1  o sCR  1 
Ao
1
Ao
1
As   
sCR    sCR A  1 1   RC 1  A
1
sRC 
o
o s
1  A o


sCR 1 
RC A o  1
As   
V O s   
A
1
Ao 5
RC 1  A o s s 
1
1
RC A o 1

A

s s
B
1
RC A o  1
5
Ao
5
Ao
RC A o 1  5A o  2.5x10 5 | B  
RC A o  1  5A o  2.5x10 5
RC 1  A o
RC 1  A o


1

1
t


5
 | v O t   2. 5x105 1  exp
V O s   2.5x10  
 for t  0
4
1

5x10 RC 
s s 


RCA o  1


The output of an ideal integrator at t= 200ms would be v O 200ms  
Desire:
5
0.2s  1
RC
RC
1
0.2 
5 
 2.5x10 1  exp
  0. 001  RC  0. 0447 using MATLAB
4
RC

5x10 RC 
Note however, for the minimum RC = 0.0447, v O 0.2s  22.4 V.
16.116
The time corresponding to1 LSB is T LSB 
16.117
V O   
1
RC
TT

v tdt 
0
For  = 0, V O   
16.118
16.119
46
1
RC
TT
 V M cost   dt 
0
0. 2s
20
2
bits
V M t 
VM
cos x dx 
sinT T     sin 
RC 
RC
V M sin T T
V T sin T T 
 M T 

RC

RC  T T 
NR  2 n
and
 190.7 ns | 0.1T LSB  19.1 ns
NC  2n  1


y11 1  r    o  1R E  r    o R E  r  1  g m R E  |
y 21 
y 22 
r '  r  1  g m R E 
o
o
gm
gm


| g 'm 
r    o 1R E r  1  g m R E  1  g m R E
1  g mR E
1


g R
 r o 1  m R E
E

 1  r




  r o 1  g m R E  for R E  r  or I CR E   o V T  2.5V



r 'o  r o 1  g m R E  | Note:  'o  g 'm r '   o and  'f  g 'm r 'o   f are both conserved.
16.120
For R th  0, R OUT
R OUT









 oR E
g mR E
g R 
 r o 1 
 = r o 1  m E 
  r o 1 
R th  R E 
R E 
 R th  r   R E 


 1 

 1 

r
r  






g mR E
= r o 1 
IC R E

 1   V

o T


  r o 1  g m R E  for IC R E  o V T | For common values,



 o V T  100 0.025V   2.5V, and the approximation holds for I CR E  2.5V
47