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Facelift: Hiding and Slowing
Down Aging in Multicores
Abhishek Tiwari and Josep Torrellas
August 11, 2009
Presented by Peter F. Klemperer
Computer Architecture Lab at
Facelift Goals
• “Facelift hides the effects of aging in a multicore
by steering high-T jobs to the fast core and lowT ones to the slow cores”
– 14-15% higher average clock speed
– Increase service life (months  years)
– Decrease design effort
• 2 Techniques:
– Scheduling to reduce temperature per core
– Modifying voltage parameters
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Transistor Wear-out Factors
• Ageing modes modeled:
– NBTI – Negative Bias Temperature Instability - PMOS
– HCI – Hot Carrier Injeciton - NMOS
– Process Variation
• Transistor Switching Delay (Ts)
• Increased threshold voltage (Vt) Higher Delay
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Ageing and Vt
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Modeling Ageing
• Critical path delay depends on the transistor that
charge or discharge output nodes.
• CACTI Simulates Age-less delay
• Multiply ageing effect of NBTI and HCI by the
number of activated transistors.
• Vt = Vt0 + ΔVt
• Example: Chain of FO4 Inverters.
N-P-N
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Facelift Framework
• Degradation of Critical Path Delay
– Guard Band (G0) gradually consumed
– Frequency (f0) limited by worst case delay (τ0)
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Benefits of Flattening the Curve
Same Clock
Decreased Guard
Band
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Benefits of Flattening the Curve
Faster
Clock
Decreased Guard
Band
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Aging Driven Scheduling
• Frequency variation between cores of 20%
– P1 slowest, P2 fastest
• Ageing driven scheduling merges the delay
• Faster cores age faster, but effect is hidden
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Chip-wide ASV/ABB
• Adaptive Supply Voltage (ASV)
– ASV+ increase Vdd
– ASV- decrease Vdd
• Adaptive Body Bias (ABB)
– FBB decrease Vt
– RBB increases Vt
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Non-Linear Optimization
• Combine slow age and high speed
• Decrease relative delay increase
• Optimize ttrans, Vdd, Vbb to get lowest Delay (S)
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Experimental Setup
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Scheduling Results
• Delay increase reduced from 23% to 14%
• Average and Max Temperature reduced
• Range of temperatures reduced
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Scheduling Results, cont’d
• Increase frequency and retain service life
• Average of 100 cores and spread
• 4% and 9% increases, regains 35-40% of loss
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Chip-Wide ASV
• ASVS+H
– 4% to 9% freq increase
• ABBS+H
– 7% frequency increase
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Combining Sched and ASV
• Sched + ASVS+H
– 8% and 14% freq increase
• Sched + ABBS+H
– 11% to 15% freq increase
• 8-11%, 15-16%
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critical path simplification
Figure 15
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Figure 16
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Figure 17
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Figure 18
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