* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Download Presentation title
Survey
Document related concepts
Variable-frequency drive wikipedia , lookup
Alternating current wikipedia , lookup
Utility frequency wikipedia , lookup
Switched-mode power supply wikipedia , lookup
Buck converter wikipedia , lookup
Chirp spectrum wikipedia , lookup
Mains electricity wikipedia , lookup
Resistive opto-isolator wikipedia , lookup
Voltage optimisation wikipedia , lookup
Thermal runaway wikipedia , lookup
Power MOSFET wikipedia , lookup
Magnetic core wikipedia , lookup
Transcript
Facelift: Hiding and Slowing Down Aging in Multicores Abhishek Tiwari and Josep Torrellas August 11, 2009 Presented by Peter F. Klemperer Computer Architecture Lab at Facelift Goals • “Facelift hides the effects of aging in a multicore by steering high-T jobs to the fast core and lowT ones to the slow cores” – 14-15% higher average clock speed – Increase service life (months years) – Decrease design effort • 2 Techniques: – Scheduling to reduce temperature per core – Modifying voltage parameters 2 Transistor Wear-out Factors • Ageing modes modeled: – NBTI – Negative Bias Temperature Instability - PMOS – HCI – Hot Carrier Injeciton - NMOS – Process Variation • Transistor Switching Delay (Ts) • Increased threshold voltage (Vt) Higher Delay 3 Ageing and Vt 4 Modeling Ageing • Critical path delay depends on the transistor that charge or discharge output nodes. • CACTI Simulates Age-less delay • Multiply ageing effect of NBTI and HCI by the number of activated transistors. • Vt = Vt0 + ΔVt • Example: Chain of FO4 Inverters. N-P-N 5 Facelift Framework • Degradation of Critical Path Delay – Guard Band (G0) gradually consumed – Frequency (f0) limited by worst case delay (τ0) 6 Benefits of Flattening the Curve Same Clock Decreased Guard Band 7 Benefits of Flattening the Curve Faster Clock Decreased Guard Band 8 Aging Driven Scheduling • Frequency variation between cores of 20% – P1 slowest, P2 fastest • Ageing driven scheduling merges the delay • Faster cores age faster, but effect is hidden 9 Chip-wide ASV/ABB • Adaptive Supply Voltage (ASV) – ASV+ increase Vdd – ASV- decrease Vdd • Adaptive Body Bias (ABB) – FBB decrease Vt – RBB increases Vt 10 Non-Linear Optimization • Combine slow age and high speed • Decrease relative delay increase • Optimize ttrans, Vdd, Vbb to get lowest Delay (S) 11 Experimental Setup 12 Scheduling Results • Delay increase reduced from 23% to 14% • Average and Max Temperature reduced • Range of temperatures reduced 13 Scheduling Results, cont’d • Increase frequency and retain service life • Average of 100 cores and spread • 4% and 9% increases, regains 35-40% of loss 14 Chip-Wide ASV • ASVS+H – 4% to 9% freq increase • ABBS+H – 7% frequency increase 15 Combining Sched and ASV • Sched + ASVS+H – 8% and 14% freq increase • Sched + ABBS+H – 11% to 15% freq increase • 8-11%, 15-16% 16 critical path simplification Figure 15 17 Figure 16 18 Figure 17 19 Figure 18 20