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LPNHE - Serial links for Control in 65nm CMOS technology G.Calderini, F.Crescioli, J.F. Genat, O.LeDortz - 65nm CMOS - Higher density, less material, less power Enhanced radiation hardness (@ regular layout) Extensive existing standard cells libraries, some rad-hard (Avago…) Inverter delay = 20ps… 65 nm PDK received today (May 14th) Jean-Francois Genat May 14th 2012 Designs - Two steps - Non rad hard development with present available libraries - Rad hard design using CERN design kit (see below) - CERN - A. Marchioro is evaluating 65nm CMOS providers (UMC, ST, TSMC, IBM) - CERN will make a decision and provide in November a design-kit + radhard libraries to the community - Present design kit (Europractice) - Focus on reliability at moderate speed O(few 100MHz) - Enhanced radiation hardness (@ regular layout) using redundancy techniques: triplication and vote, skewed clocks etc… - Use full custom and existing standard cells libraries from Europractice - Design strategy - Analog SPICE post-layout simulations whenever felt needed (SerDes) TSMC CMOS 65nm process and libraries Analog: Mixed-signal + RF - Voltage supply: core 1.0, 1.2V 1.8, 2.5, 3.3V I/O transistors - MiM and MoM (metal-oxide) caps - Thick copper for inductors - Diodes - Poly diff, N-well resistors - Deep N-well (noise immunity) Digital: - General purpose std cells 850kGate/mm2 - Very low power 0.8, 1V - 10-12LM TSMC 65nm: 35 different flavours of libraries from Synopsys http://www.magma-da.com/partners/standardcelllibs_65nm.aspx Radiation Hardness 65nm SRAM @ <100kRad TID (TNS Vol.57 n4 Aug 2010 pp2079-2088) Control serial link - Service serial link Use simple SPI (Serial Peripheral Interface) protocol PLL based frequency control JTAG controller (Testability) Very strong radiation hardness needed (sLHC requires 50-500 Mrads optimized design required at the transistor level) - Error Correcting Codes sized to very low Bit Error Rates in0 sel0 Goal: build a library of logic blocks specialized for readout applications ou t sel in1 sel1 Std cell kit compatible – Easy to synthesize readout trees – Usable by automatic place&route programs (ie. Cadence Encounter) Basic building block → std cell Optimized to minimize routing First implementation of the MEPHISTO binary readout architecture for strip detectors P.Fischer NIM-A (2001) pix pix FIFO FIFO pix pix FIFO FIFO pix pix FIFO FIFO pix pix FIFO FIFO – Compact and regular designs – Less time spent on routing Serial Readout Ctrl logic To be integrated with INFN Milano std cell design efforts. Develop a tight collaboration and a common characterization framework. addr+ data Pixel address and additional data can be multiplexed using the sel signal From Francesco Crescioli Manpower at LPNHE J.F. Genat (IR) O. Le Dortz (IR) F. Crescioli (IR) (about 2 FTE in total)