Download 3-Stage Transimpedance Amplifier

3-Stage Transimpedance Amplifier
ECE 3400 - Dr. Maysam Ghovanloo
Garren Boggs
Vasundhara Rawat
December 11, 2015
TEAM 11
Project Specifications and Design Approach
Goal: Design a 3-stage transimpedance amplifier to amplify input current from a piezoelectric transducer with Is = 5 µA amplitude and 1 MΩ output impedance.
The TIA will drive a 50 Ω load with a gain of 1 MΩ. The amplifier should also have a low pass filtering capability to only amplify the ultrasound signals lower than
10 MHz.
Stage 1: Common Gate (Required to be FET)
◦ Must have an input impedance ≤ 100 Ω. This is to maximize the source current entering the amplifier. Common-gate was selected for its low small signal impedance
◦ This first stage also allowed for a decent gain.
Stage 2: Common Emitter
◦ This stage was primarily utilized for high gain. BJT’s more commonly produce higher signal gain over FET’s.
Stage 3: Common Drain
◦ Utilized as a current-driving follower circuit in order to match the low load impedance of 50 Ω. The FET’s infinite input impedance was very useful as well.
Approach:
◦ Analyze 4 resistor bias networks to set DC operating points for each stage of the amplifier.
◦ Select starting point by setting a key parameter to a desired value, and solving for unknowns using that parameter.
◦ Maximize gain for each stage while minimizing power dissipation.
◦ Simulate each stage and verify that the results match the by-hand calculations (shown on next slide).
◦ Decouple and bypass the DC bias from the AC input signal, and unify all 3 stages. Verify the final result to the project specifications.
1
𝑔𝑚
.
Figure 1. Mathcad calculations for biasing each stage of the overall TIA amplifier.
Finalized 3-Stage Amplifier Circuit
The completed 3-stage amplifier design is
shown on the right:
◦ The input current source is located between
Stage 1 and Stage 2.
◦ The output load is located to the right of
Stage 3.
Resistor/capacitor values and transistor
parameters used in the design are listed
next to their respective components.
The circuit was constructed and simulated
using Multisim.
Figure 2. Multisim schematic of the completed 3-stage amplifier design.
Amplifier Gain
The gains achieved for each stage are as follows:
◦ Stage 1: 74.84 dB = 5520.77 Ω
◦ Stage 2: 45.06 dB = 179.06 Ω
◦ Stage 3: -1.13 dB = 0.878 Ω
The overall midband gain for the TIA is:
◦ Overall: 118.78 dB = 868.96 kΩ
While the total gain does not meet the specified 1 MΩ, it
comes substantially close. These limitations on gain most
likely arise from impedance mismatching, clipping, and
limitations on power consumption.
Some of the above limitations also describe why the second
stage of the TIA would have a lower gain than the first.
When the bypass capacitors are removed, the overall
midband gain for the TIA is:
◦ No Bypass Capacitor Gain: 84.54 dB = 16.87 kΩ
Figure 3. AC analysis showing the gain provided by each stage, as
well as the total amplifier gain. Stage 1 gain is shown in blue. Stage 2
gain is shown in purple. Stage 3 gain is shown green. The total
transimpedance gain is shown in red.
Input and Load Impedance
The input impedance for stage 1 of this amplifier is
calculated using:
𝑹𝒊𝒏 = 𝑹𝑺 ||
𝟏
𝒈𝒎
𝑹𝒊𝒏 = 𝟕. 𝟖𝟒𝟑𝒌Ω||𝟗𝟗. 𝟎𝟏Ω
The load impedance for the output of this amplifier is
calculated using:
𝑹𝑳𝑶𝑨𝑫 = 𝑹𝑳 ||𝑹𝑺 ||𝒓𝒐
(values from Fig. 1)
𝑹𝑳𝑶𝑨𝑫 = 𝟓𝟎Ω 𝟔𝟐. 𝟖𝟓Ω 𝟑. 𝟕𝟖Ω
(values from Fig. 1)
𝑹𝒊𝒏 = 𝟗𝟕. 𝟕𝟖Ω
𝑹𝑳𝑶𝑨𝑫 = 𝟑. 𝟑𝟐Ω
The input impedance to the common gate stage is simply
the parallel combination of the source biasing resistor with
the small signal input impedance of the transistor.
Taking RL = 50 Ω the load impedance seen at the output is
the parallel combination of the connected load, the source
biasing resistor, and the small signal output impedance of
the transistor.
By biasing the first stage the way it is, a large (relative) value
for gm was achieved, thus allowing it to be the defining
factor for the input impedance.
The input impedance of the TIA meets the specified criteria
for design of ≤ 100 Ω.
By biasing the third stage the way it is, a very large (relative)
value for gm was achieved, thus allowing it to be the
defining factor for the load impedance.
The load impedance of the TIA permits a large current gain
in order to drive the specified 50 Ω load.
Bandwidth Analysis
The specification for this design regarding bandwidth was
that the TIA must act as a low-pass filter for frequencies less
than 10 MHz.
In order to accomplish this, a shunt capacitor, Cshunt, was
connected in parallel to the input of stage 3, bypassing
some of the AC current to ground. An AC voltage divider had
essentially been constructed for high frequencies.
In order to determine the value of Cshunt, the resistance that
this capacitor saw from one terminal to its other was
calculated. Then, the cutoff frequency was equated using:
𝑓𝑐 =
1
2𝜋∗𝑅𝑐𝑠 ∗𝐶𝑠ℎ𝑢𝑛𝑡
Taking fc = 10 MHz, Cshunt = .691 pF.
The design shows a successful cutoff frequency at 10 MHz
with a gain of -3.0125 dB from the midband gain.
Figure 4. AC analysis showing the 10 MHz bandwidth for the
amplifier.
Input and Output Voltage Range
Ideally the TIA would have an input range of ±5
mVpp (Thevanin equivalent induced from the
current source) and an output range of ±5 Vpp.
However, due to clipping from such a large gain,
the actual limits are as such:
◦ Input Voltage Range: ±0.23 mVpp
◦ Output Voltage Range: −1.78 Vpp to 1.87 Vpp
This discrepancy in the output voltage is due to
a linear DC offset built up at the output of each
stage. Thus, during the design process in order
to maximize these ranges, an attempt was made
to zero the DC offset voltages at each of the
output nodes (this process can be seen in the
calculations in Fig. 1)
Bias points were also chosen for each stage,
such that they would stay within the forward
active or saturation regions of operation.
Figure 5. Transient analysis showing
the output voltage waveform at the
maximum input voltage range (0.23
mVpp), just before clipping occurs.
Figure 6. Transient analysis showing
the output voltage waveform at the
ideal input voltage range (0.5 mVpp).
Due to circuit limitations, clipping
occurs.
Rise and Fall Time
It is desirable to minimize the rise and fall time, as it has a direct dependence on the speed of a device. This design is no different. The rise and fall times were
measured through transient analyses using a step current source. The measured rise and fall times corresponded with the time between obtaining 10% and 90%
of the maximum or minimum value of the output.
In order to decrease the rise/fall time, the decoupling capacitor at the output must be decreased, to decrease the time constant. However, the tradeoff with this
lies with the causation of a smaller bandwidth.
Measured Rise Time: 107.86 μs
Measured Fall Time: 107.63 μs
Figure 7. Transient analysis showing the output
response to a step wave and its rise time.
Figure 8. Transient analysis showing the output
response to a step wave and its fall time.
Distortion
One of the specifications for this design is to have as low of
total harmonic distortion as possible.
In order to determine the THD of the amplifier, a Fourier
analysis was run on the output, using an input signal with a
fundamental frequency of 1000 Hz. The value for input
signal was chosen to be .23 mVpp, to avoid clipping.
Any clipping that would occur would dramatically skew the
THD reading.
The THD of the amplifier was approximately 8.54%.
As the gain of the amplifier increases, clipping becomes
more prominent and thus the THD increases.
Figure 9. Fourier analysis showing THD and contributions from the
first nine harmonics.
PSRR and Power Consumption
In order to measure the PSRR of the TIA, small AC voltage
sources were added in series to the power supplies and the
input signal was disconnected. A transient analysis was then
run to determine the relative value for the output voltage.
The PSRR was then calculated:
◦ PSRR+: -9.54 dB
◦ PSRR-: -14.77 dB
The power consumption for the TIA could be calculated by
multiplying the two power supply voltages Vdd and Vss, the
total DC current that is biasing the three stages.
Total Power Consumption: 707 mW
The power consumption of the TIA meets the specified
criteria for design of ≤ 1 W.
Figure 10. Mathcad calculations for determining total power
consumption.
Feedback Implementation
Adding feedback to the TIA design will
give it more stability, however there are
some tradeoffs. In exchange for a larger
bandwidth, the feedback reduces the
overall midband gain of the TIA.
Figure 11. (Above) Multisim schematic of the TIA
design implemented with a shunt feedback system
(highlighted in blue).
Previously, without feedback this
amplifier could not achieve the intended
±5 mVpp input swing. However, with
feedback in place, the reduced gain allows
the full undistorted output waveform to
pass.
A 700k resistor has been chosen for RF as
it maximizes the bandwidth enlargement
while minimizing reduction in gain.
If the 10 MHz bandwidth is still desired in
addition to feedback, the capacitor Cshunt
can be adjusted until the bandwidth again
meets specifications.
Figure 12. (Above) AC analysis showing a decrease in
TIA gain, but an increase in bandwidth.
Figure 13. (Right)
Transient
analysis
showing the ideal
input voltage range
without clipping.