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Int. J. Electron. Commun. (AEÜ) 65 (2011) 794–798 Contents lists available at ScienceDirect International Journal of Electronics and Communications (AEÜ) journal homepage: www.elsevier.de/aeue Component reduced ﬂoating ±L, ±C and ±R simulators with grounded passive components Mehmet Sagbas ∗ Department of Electronics Engineering, Maltepe University, 34857 Maltepe, İstanbul, Turkey a r t i c l e i n f o Article history: Received 1 February 2010 Accepted 9 January 2011 Keywords: Current backward transconductance ampliﬁer Floating inductor simulator Immittance simulator Active networks Analog signal processing circuits a b s t r a c t In this study, a novel immittance simulator circuit is proposed. The proposed circuit can simulate any one of the ﬂoating positive or negative inductor simulator (±L), positive or negative capacitor simulator (±C) and positive or negative resistor simulator (±R). It uses only one current backward transconductance ampliﬁer (CBTA) and two grounded passive components. The proposed simulator can be tuned electronically by changing the transconductance value of the CBTA. Moreover, the circuit does not require any conditions of component matching. It has a good sensitivity performance with respect to the tracking errors and the passive components. The performance of the proposed immittance simulator is demonstrated on the fourth-order voltage- and current-mode band-pass ﬁlters by using Pspice simulations based on the 0.25 m TSMC level-7 CMOS technology parameters. © 2011 Elsevier GmbH. All rights reserved. 1. Introduction The immittance function simulator can be applied in areas like oscillator design, active ﬁlters, chaos circuits and cancellation of parasitic elements. Consequently, it has become a standard research topic. The advent of integrated circuits has encouraged the design of synthetic inductors, which can be used instead of the physical inductors in passive ﬁlters. Furthermore, physical inductors are usually unwanted passive components in most of the electronic conﬁgurations because their characteristics are far from the ideal element behaviors. In addition, they occupy larger chip area when compared to the other passive components such as resistors and capacitors [1]. Although, it is difﬁcult to implement inductors and ﬂoating capacitors in the integrated circuits, several published circuits employing various active devices overcome this difﬁculty [2–14]. However, they suffer from one or more of the following drawbacks: (i) Use of an excessive number of active components, since, power consumptions are important for the circuit designers, they look for simple structures employing no more than a single active element. (ii) Use of high number of passive components. Moreover, a network using a minimum number of active and passive components is important from the VLSI implementation point of view. (iii) Requiring any component matching. (iv) Use of grounded passive component, since, a circuit using a grounded capacitor and without requiring passive component matching con- ∗ Corresponding author. Tel.: +90 216 626 10 50. E-mail addresses: [email protected], [email protected] 1434-8411/$ – see front matter © 2011 Elsevier GmbH. All rights reserved. doi:10.1016/j.aeue.2011.01.006 straints is very suitable for IC technology [15,16]. (v) Realizing only grounded simulator circuits. In this work, a novel ﬂoating inductor, capacitor and resistor simulator circuit depending on the passive element choice is presented. The proposed circuit consists of only one CBTA as active component, one grounded capacitor and one grounded resistor for the ﬂoating inductor and capacitor simulators, one CBTA and two grounded resistors for the ﬂoating resistor simulator. The proposed circuit can simulate any one of the ﬂoating ±L, ±C and ±R, for which all values can be adjusted electronically by changing the transconductance value of the CBTA. The negative passive component resistance, capacitance and inductance can be used for the cancellation of the positive parasitic values, resistive, capacitive and inductive, respectively [17]. The proposed circuit does not require any component matching and it is tested in the fourth-order resistively terminated LC band-pass ﬁlter. 2. Current backward transconductance ampliﬁer A recent publication [18] introduced the concept and an implementation in the form of a circuit building block termed current backward transconductance ampliﬁer. The circuit symbol of the CBTA with reference directions of the signals and its equivalent circuit are given in Fig. 1. It can be characterized by the following equations considering the non-ideal conditions: Iz = gm (s)(Vp − Vn ), In = −˛n (s)Iw Vw = w (s)Vz , Ip = ap (s)Iw , (1) M. Sagbas / Int. J. Electron. Commun. (AEÜ) 65 (2011) 794–798 795 Fig. 1. (a) Block diagram of the CBTA. (b) Equivalent circuit of the CBTA. Table 1 The dimensions of the CMOS transistors. W (m)/L (m) PMOS transistors M3 –M9 M15 M16 , M17 , M23 –M27 , M29 M28 and M30 NMOS Transistors M1 , M2 , M13 , M14 M10 –M12 M18 , M19 M20 M21 and M22 M31 and M32 M33 and M34 20/1 1/0.25 2.5/0.25 10/0.25 Fig. 3. (a) Floating admittance. (b) Floating admittance simulator circuit. 10/1 2.5/1 0.5/0.25 2.5/0.25 2/0.25 2.25/0.25 10/0.25 In these equations ˛p (s), ˛n (s) and (s) are the current and voltage gains, respectively and they can be expressed as ˛p (s) = ω˛p (1 − ε˛p )/(s + ω˛p ), ˛n (s) = ω˛n (1 − ˛n )/(s + ω˛n ), gm (s) = go ωgm (1 − εgp )/(s + ωgm ) and w (s) = ωw (1 − εw )/(s + ωw ) with |ε˛p | 1, |ε˛n | 1, |εgm | 1, and |ε | 1, where, go is the DC transconductance gain. ε˛p and ε˛n denote the current tracking errors, ε denotes the voltage tracking error, εgm denotes the transconductance error and ω˛p , ω˛n , ωgm , ω denote the corner frequencies. Note that, in the ideal case, the voltage and current gains are w (s) = 1 and ˛p (s) = ˛n (s) = 1, respectively. The non-ideal effects are discussed in Section 4. The CMOS implementation of the CBTA is given in Fig. 2 [19,20]. The dimensions of the MOS transistors used in the CBTA implementation are given in Table 1. In Fig. 2, the transconductance section is realized by using the transistor M15 –M22 that is formed by MOS coupled pair and current mirrors. Where, vin is the differential input voltage (vin = vp − vn ), io is the output current of the transconductance section and IB is the bias current. We will assume that all the MOS devices operate in the saturation region. Let us assume that M19 and M20 are perfectly matched and the current mirrors have unity current gain. io can be given by io = gm vin = ( 2IB K)vin (2) where, the transconductance parameter K = Cox W/2L, is the mobility of the carrier, Cox is the gate-oxide capacitance per unit area, W is the effective channel width, L is the effective channel length. The studies mentioned above prove that the CBTA is a versatile building block for the voltage- and current-mode signal-processing applications. Considering these facts, in this study, the novel ﬂoating inductor, capacitor and resistor simulator circuits are proposed. 3. The proposed ﬂoating inductor, capacitor and resistor simulator circuit Consider the ﬂoating admittance in Fig. 3a and the simulator circuit in Fig. 3b. The short-circuit admittance matrices of these circuits can be respectively written as [yij ] = y11 y21 [yij ]=˛w gm Y1 Y2 y12 y22 = Yf +1 −1 −1 +1 Fig. 2. The CMOS implementation of the CBTA. +1 −1 −1 +1 , (3a) , where ˛p ≈ ˛n = ˛, and Ip In = [yij ] Vp Vn (3b) 796 M. Sagbas / Int. J. Electron. Commun. (AEÜ) 65 (2011) 794–798 Normalized active and passive sensitivities of the inductance Lf , the capacitance Cf and the resistance Rf are given by yij ij = 1 = Sgym SYyij = −SYyij = S˛yij = S w 1 (3c) 2 (i) If the admittances are chosen as Y1 = G1 and Y2 = sC2 , the input admittance becomes gm G1 [YL ] = ˛w sC2 +1 −1 −1 +1 1 = sLf +1 −1 −1 +1 (4) which represents a ﬂoating inductor whose inductance is given by Lf = (1/˛w )(C2 /gm G1 ). In the ideal conditions Lf = C2 /(gm G1 ). This means that the ﬂoating admittance, Yf , in Fig. 3a can be simulated using the circuit in Fig. 3b and behaves as a ﬂoating inductor between the p and n terminals. Setting either Vn = 0 or Vp = 0, the proposed circuit can also be used as a grounded inductor. (ii) If Y1 = sC1 , Y2 = G2 are chosen for the circuit depicted in Fig. 3b, the short circuit admittance matrix of the ﬂoating capacitor is found to be gm sC1 [YC ] = ˛w G2 +1 −1 −1 +1 = sCf +1 −1 −1 +1 (5) where, Cf = ˛w gm C1 /G2 . In the ideal conditions, Cf = gm C1 /G2 . (iii) If Y1 = G1 , Y2 = G2 are chosen for the circuit depicted in Fig. 3b, the short circuit admittance matrix of the ﬂoating resistor is found to be [YR ] = ˛w gm G1 G2 +1 −1 −1 +1 = where, Rf = G2 /˛w gm G1 . Rf = G2 /gm G1 . 1 Rf In +1 −1 −1 +1 the (6) ideal conditions, It is important to note that the proposed simulator circuit can also simulate any one of the ﬂoating negative inductor (−L), the ﬂoating negative capacitor (−C) and the ﬂoating negative resistor (−R) by interchanging the p and n terminal inner connections of the BJT implementation of the CBTA. It is also possible to implement the grounded ±L, ±C and ±R simulator by grounding the p or n terminal of the CBTA. Since, the Vn and Vp are zero as seen in Eq. (1). Simulation of large positive and negative inductances without using large capacitors is possible due to the difference term in the denominator; this however needs attention to the passive sensitivities and tolerances of the passive components. Furthermore, simulation of large negative capacitances can easily be performed without needing for large capacitors since a capacitor ratio can be used as multiplying factor. Similar discussions are also valid for the resistor simulator. 4. Frequency limitations and simulation results In order to prove workability of the proposed structures, Pspice simulations are given. The ﬁrst simulations include the performance analysis of the CMOS implementation of CBTA. All CBTAs are simulated using the CMOS schematic implementation shown in Fig. 2, with 0.25 m TSMC level-7 CMOS technology parameters based on the dimensions of the CMOS transistor in Table 1 with DC power supply voltages equal to VDD = −VSS = 1.5 V for all simulations. Due to the non-idealities of the CBTA in Eq. (1), some discrepancies exhibit between the theoretical and the simulation results. These non-idealities are found by using the Spice simulations as below: εgm = 0.0184, εw = −0.035, εp = −0.0142, εn = 0.03 (7a) Fig. 4. The equivalent circuit of the CBTA. ωgm ∼ = 3700 Mrad/s, ωw ∼ = 5150 Mrad/s, ωp ∼ = 5020 Mrad/s, ωn ∼ = 5150 Mrad/s (7b) As a result, the maximum operating frequency of the CBTA is fmax = min{fp , fn , fgm , f } ∼ = 590 MHz. The CBTA has the parasitic resistances and capacitances as shown in Fig. 4. The parasitic resistance and capacitance values of the CBTA are also found by using the Spice simulations and given in Table 2. Fig. 5 shows that the magnitudes of the impedances of an ideal inductor and its simulator circuit can be made very close for a set of selected values over many decades. The simulated data is approximately equal to the theoretical data between 800 Hz and 45 MHz. The parasitic resistance of the inductor simulator is approximately 3 . Fig. 6 shows that the magnitudes of the impedances of an ideal capacitor and its simulator circuit can be made very close for a set of selected values over many decades; the simulated data is approximately equal to the theoretical data between 2 kHz and 7 MHz. The simulations also show that the proposed structure can simulate the ﬂoating capacitor from 200 times smaller capacitors. Fig. 7 shows that the magnitudes of the impedances of an ideal resistor and its simulator circuit can be made very close for a set of selected values over many decades. The simulated data is approximately equal to the theoretical data between 10 Hz and 100 MHz. The functionality of the proposed circuit is also demonstrated on the voltage- and current-mode band-pass ﬁlters design examples shown in Fig. 8. In this ﬁgure, the presented circuits replace with the inductor, capacitor and resistor simulator circuits shown in Fig. 3b. The all CBTAs are modeled using 0.25 m TSMC level-7 CMOS implementation shown in Fig. 2 with the dimensions of the CMOS transistor in Table 1. In the simulations, the voltage- and currentmode band-pass ﬁlters as explained above have cutoff frequencies of ωc = 1 Mrad/s (fc = 159.16 kHz) and bandwidths of 3.18 kHz. The inductance values L2 = L5 = C2 /gm G1 of the simulation example are found by substituting the values of gm = 0.5 mS, R1 = 1/G1 = 500 and C2 = 140 pF. The inductance value L3 = L4 = C2 /gm G1 of the simTable 2 The parasitic impedances of the CBTA. Parasitic impedances Values Rp Rn Rz Rw Cp Cn Cz 53 k 67 k 403 k 19.6 75 fF 990 fF 430 fF Rp , Cp , Rn , Cn , Rz , Cz , Rw are the parasitic resistances and capacitances of the CBTA. M. Sagbas / Int. J. Electron. Commun. (AEÜ) 65 (2011) 794–798 Fig. 5. The magnitude of the impedance of the proposed ﬂoating inductor (L = 1 mH). Fig. 6. The magnitude of the impedance of the proposed ﬂoating capacitor (C = 100 nF). Fig. 7. The magnitude of the impedance of the proposed resistor capacitor (R = 10 k). Fig. 8. The voltage- and current-mode band-pass ﬁlters. 797 798 M. Sagbas / Int. J. Electron. Commun. (AEÜ) 65 (2011) 794–798 Fig. 9. The magnitude and phase responses of the low-pass ﬁlter. ulation example are obtain by taking gm = 0.5 mS, R1 = 1/G1 = 5 k and C2 = 707 pF. The Pspice simulation results of the ﬁlter are given in Fig. 9. The deviations in the cut-off frequency from theoretical values are caused by the non-idealities of the CBTAs such as the current and voltage tracking errors. 5. Conclusion As a conclusion, a novel ideal ﬂoating inductor, capacitor and resistor simulator circuit shown in of Fig. 3 is proposed using CBTA. The proposed circuit has the following advantages: (i) It uses only one CBTA and two passive components. (ii) It uses a grounded capacitor, which is more suitable for IC fabrication [21]. (iii) Proposed simulator does not require any component-matching to arrive at Eq. (3) and provides independent control of L. (iv) It has low sensitivities. (v) The impedance value of the simulator can be adjusted electronically. Therefore it is also suitable for fully integrated ﬂoating immittance realization. (vi) The proposed circuit can simulate one of the ﬂoating ±L, ±C and ±R. (vii) The simulation results demonstrate that the theoretical and simulation results are in good agreement. References [1] Piwowarska E, Sidlarewicz A. Analysis of spiral inductor model in CMOS circuit. In: International Conference on Mixed Design of Integrated Circuits and System. 2006. p. 454–9. [2] Sagbas M, Ayten UE, Sedef H, Koksal M. Electronically tunable ﬂoating inductance simulator. AEU – International Journal of Electronics and Communications 2009;63(5):423–7. [3] Sedef H, Acar C. A new ﬂoating inductor circuit using differential voltage current conveyors. Frequenz 2000;54:123–5. [4] Keskin AU, Erhan H. CDBA-based synthetic ﬂoating inductance circuits with electronic tuning properties. ETRI Journal 2005;27:239–41. [5] Psychalinos C, Spanidou A. Current ampliﬁer based grounded and ﬂoating inductance simulators. AEU – International Journal of Electronics and Communications 2006;60(2):168–71. [6] Sedef H, Sagbas M, Acar C. Current-controllable fully-integrated inductor simulator using CCCIIs. International Journal of Electronics 2008;95(5):425–9. [7] Ferri G, Guerrini NC, Diqual M. CCII-based ﬂoating inductance simulator with compensated series resistance. Electronics Letters 2003;39:1560–2. [8] Minaei S, Yuce E, Cicekoglu O. A versatile active circuit for realizing ﬂoating inductance, capacitance, FDNR and admittance converter. Analog Integrated Circuits and Signal Processing 2006;47:199–202. [9] Cicekoglu O, Toker A, Kuntman H. Universal immittance function simulators using current conveyors. Computers & Electrical Engineering 2001;27:227–38. [10] Toker A, Özoğuz S, Acar C. CDBA-based fully-integrated gyrator circuit suitable for electronically tunable inductance simulation. AEÜ – International Journal of Electronics and Communications 2000;54(5):293–6. [11] Marcellis A, Ferri G, Guerrini NC, Scotti G, Stornelli V, Triﬁletti A. A novel lowvoltage low-power fully differential voltage and current gained CCII for ﬂoating impedance simulations. Microelectronics Journal 2009;40:20–5. [12] Orchard HJ. Inductorless ﬁlters. Electronics Letters 1966;2:224–5. [13] Pal K, Singh R. Inductorless current conveyor allpass ﬁlter using grounded capacitors. Electronics Letters 1982;18:47. [14] Kumar P, Senani R. New grounded simulated inductance circuit using a single PFTFN. Analog Integrated Circuits and Signal Processing 2010;62(1):105–12. [15] Çam U, Kaçar F, Cicekoglu O, Kuntman H, Kuntman A. Novel grounded parallel immittance simulator topologies employing single OTRA. AEU – International Journal of Electronics and Communications 2003;57(4):287–90. [16] Siripruchyanun M, Jaikla W. CMOS current-controlled current differencing transconductance ampliﬁer and applications to analog signal processing. AEU – International Journal of Electronics and Communications 2008;62(4):277–87. [17] Bruton LT. RC Active Circuits: Theory and Design. Englewood Cliffs: PrenticeHall; 1997. [18] Ayten UE, Sagbas M, Sedef H. Current-mode leapfrog ladder ﬁlters using a new active block. AEU – International Journal of Electronics and Communications 2010;64(6):503–11. [19] Ferri G, Guerrini NC. Low-Voltage Low-Power CMOS Current Conveyors. London: Kluwer Academic Publishers; 2003. [20] Kaewdang K, Surakampontorn W. On the realization of electronically current-tunable CMOS OTA. AEU – International Journal of Electronics and Communications 2007;61:300–6. [21] Bhusan M, Newcomb R. Grounding capacitors in integrated circuits. Electronics Letters 1967;3:148–9. Mehmet Sagbas received his BS degree in Electronics and Communication Engineering from Istanbul Technical University in 2000. He received his MS degree in Electronics Engineering from Fatih University in 2003. He received his PhD in Electronics Engineering Department at Yıldız Technical University in 2007. His research interests are active circuits, analog integrated circuit design, digital signal processing, image processing and active ﬁlter design. ID 446420 Title Componentreducedfloating±L,±Cand±Rsimulatorswithgroundedpassivecomponents http://fulltext.study/journal/481 http://FullText.Study Pages 5