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L E A D E R S H I P F O R T H E Design Support S o C G E N E R A T I O N www.umc.com F O U N D R Y Design Support Solutions Overview UMC's Design Support Solutions provide customers with a power design flow provides customers with a quick start for SoC practical and cost effective environment from RTL designs to GDS2 designs in advanced technologies. Cost effective DFM solutions tape-outs. The fundamental IP solutions include speed and area offer customers practical DFM methodologies that are seamlessly optimized standard cell libraries, I/O libraries with patented ESD compliant with current SoC designs flows. The foundry design protection, and embedded memory compilers. kits provide customers a quick and convenient analog design The platform-based IP solutions enable customers to easily environment with Optimized Capacitor Finder (OCF), Optimized develop specific products such as baseband chips, DTV controllers, Inductor Finder (OIF) and Optimized Transformer Finder (OTF). audio player controllers, digital camera controllers, etc. The low Fundamental IP Standard Cell Libraries UMC's standard cell libraries are optimized for UMC's advanced technologies including 90nm, 65nm, 40nm and 28nm. They provide rich features including multiple threshold voltage support, over-drive capabilities, density up to 3120 K-gate/mm2 at 28nm, multi-Vdd operations, and DFM compliance. 3200 ps Kgates/mm2 28nm 2500 1500 1000 500 0 90 250nm 60 40nm 2X smaller 65nm 130nm 90nm 65nm 40nm 30 90nm 130nm 250nm 180nm 0 Gate Density 35% faster 180nm 28nm Gate Delay Standard I/O Libraries With patented ESD protection techniques, UMC's standard I/O libraries provide the best functionality for SoC connectivity. In addition to 16mA fan-out driving, the I/O cells have a compact cell area at advanced nodes with Bonding Over Active Circuit (BOAC) support. Analog I/O & power cells are also available. Embedded Memory Compilers Embedded memories are generally required for SoC designs. UMC offers complete embedded memory generators for designers' convenience. These include single port SRAM, dual port SRAM, 1-port register files, 2-port register files, and ROM. The bit cells are built with HVt or RVt MOS transistors for low power designs in advanced technologies. Feature HV CIS Dual port SRAM - - 1-port Register File - 2-port Register File - Standard Cell Standard I/O Analog I/O Single Port SRAM ROM - 0.25um 0.18um 0.13um 90nm 65nm 55nm 40nm 28nm Analog IP DTV Platform based IP solutions PLL, USB, LVDS, ADC/DAC, Embedded Memory, HDMI, DDR2 With a complete platform based IP portfolio, customers are able to seamlessly deploy their required IP for specific SoC products, such as baseband SoCs, digital TV controllers, camera controllers and audio players. Digital Camera PLL, USB, LVDS, ADC/DAC, HDMI, SATA, Embedded Memory Baseband Mobile DDR, PLL, ADC/DAC, LVDS, USB, Embedded Memory Audio Players PLL, USB, LVDS, ADC/DAC, Embedded Memory Embedded Memory Macros In the modern SoC era, memory becomes an important and essential IP requirement for SoC design. UMC offers state-of-the-art embedded memory solutions to meet a variety of applications for 4C markets. High quality embedded non-volatile memory (eFuse, eOTP, eMTP, eEEPROM and eFlash) can be used for trimming, redundancy, data encryption, ID, coding and programming. In addition, UMC's proprietary URAMTM is an ideal solution for higher density memory requirements. The important features of URAM are smaller form factor, higher bandwidth/speed and lower power consumption compared to traditional embedded 6T-SRAM. These comprehensive IP solutions have been helping UMC customers maximize the performance potential of their SoC designs. UMC Embedded Memory Profiles UMC offers a comprehensive embedded memory profile. Customers have many options to help customize their SoC designs. Furthermore, UMC embedded memory is logic process compatible. The logic standard cell (SC) and I/O can be adopted directly into UMC embedded memory. eFlash/ EEPROM OTP D MTP eFuse URAMTM 0.35um 0.25um 0.18um 0.162um 0.13um 0.11um 90nm 65nm 40nm /0.153um /80um /55um AvailableDeveloping D 28nm Low Power Design Power Consumption Trends Leakage Power Dynamic Power Power Consumption With today's proliferation of low power applications, lowering energy consumption without sacrificing performance has become a critical concern for chip designers. UMC is committed to providing customers with the latest low power solutions, including low power and low leakage transistor options using advanced technologies. UMC develops multi Vt reference flows for low power designs. For advanced low power solutions, UMC provides low power kits as well as UMC libraries. Related reference EDA flows are also available upon request. These resources provide customers with a streamlined path to manufacturing, allowing UMC customers designing powerefficient SoC projects to capitalize on today's low power market opportunities.. 0.25um 0.18um 0.13um 90nm 65nm 40nm 28nm Technology Nodes Low Power Design Support To reduce overall power consumption, designers have to take action during both front-end and back-end design stages. As shown in the following chart, UMC is delivering convenient design solutions to support designers at each stage. Front-end design Multi VDD Multi Vth Low leakage process Voltage and frequency scaling Low power synthesis Power gating Clock gating Body bias 80% 60% 40% Back-end design 20% 20% 40% Leakage Power Saving 60% 80% Dynamic Power Saving Low Power Design Solutions Type Dynamic Power Voltage Island & Scaling Clock Gating & Frequency Scaling Multi-Vt Leakage Power Power Gating Body Bias Support Features Support 28nm 40nm 65nm 90nm 0.13um Þ Þ Þ Þ Þ Clock Gated F/F Þ Þ Þ Þ Þ Multi-Vt cells Þ Þ Þ Þ Þ Isolation cells, Retention F/F Headers / Footers, etc. Þ Þ Þ Þ Þ Þ Þ Þ Þ Þ Level Shifters w / Insulator Tapless cells Power & Timing Model @ 80% of Vdd Timing / Power Model (1) Timing and power models will be supported according to each customer's particular requirements. Low Power Reference Design Flow Advanced leakage reduction techniques are demonstrated with low power reference design flow examples – Multi-Vdd Design with established voltage island, Multi-Vt Optimization, and advanced power gating technologies. Multi-Vdd Designs Multi-Vdd designs are common in advanced technologies. In addition to data retention circuitry and timing considerations, UMC also supports designers to optimize voltage island placement surrounded by appropriate level shifters. The left is the example of the voltage island establishment. Level Shifter Cells Voltage Island Create Voltage Area Level Shifter Placement Multi-Vt Optimization Multi-Vt optimization can be performed using a two-phase leakage reduction flow. This enables optimized results for cell swaps, where low threshold voltage standard cells are replaced with high threshold voltage standard cells. The result is an 83% leakage power reduction in 0.13um technology. Design Implementation The Two-Phase Leakage reduction flow can be performed using Post Place & Route Leakage Power Optimization. PostPlace Leakage Power Optimizations Floor plan Si Driven Routing Post Route Leakage Power Optimization Physical Verification SoC Encounter 100% Experimental Results 83% leakage reduction (uW) FDK EDA Supported Tools 800 80% 600Synopsys 60% 400 40% 200 20% 0% Placement Spectre SpectreRF PostPlace Eldo HVT cells (%) EldoRF Routing LVT cells (%) PostRoute Opt. ADS Leakage power (uW) 0 Clock Speed 333Mhz Gate Count About 1 million gates Process UMC 0.13um 1P8M HSPICE Power Gating Solution UMC's power gating solution takes advantage of high threshold-voltage transistors or sleep transistors in circuit blocks that switch infrequently. This results in zero standby currents during the inactive state. The goal of power gating is to minimize leakage current by temporarily switching off power to blocks that are not required in the current operating mode. In our low power kits, we also designed isolation cells to prevent crowbar current. For the advanced purpose of retaining the internal state of the block during power down and restoring the state during power up, we also implemented retention Virtuoso XL registers in place of ordinary flip-flops. The result is a 70x leakage power reduction for 65nm technology through a proper design implementation strategy. Primary power net VDD VDD RR LS VDD1 VDD1 ISO VSS Primary ground net Top design PG Primary power net VSS Primary ground net u1 CORE TOP Foundry Design Kit (FDK) The Foundry Design Kit provides IC designers with an automatic design environment that eliminates unnecessary manual tasks and ensures successful mixed signal and RF IC tape-outs. The FDK includes parameterized cells (P Cell), which have a schematic layout to provide an automatic and complete design flow. Callback functions are also provided in the design flow to minimize data entry. In addition, UMC has worked with industry leading EDA tool partners to deliver fast and accurate 3D electromagnetic simulation tools for RF chip designs, including Virtual Capacitor Library (VCL), Virtual Inductor Library (VIL), and Virtual Transformer Library (VTL). UMC has also implemented Optimized Capacitor Finder (OCF), Optimized Inductor Finder (OIF), and Optimized Transformer Finder (OTF) tools deployed inside UMC’s Foundry Design Kit (FDK). These tools allow customers to make tradeoff decision between impedance and area, Q and area, or request a specified “flatness” of inductance within a given frequency range for ultra-wideband (UWB), WiMAX, and mobile TV design. Using OIF for Optimum Inductor Broad EDA Tool Support UMC works closely with leading EDA tool vendors to provide a convenient, productive and up-to-date work environment for designers. Tools are well supported by Logic Design Physical Verification Place & Route Verification Logic Simulation Cadence NC-Sim Mentor Model-Sim Synopsys UMC and its EDA partners throughout the EDI Cadence VCS Cadence ETS EPS Mentor CELTIC MVRC Talus Vortex entire design process, from RTL design to tapeout. Physical Design Logic Synthesis Cadence Magma Synopsys Magma RTL Compiler Talus Design Talus Design Quartz Rail Talus Power IC Compiler Design Compiler Synopsys Talus Power Synopsys Magma Assura QRC Calibre XRC Hercules StarRC-XT Quartz QuickCap PrimeTime PrimeRail FDK Integrated Flow EDA Vendors Schematic Entry Circuit Simulation IC Layout LVS/DRC/ LPE Composer Spectre SpecterRF Virtuoso Virtuoso XL Assura QRC Eldo Eldo RF ADS Calibre Calibre XRC ADS HSPICE Customer Support Partnership with ARM, Faraday & Virage • Enables prompt response from IP vendors • Feasibility assessment for customer’s requirements Free Libraries for cost-sensitive products • Foundry library programs UMC Online support environment • IP Master sourcing • IP Help Desk Hercules StarRC-XT www.umc.com F O U N D R Y New Customers For new customer inquiries, please direct all questions to [email protected] Worldwide Contacts Headquarters: UMC No. 3, Li-Hsin 2nd Road, Hsinchu Science Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-578-2258 Fax: 886-3-577-9392 Email: [email protected] L E A D E R S H I P F O R In China: UMC Beijing: Room #512, 5F, South Block, Raycom InfoTech Park, No.2, Kexueyuan South Road, Zhongguancun, Haidian District, Beijing 100190, China Tel: 86-10-59822250 86-18913138053 Fax: 86-10-59822588 HeJian Technology (Suzhou): No. 333, Xinghua Street, Suzhou Industrial Park, Suzhou, Jiangsu Province 215025, China Tel: 86-512-65931299 Fax: 86-512-62530172 T H E S o C G E N E R A T I O N In Japan: UMC Group Japan 15F Akihabara Centerplace Bldg., 1 Kanda Aioi-Cho Chiyoda-Ku Tokyo 101-0029 Japan Tel : 81-3-5294-2701 Fax: 81-3-5294-2707 In Singapore: UMC-SG No. 3, Pasir Ris Drive 12, Singapore 519528 Tel: 65-6213-0018 Fax: 65-6213-0005 In North America: UMC USA 488 De Guigne Drive, Sunnyvale, CA 94085, USA Tel: 1-408-523-7800 Fax: 1-408-733-8090 In Europe: UMC Europe BV De entree 77 1101 BH Amsterdam Zuidoost The Netherlands Tel: 31-(0)20-5640950 Fax: 31-(0)20-6977826 In Korea: UMC Korea 1117, Hanshin Intervally24, 322, Teheran-ro, Gangnam-gu, Seoul, Korea Tel: 82-2-2183-1790 Fax: 82-2-2183-1794 Email:[email protected] For more information: visit www.umc.com or e-mail [email protected] 1506