Download COMBINATIONAL CIRCUITS

COMBINATIONAL CIRCUITS
Combinational PLDs
(Programmable Logic Devices)
Basic Configuration of three PLDs
Boolean variables
INPUTS
Fixed
AND array
(decoder)
Programmable
OR array
OUTPUTS
Programmable Read-Only Memory (PROM)
INPUTS
Programmable
AND array
Fixed
OR array
OUTPUTS
Programmable Array Logic (PAL)
Programmable
AND array
INPUTS
Programmable
OR array
OUTPUTS
(Field) Programmable Logic Array (PLA)
1
©Loberg
COMBINATIONAL CIRCUITS
Two-level AND-OR Arrays
Combinational PLDs
(Programmable Logic Devices)
F (C , B , A ) = CBA + C B
AND
A
B
+V
C
A
B
C
A
B
C
F
F
F1
AND + V
OR
B
C
Multiple functions
Simplified equivalent circuit for
two-level AND-OR array
2
©Loberg
COMBINATIONAL CIRCUITS
Combinational PLDs
(Programmable Logic Devices)
Field-programmable AND and OR Arrays
Field-programmable logic elements are devices that contain uncommitted
AND/OR arrays that are (programmed) configured by the designer.
+V
A
F (C , B , A )
+V
A
B
B
C
C
Unprogrammed AND array
F (C , B , A ) = CB A
Fuse can be "blown" by
passing a high current
through it.
3
©Loberg
COMBINATIONAL CIRCUITS
Combinational PLDs
(Programmable Logic Devices)
Field-programmable AND and OR Arrays
F (P1 , P2 , P3 ) = P1 + P3
P1
P2
P3
F (P1 , P2 , P3 )
Unprogrammed OR array
P1
P2
P3
F
Programmed OR array
P1
P2
P3
P1 + P3
4
©Loberg
COMBINATIONAL CIRCUITS
Output Polarity Options
Combinational PLDs
(Programmable Logic Devices)
I1
Ik
Active high
Active low
Complementary
outputs
Programmable
polarity
P1 Pm
+V
5
©Loberg
COMBINATIONAL CIRCUITS
Combinational PLDs
(Programmable Logic Devices)
Bidirectional Pins and Feed back Lines
I1
Ik
Feedback
IOm
Three-state driver
6
©Loberg
COMBINATIONAL CIRCUITS
PLA (Programmable Logic Array)
Combinational PLDs
(Programmable Logic Devices)
If we use ROM to implement the Boolean function we will waste the silicon area.
All Input combinations are implemented in ROM (address decoder).
Usually we must implement
only few minterms.
⇒
⇒
Only few OR-operators.
A
B
C
A⋅ B
The standard SOP format has few
OR operations and several input
variables.
A⋅ C
B ⋅C
A⋅ B ⋅C
PLA saves silicon area
F1 = B ⋅ A + C ⋅ A + C ⋅ B ⋅ A
F2 = C ⋅ A + B ⋅ C
C B A
C B A
Inverted
output
0
1
F1
F2
7
©Loberg
COMBINATIONAL CIRCUITS
PLA (Programmable Logic Array)
Combinational PLDs
(Programmable Logic Devices)
Example (Old Signetics FPLA 82S100 Field Programmable Logic Array)
Vcc
82S100 is 16X48X8 Fuse Programmable
Logic Array circuit
fuse
I0
I1
I15
P0
Vcc
fuse
P1
P47
S0
F0
S1
F1
S7
F7
8
©Loberg
COMBINATIONAL CIRCUITS
Combinational PLDs
(Programmable Logic Devices)
Example of FPLA Device
PLA (Programmable Logic Array)
I0
Philips PLS153A
I7
I/O
B9
B0 9
©Loberg
COMBINATIONAL CIRCUITS
PAL (Programmable Array Logic)
Combinational PLDs
(Programmable Logic Devices)
Product term
F1 = A ⋅ B ⋅ C + A ⋅ B ⋅ C + D
1
Fixed OR array
F1
2
3
A
I1
Feedback
4
5
B
I2
6
7
8
C
I3
F2
F3
9
10
11
F4
12
D
I4
10
©Loberg
COMBINATIONAL CIRCUITS
Combinational PLDs
(Programmable Logic Devices)
PAL (Programmable Array Logic)
Example of PAL Device
AMD PAL18P8
11
©Loberg
COMBINATIONAL CIRCUITS
PAL (Programmable Array Logic)
Combinational PLDs
(Programmable Logic Devices)
Combinational logic + D-flip-flops
(for sequential circuit applications)
One example : PEEL 22CV10A Electrically Erasable
1 of 10 Macro cells
I
I/O
AND
array
I
MACRO
CELL
OE
SP AC
SP Synchronous Preset
Common Clock AC Asynchronous Clear
OE Output Enable
12
©Loberg
COMBINATIONAL CIRCUITS
Combinational PLDs
(Programmable Logic Devices)
PAL16R4AM
13
©Loberg
COMBINATIONAL CIRCUITS
ROM implementation
Combinational PLDs
(Programmable Logic Devices)
2m × n
m inputs (address Ai = 2m combinations)
Linear, one-dimensional
addressing
Address lines
A0
A1
m× 2
Word-lines
m
decoder
n outputs (data)
ROM
W0
W1
memory core
Encoder
Memory
matrix
Input variables
Am − 2
Am −1
m-bit address
ROM cells
WM − 2
WM −1
2m = M
Dn −1 Dn − 2
Outputs
D1 D0
n-bit data
Data lines
14
©Loberg
COMBINATIONAL CIRCUITS
ROM implementation
Combinational PLDs
(Programmable Logic Devices)
Canonical SOP form of the Boolean function : Minterms
Address locations
A0
D0
10 Input variables
1k x 8
8 Outputs
D7
A9
Select lines
Output Enable lines
15
©Loberg
COMBINATIONAL CIRCUITS
ROM implementation
Combinational PLDs
(Programmable Logic Devices)
Example
13 input variables In12 - In0
8 different switching functions F7-F0
A12 − A0
P
E
G
13
VCC VPP
M27C64A
8
Q0 − Q7
Direction during program
VSS
Logic diagram
ROM organized as 8Kb x 8 (8192x8bits)
For example M27C64A UV EPROM
VCC
Supply voltage +5V (10%)
VSS
Ground
VPP
Program Supply 12.5V +- 0.25V
P
Program
E
Chip Enable
Output Enable
G
A12 − A0 Address Inputs
Q7 − Q0 Data Outputs
Signal Names
16
©Loberg
COMBINATIONAL CIRCUITS
ROM implementation
Combinational PLDs
(Programmable Logic Devices)
Example
VCC +5V
In0
10
9
A0
8
11
13
15
5
4
17
3
In8
25
In9
In10
24
21
In11
23
2
14
F0
12
7
6
In7
In12
M27C64A
Q0
VPP
A12
A7
1
28
A11
G
18
VPP
P
A12
19
F7
1
27
NC 26
E
G
P
A8
16
Q7
VCC
20
22
Implemented combinational logic
Q0
Q2
Q7
A0
VSS
14
15
E
NC
A9
A10
Q3
Dip Connections
17
©Loberg
COMBINATIONAL CIRCUITS
ROM implementation
Universal Programmer
UV Eraser
18
COMBINATIONAL CIRCUITS
Programming Software
Combinational PLDs
(Programmable Logic Devices)
Examples (free download)
ATMEL : WinCUPL software
SPLDs
Simple Programmable Logic Devices
(16V8, 20V8, 22V10)
ATF22LV10ZQZ
CPLDs
Complex Programmable Logic Devices
ATF15xxBE family
ATV750B
XILINX : Xilinx ISE Design Suite (Schematics, VHDL, Verilog)
CPLDs
Complex Programmable Logic Devices
XC95xx family
FPGAs
Field Programmable Gate Arrays
Virtex, Spartan,..
19
The End
20